[Qemu-devel] [Bug 1843254] [NEW] HCR.TID3 traps are not implemented

[Qemu-devel] [Bug 1843254] [NEW] HCR.TID3 traps are not implemented

[Udo Steinberg]

Public bug reported:

On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
However, setting that HCR bit has no effect and accesses to those ID
registers are not trapped to EL2 with an EC syndrome value of 0x18.

** Affects: qemu
     Importance: Undecided
         Status: New


** Tags: arm virtualization

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Title:
  HCR.TID3 traps are not implemented

Status in QEMU:
  New

Bug description:
  On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
  which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
  However, setting that HCR bit has no effect and accesses to those ID
  registers are not trapped to EL2 with an EC syndrome value of 0x18.

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[Qemu-devel] [Bug 1843254] Re: HCR.TID3 traps are not implemented

[Peter Maydell]

Yes, we don't currently implement most of the 'trap system register
access' bits in HCR_EL2. Last time I checked we were missing TID0 TID1
TID2 TID3 TIDCP TAC TSW TPC TPU TTLB TVM TRVM TDZ, but it's possible
we've implemented one or two of those since then.


** Changed in: qemu
       Status: New => Confirmed

** Summary changed:

- HCR.TID3 traps are not implemented
+ arm emulation of HCR.TID3 traps are not implemented

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Title:
  arm emulation of HCR.TID3 traps are not implemented

Status in QEMU:
  Confirmed

Bug description:
  On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
  which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
  However, setting that HCR bit has no effect and accesses to those ID
  registers are not trapped to EL2 with an EC syndrome value of 0x18.

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[Bug 1843254] Re: arm emulation of HCR.TID3 traps are not implemented

[Peter Maydell]

TID3 trapping should be mostly fixed for 4.2 -- we will trap accesses to
all the coprocessor/sysreg ID registers that TID3 covers. Trapping of
aarch32 MVFR* (which are accessed via vmrs) will not make it into this
release, but should be in 5.0.


** Changed in: qemu
       Status: Confirmed => In Progress

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Title:
  arm emulation of HCR.TID3 traps are not implemented

Status in QEMU:
  In Progress

Bug description:
  On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
  which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
  However, setting that HCR bit has no effect and accesses to those ID
  registers are not trapped to EL2 with an EC syndrome value of 0x18.

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[Bug 1843254] Re: arm emulation of HCR.TID3 traps are not implemented

[Peter Maydell]

The last bit of TID3 trapping is now in QEMU git master and will be in
5.0.


** Changed in: qemu
       Status: In Progress => Fix Committed

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Title:
  arm emulation of HCR.TID3 traps are not implemented

Status in QEMU:
  Fix Committed

Bug description:
  On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
  which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
  However, setting that HCR bit has no effect and accesses to those ID
  registers are not trapped to EL2 with an EC syndrome value of 0x18.

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[Bug 1843254] Re: arm emulation of HCR.TID3 traps are not implemented

[Thomas Huth]

** Changed in: qemu
       Status: Fix Committed => Fix Released

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Title:
  arm emulation of HCR.TID3 traps are not implemented

Status in QEMU:
  Fix Released

Bug description:
  On ARM (aarch64), HCR_EL2.TID3 [bit18] is supposed to trap ID group 3,
  which includes the ID_AA64{PFR,DFR,ISAR,MMFR,AFR}*_EL1 registers.
  However, setting that HCR bit has no effect and accesses to those ID
  registers are not trapped to EL2 with an EC syndrome value of 0x18.

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