From: Cathy Zhang <cathy.zhang@intel.com>
To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org, Cathy Zhang <cathy.zhang@intel.com>
Subject: [PATCH 2/3] i386: Add macro for stibp
Date: Sat, 12 Oct 2019 15:00:37 +0800 [thread overview]
Message-ID: <1570863638-22272-3-git-send-email-cathy.zhang@intel.com> (raw)
In-Reply-To: <1570863638-22272-1-git-send-email-cathy.zhang@intel.com>
stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955
Add a macro for it to allow CPU models report it when host supports.
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e757149..c47bcb5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -717,6 +717,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
+#define CPUID_7_0_EDX_STIBP (1U << 27) /* Single Thread Indirect Branch Predictors */
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
--
1.8.3.1
next prev parent reply other threads:[~2019-10-12 12:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-12 7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
2019-10-12 7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
2019-10-12 7:00 ` Cathy Zhang [this message]
2019-10-12 7:00 ` [PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
2019-10-12 15:04 ` [PATCH 0/3] Add CPU model for intel processor Cooper Lake no-reply
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