* [PULL 01/39] target/i386: log MCE guest and host addresses
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 02/39] mc146818rtc: fix timer interrupt reinjection Paolo Bonzini
` (39 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Mario Smarduch
From: Mario Smarduch <msmarduch@digitalocean.com>
Patch logs MCE AO, AR messages injected to guest or taken by QEMU itself.
We print the QEMU address for guest MCEs, helps on hypervisors that have
another source of MCE logging like mce log, and when they go missing.
For example we found these QEMU logs:
September 26th 2019, 17:36:02.309 Droplet-153258224: Guest MCE Memory Error at qemu addr 0x7f8ce14f5000 and guest 3d6f5000 addr of type BUS_MCEERR_AR injected qemu-system-x86_64 amsN ams3nodeNNNN
September 27th 2019, 06:25:03.234 Droplet-153258224: Guest MCE Memory Error at qemu addr 0x7f8ce14f5000 and guest 3d6f5000 addr of type BUS_MCEERR_AR injected qemu-system-x86_64 amsN ams3nodeNNNN
The first log had a corresponding mce log entry, the second didnt (logging
thresholds) we can infer from second entry same PA and mce type.
Signed-off-by: Mario Smarduch <msmarduch@digitalocean.com>
Message-Id: <20191009164459.8209-3-msmarduch@digitalocean.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/kvm.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 8c73438..0e3da99 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -592,9 +592,9 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
(MCM_ADDR_PHYS << 6) | 0xc, flags);
}
-static void hardware_memory_error(void)
+static void hardware_memory_error(void *host_addr)
{
- fprintf(stderr, "Hardware memory error!\n");
+ error_report("QEMU got Hardware memory error at addr %p", host_addr);
exit(1);
}
@@ -618,15 +618,34 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
kvm_hwpoison_page_add(ram_addr);
kvm_mce_inject(cpu, paddr, code);
+
+ /*
+ * Use different logging severity based on error type.
+ * If there is additional MCE reporting on the hypervisor, QEMU VA
+ * could be another source to identify the PA and MCE details.
+ */
+ if (code == BUS_MCEERR_AR) {
+ error_report("Guest MCE Memory Error at QEMU addr %p and "
+ "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
+ addr, paddr, "BUS_MCEERR_AR");
+ } else {
+ warn_report("Guest MCE Memory Error at QEMU addr %p and "
+ "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
+ addr, paddr, "BUS_MCEERR_AO");
+ }
+
return;
}
- fprintf(stderr, "Hardware memory error for memory used by "
- "QEMU itself instead of guest system!\n");
+ if (code == BUS_MCEERR_AO) {
+ warn_report("Hardware memory error at addr %p of type %s "
+ "for memory used by QEMU itself instead of guest system!",
+ addr, "BUS_MCEERR_AO");
+ }
}
if (code == BUS_MCEERR_AR) {
- hardware_memory_error();
+ hardware_memory_error(addr);
}
/* Hope we are lucky for AO MCE */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 02/39] mc146818rtc: fix timer interrupt reinjection
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
2019-10-24 14:03 ` [PULL 01/39] target/i386: log MCE guest and host addresses Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0 Paolo Bonzini
` (38 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Marcelo Tosatti
From: Marcelo Tosatti <mtosatti@redhat.com>
commit 369b41359af46bded5799c9ef8be2b641d92e043 broke timer interrupt
reinjection when there is no period change by the guest.
In that case, old_period is 0, which ends up zeroing irq_coalesced
(counter of reinjected interrupts).
The consequence is Windows 7 is unable to synchronize time via NTP.
Easily reproducible by playing a fullscreen video with cirrus and VNC.
Fix by not updating s->irq_coalesced when old_period is 0.
V2: reorganize code (Paolo Bonzini)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Message-Id: <20191010123008.GA19158@amt.cnet>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/timer/mc146818rtc.c | 53 +++++++++++++++++++++++++-------------------------
1 file changed, 27 insertions(+), 26 deletions(-)
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 6cb3787..0e7cf97 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -203,24 +203,28 @@ periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period)
period = rtc_periodic_clock_ticks(s);
- if (period) {
- /* compute 32 khz clock */
- cur_clock =
- muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
+ if (!period) {
+ s->irq_coalesced = 0;
+ timer_del(s->periodic_timer);
+ return;
+ }
- /*
- * if the periodic timer's update is due to period re-configuration,
- * we should count the clock since last interrupt.
- */
- if (old_period) {
- int64_t last_periodic_clock, next_periodic_clock;
-
- next_periodic_clock = muldiv64(s->next_periodic_time,
- RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
- last_periodic_clock = next_periodic_clock - old_period;
- lost_clock = cur_clock - last_periodic_clock;
- assert(lost_clock >= 0);
- }
+ /* compute 32 khz clock */
+ cur_clock =
+ muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
+
+ /*
+ * if the periodic timer's update is due to period re-configuration,
+ * we should count the clock since last interrupt.
+ */
+ if (old_period) {
+ int64_t last_periodic_clock, next_periodic_clock;
+
+ next_periodic_clock = muldiv64(s->next_periodic_time,
+ RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
+ last_periodic_clock = next_periodic_clock - old_period;
+ lost_clock = cur_clock - last_periodic_clock;
+ assert(lost_clock >= 0);
/*
* s->irq_coalesced can change for two reasons:
@@ -251,22 +255,19 @@ periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period)
rtc_coalesced_timer_update(s);
}
} else {
- /*
+ /*
* no way to compensate the interrupt if LOST_TICK_POLICY_SLEW
* is not used, we should make the time progress anyway.
*/
lost_clock = MIN(lost_clock, period);
}
+ }
- assert(lost_clock >= 0 && lost_clock <= period);
+ assert(lost_clock >= 0 && lost_clock <= period);
- next_irq_clock = cur_clock + period - lost_clock;
- s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1;
- timer_mod(s->periodic_timer, s->next_periodic_time);
- } else {
- s->irq_coalesced = 0;
- timer_del(s->periodic_timer);
- }
+ next_irq_clock = cur_clock + period - lost_clock;
+ s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1;
+ timer_mod(s->periodic_timer, s->next_periodic_time);
}
static void rtc_periodic_timer(void *opaque)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
2019-10-24 14:03 ` [PULL 01/39] target/i386: log MCE guest and host addresses Paolo Bonzini
2019-10-24 14:03 ` [PULL 02/39] mc146818rtc: fix timer interrupt reinjection Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 19:54 ` Aleksandar Markovic
2019-10-24 14:03 ` [PULL 04/39] i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenment Paolo Bonzini
` (37 subsequent siblings)
40 siblings, 1 reply; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexander Shopov
From: Alexander Shopov <ash@kambanaria.org>
Signed-off-by: Alexander Shopov <ash@kambanaria.org>
Message-Id: <20191019120534.27479-2-ash@kambanaria.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
po/bg.po | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/po/bg.po b/po/bg.po
index 3d8c353..98c57e5 100644
--- a/po/bg.po
+++ b/po/bg.po
@@ -1,14 +1,14 @@
# Bulgarian translation of qemu po-file.
-# Copyright (C) 2016 Alexander Shopov <ash@kambanaria.org>
+# Copyright (C) 2016, 2019 Alexander Shopov <ash@kambanaria.org>
# This file is distributed under the same license as the qemu package.
-# Alexander Shopov <ash@kambanaria.org>, 2016.
+# Alexander Shopov <ash@kambanaria.org>, 2016, 2019.
#
msgid ""
msgstr ""
-"Project-Id-Version: QEMU 2.6.50\n"
+"Project-Id-Version: QEMU 4.1.0\n"
"Report-Msgid-Bugs-To: qemu-devel@nongnu.org\n"
"POT-Creation-Date: 2018-07-18 07:56+0200\n"
-"PO-Revision-Date: 2016-06-09 15:54+0300\n"
+"PO-Revision-Date: 2019-10-19 13:14+0200\n"
"Last-Translator: Alexander Shopov <ash@kambanaria.org>\n"
"Language-Team: Bulgarian <dict@ludost.net>\n"
"Language: bg\n"
@@ -66,7 +66,7 @@ msgid "Detach Tab"
msgstr "Към самостоятелен подпрозорец"
msgid "Show Menubar"
-msgstr ""
+msgstr "Лента за менюто"
msgid "_Machine"
msgstr "_Машина"
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0
2019-10-24 14:03 ` [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0 Paolo Bonzini
@ 2019-10-24 19:54 ` Aleksandar Markovic
2019-10-24 20:19 ` Paolo Bonzini
0 siblings, 1 reply; 51+ messages in thread
From: Aleksandar Markovic @ 2019-10-24 19:54 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Alexander Shopov, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1710 bytes --]
24.10.2019. 16.26, "Paolo Bonzini" <pbonzini@redhat.com> је написао/ла:
>
> From: Alexander Shopov <ash@kambanaria.org>
>
> Signed-off-by: Alexander Shopov <ash@kambanaria.org>
> Message-Id: <20191019120534.27479-2-ash@kambanaria.org>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> po/bg.po | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
How come my "Reviewed-by" is not recorded here? It is not a big deal, just
curious how it happened.
A.
> diff --git a/po/bg.po b/po/bg.po
> index 3d8c353..98c57e5 100644
> --- a/po/bg.po
> +++ b/po/bg.po
> @@ -1,14 +1,14 @@
> # Bulgarian translation of qemu po-file.
> -# Copyright (C) 2016 Alexander Shopov <ash@kambanaria.org>
> +# Copyright (C) 2016, 2019 Alexander Shopov <ash@kambanaria.org>
> # This file is distributed under the same license as the qemu package.
> -# Alexander Shopov <ash@kambanaria.org>, 2016.
> +# Alexander Shopov <ash@kambanaria.org>, 2016, 2019.
> #
> msgid ""
> msgstr ""
> -"Project-Id-Version: QEMU 2.6.50\n"
> +"Project-Id-Version: QEMU 4.1.0\n"
> "Report-Msgid-Bugs-To: qemu-devel@nongnu.org\n"
> "POT-Creation-Date: 2018-07-18 07:56+0200\n"
> -"PO-Revision-Date: 2016-06-09 15:54+0300\n"
> +"PO-Revision-Date: 2019-10-19 13:14+0200\n"
> "Last-Translator: Alexander Shopov <ash@kambanaria.org>\n"
> "Language-Team: Bulgarian <dict@ludost.net>\n"
> "Language: bg\n"
> @@ -66,7 +66,7 @@ msgid "Detach Tab"
> msgstr "Към самостоятелен подпрозорец"
>
> msgid "Show Menubar"
> -msgstr ""
> +msgstr "Лента за менюто"
>
> msgid "_Machine"
> msgstr "_Машина"
> --
> 1.8.3.1
>
>
>
[-- Attachment #2: Type: text/html, Size: 2896 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0
2019-10-24 19:54 ` Aleksandar Markovic
@ 2019-10-24 20:19 ` Paolo Bonzini
0 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 20:19 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: Alexander Shopov, qemu-devel
On 24/10/19 21:54, Aleksandar Markovic wrote:
>
> 24.10.2019. 16.26, "Paolo Bonzini" <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>> је написао/ла:
>>
>> From: Alexander Shopov <ash@kambanaria.org <mailto:ash@kambanaria.org>>
>>
>> Signed-off-by: Alexander Shopov <ash@kambanaria.org
> <mailto:ash@kambanaria.org>>
>> Message-Id: <20191019120534.27479-2-ash@kambanaria.org
> <mailto:20191019120534.27479-2-ash@kambanaria.org>>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
>> ---
>> po/bg.po | 10 +++++-----
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>
> How come my "Reviewed-by" is not recorded here? It is not a big deal,
> just curious how it happened.
I had applied it locally before you sent your review.
Paolo
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PULL 04/39] i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenment
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (2 preceding siblings ...)
2019-10-24 14:03 ` [PULL 03/39] Updated Bulgarian translation (19) - 4.1.0 Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 05/39] Do not use %m in common code to print error messages Paolo Bonzini
` (36 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Vitaly Kuznetsov
From: Vitaly Kuznetsov <vkuznets@redhat.com>
Hyper-V TLFS specifies this enlightenment as:
"NoNonArchitecturalCoreSharing - Indicates that a virtual processor will never
share a physical core with another virtual processor, except for virtual
processors that are reported as sibling SMT threads. This can be used as an
optimization to avoid the performance overhead of STIBP".
However, STIBP is not the only implication. It was found that Hyper-V on
KVM doesn't pass MD_CLEAR bit to its guests if it doesn't see
NoNonArchitecturalCoreSharing bit.
KVM reports NoNonArchitecturalCoreSharing in KVM_GET_SUPPORTED_HV_CPUID to
indicate that SMT on the host is impossible (not supported of forcefully
disabled).
Implement NoNonArchitecturalCoreSharing support in QEMU as tristate:
'off' - the feature is disabled (default)
'on' - the feature is enabled. This is only safe if vCPUS are properly
pinned and correct topology is exposed. As CPU pinning is done outside
of QEMU the enablement decision will be made on a higher level.
'auto' - copy KVM setting. As during live migration SMT settings on the
source and destination host may differ this requires us to add a migration
blocker.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20191018163908.10246-1-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
docs/hyperv.txt | 13 +++++++++++++
target/i386/cpu.c | 2 ++
target/i386/cpu.h | 2 ++
target/i386/hyperv-proto.h | 1 +
target/i386/kvm.c | 26 ++++++++++++++++++++++++++
5 files changed, 44 insertions(+)
diff --git a/docs/hyperv.txt b/docs/hyperv.txt
index 8fdf25c..6518b71 100644
--- a/docs/hyperv.txt
+++ b/docs/hyperv.txt
@@ -184,6 +184,19 @@ enabled.
Requires: hv-vpindex, hv-synic, hv-time, hv-stimer
+3.17. hv-no-nonarch-coresharing=on/off/auto
+===========================================
+This enlightenment tells guest OS that virtual processors will never share a
+physical core unless they are reported as sibling SMT threads. This information
+is required by Windows and Hyper-V guests to properly mitigate SMT related CPU
+vulnerabilities.
+When the option is set to 'auto' QEMU will enable the feature only when KVM
+reports that non-architectural coresharing is impossible, this means that
+hyper-threading is not supported or completely disabled on the host. This
+setting also prevents migration as SMT settings on the destination may differ.
+When the option is set to 'on' QEMU will always enable the feature, regardless
+of host setup. To keep guests secure, this can only be used in conjunction with
+exposing correct vCPU topology and vCPU pinning.
4. Development features
========================
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 47200b4..6c87c99 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6174,6 +6174,8 @@ static Property x86_cpu_properties[] = {
HYPERV_FEAT_IPI, 0),
DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
HYPERV_FEAT_STIMER_DIRECT, 0),
+ DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
+ hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index cedb5bc..c50a9c7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -24,6 +24,7 @@
#include "cpu-qom.h"
#include "hyperv-proto.h"
#include "exec/cpu-defs.h"
+#include "qapi/qapi-types-common.h"
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
@@ -1614,6 +1615,7 @@ struct X86CPU {
bool hyperv_synic_kvm_only;
uint64_t hyperv_features;
bool hyperv_passthrough;
+ OnOffAuto hyperv_no_nonarch_cs;
bool check_cpuid;
bool enforce_cpuid;
diff --git a/target/i386/hyperv-proto.h b/target/i386/hyperv-proto.h
index cffac10..056a305 100644
--- a/target/i386/hyperv-proto.h
+++ b/target/i386/hyperv-proto.h
@@ -63,6 +63,7 @@
#define HV_CLUSTER_IPI_RECOMMENDED (1u << 10)
#define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11)
#define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14)
+#define HV_NO_NONARCH_CORESHARING (1u << 18)
/*
* Basic virtualized MSRs
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 0e3da99..49a3011 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1227,6 +1227,16 @@ static int hyperv_handle_properties(CPUState *cs,
}
}
+ if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
+ env->features[FEAT_HV_RECOMM_EAX] |= HV_NO_NONARCH_CORESHARING;
+ } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
+ c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
+ if (c) {
+ env->features[FEAT_HV_RECOMM_EAX] |=
+ c->eax & HV_NO_NONARCH_CORESHARING;
+ }
+ }
+
/* Features */
r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
@@ -1340,6 +1350,7 @@ free:
}
static Error *hv_passthrough_mig_blocker;
+static Error *hv_no_nonarch_cs_mig_blocker;
static int hyperv_init_vcpu(X86CPU *cpu)
{
@@ -1359,6 +1370,21 @@ static int hyperv_init_vcpu(X86CPU *cpu)
}
}
+ if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
+ hv_no_nonarch_cs_mig_blocker == NULL) {
+ error_setg(&hv_no_nonarch_cs_mig_blocker,
+ "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
+ " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
+ " make sure SMT is disabled and/or that vCPUs are properly"
+ " pinned)");
+ ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ error_free(hv_no_nonarch_cs_mig_blocker);
+ return ret;
+ }
+ }
+
if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
/*
* the kernel doesn't support setting vp_index; assert that its value
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 05/39] Do not use %m in common code to print error messages
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (3 preceding siblings ...)
2019-10-24 14:03 ` [PULL 04/39] i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenment Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 06/39] memory-device: simplify Makefile.objs conditions Paolo Bonzini
` (35 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Thomas Huth
From: Thomas Huth <thuth@redhat.com>
The %m format specifier is an extension from glibc - and when compiling
QEMU for NetBSD, the compiler correctly complains, e.g.:
/home/qemu/qemu-test.ELjfrQ/src/util/main-loop.c: In function 'sigfd_handler':
/home/qemu/qemu-test.ELjfrQ/src/util/main-loop.c:64:13: warning: %m is only
allowed in syslog(3) like functions [-Wformat=]
printf("read from sigfd returned %zd: %m\n", len);
^
Let's use g_strerror() here instead, which is an easy-to-use wrapper
around the thread-safe strerror_r() function.
While we're at it, also convert the "printf()" in main-loop.c into
the preferred "error_report()".
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20191018130716.25438-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/misc/tmp421.c | 4 ++--
util/main-loop.c | 3 ++-
util/systemd.c | 4 ++--
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c
index 9f04470..c0bc150 100644
--- a/hw/misc/tmp421.c
+++ b/hw/misc/tmp421.c
@@ -120,7 +120,7 @@ static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name,
int tempid;
if (sscanf(name, "temperature%d", &tempid) != 1) {
- error_setg(errp, "error reading %s: %m", name);
+ error_setg(errp, "error reading %s: %s", name, g_strerror(errno));
return;
}
@@ -160,7 +160,7 @@ static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name,
}
if (sscanf(name, "temperature%d", &tempid) != 1) {
- error_setg(errp, "error reading %s: %m", name);
+ error_setg(errp, "error reading %s: %s", name, g_strerror(errno));
return;
}
diff --git a/util/main-loop.c b/util/main-loop.c
index e3eaa55..eda63fe 100644
--- a/util/main-loop.c
+++ b/util/main-loop.c
@@ -61,7 +61,8 @@ static void sigfd_handler(void *opaque)
}
if (len != sizeof(info)) {
- printf("read from sigfd returned %zd: %m\n", len);
+ error_report("read from sigfd returned %zd: %s", len,
+ g_strerror(errno));
return;
}
diff --git a/util/systemd.c b/util/systemd.c
index d22e86c..1dd0367 100644
--- a/util/systemd.c
+++ b/util/systemd.c
@@ -60,8 +60,8 @@ unsigned int check_socket_activation(void)
* and we should exit.
*/
error_report("Socket activation failed: "
- "invalid file descriptor fd = %d: %m",
- fd);
+ "invalid file descriptor fd = %d: %s",
+ fd, g_strerror(errno));
exit(EXIT_FAILURE);
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 06/39] memory-device: simplify Makefile.objs conditions
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (4 preceding siblings ...)
2019-10-24 14:03 ` [PULL 05/39] Do not use %m in common code to print error messages Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 07/39] hw/virtio: Factorize virtio-mmio headers Paolo Bonzini
` (34 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel
hw/mem/ is only included if CONFIG_MEM_DEVICE is true, so we need not
specify the condition again in hw/mem/Makefile.objs.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/mem/Makefile.objs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/Makefile.objs b/hw/mem/Makefile.objs
index 3e2f7c5..56345be 100644
--- a/hw/mem/Makefile.objs
+++ b/hw/mem/Makefile.objs
@@ -1,3 +1,3 @@
common-obj-$(CONFIG_DIMM) += pc-dimm.o
-common-obj-$(CONFIG_MEM_DEVICE) += memory-device.o
+common-obj-y += memory-device.o
common-obj-$(CONFIG_NVDIMM) += nvdimm.o
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 07/39] hw/virtio: Factorize virtio-mmio headers
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (5 preceding siblings ...)
2019-10-24 14:03 ` [PULL 06/39] memory-device: simplify Makefile.objs conditions Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 08/39] hw/i386/pc: rename functions shared with non-PC machines Paolo Bonzini
` (33 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Put QOM and main struct definition in a separate header file, so it
can be accessed from other components.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/virtio/virtio-mmio.c | 48 +--------------------------
include/hw/virtio/virtio-mmio.h | 73 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 74 insertions(+), 47 deletions(-)
create mode 100644 include/hw/virtio/virtio-mmio.h
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
index 3d5ca0f..94d934c 100644
--- a/hw/virtio/virtio-mmio.c
+++ b/hw/virtio/virtio-mmio.c
@@ -29,57 +29,11 @@
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "sysemu/kvm.h"
-#include "hw/virtio/virtio-bus.h"
+#include "hw/virtio/virtio-mmio.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "trace.h"
-/* QOM macros */
-/* virtio-mmio-bus */
-#define TYPE_VIRTIO_MMIO_BUS "virtio-mmio-bus"
-#define VIRTIO_MMIO_BUS(obj) \
- OBJECT_CHECK(VirtioBusState, (obj), TYPE_VIRTIO_MMIO_BUS)
-#define VIRTIO_MMIO_BUS_GET_CLASS(obj) \
- OBJECT_GET_CLASS(VirtioBusClass, (obj), TYPE_VIRTIO_MMIO_BUS)
-#define VIRTIO_MMIO_BUS_CLASS(klass) \
- OBJECT_CLASS_CHECK(VirtioBusClass, (klass), TYPE_VIRTIO_MMIO_BUS)
-
-/* virtio-mmio */
-#define TYPE_VIRTIO_MMIO "virtio-mmio"
-#define VIRTIO_MMIO(obj) \
- OBJECT_CHECK(VirtIOMMIOProxy, (obj), TYPE_VIRTIO_MMIO)
-
-#define VIRT_MAGIC 0x74726976 /* 'virt' */
-#define VIRT_VERSION 2
-#define VIRT_VERSION_LEGACY 1
-#define VIRT_VENDOR 0x554D4551 /* 'QEMU' */
-
-typedef struct VirtIOMMIOQueue {
- uint16_t num;
- bool enabled;
- uint32_t desc[2];
- uint32_t avail[2];
- uint32_t used[2];
-} VirtIOMMIOQueue;
-
-typedef struct {
- /* Generic */
- SysBusDevice parent_obj;
- MemoryRegion iomem;
- qemu_irq irq;
- bool legacy;
- /* Guest accessible state needing migration and reset */
- uint32_t host_features_sel;
- uint32_t guest_features_sel;
- uint32_t guest_page_shift;
- /* virtio-bus */
- VirtioBusState bus;
- bool format_transport_address;
- /* Fields only used for non-legacy (v2) devices */
- uint32_t guest_features[2];
- VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX];
-} VirtIOMMIOProxy;
-
static bool virtio_mmio_ioeventfd_enabled(DeviceState *d)
{
return kvm_eventfds_enabled();
diff --git a/include/hw/virtio/virtio-mmio.h b/include/hw/virtio/virtio-mmio.h
new file mode 100644
index 0000000..7dbfd03
--- /dev/null
+++ b/include/hw/virtio/virtio-mmio.h
@@ -0,0 +1,73 @@
+/*
+ * Virtio MMIO bindings
+ *
+ * Copyright (c) 2011 Linaro Limited
+ *
+ * Author:
+ * Peter Maydell <peter.maydell@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_VIRTIO_MMIO_H
+#define HW_VIRTIO_MMIO_H
+
+#include "hw/virtio/virtio-bus.h"
+
+/* QOM macros */
+/* virtio-mmio-bus */
+#define TYPE_VIRTIO_MMIO_BUS "virtio-mmio-bus"
+#define VIRTIO_MMIO_BUS(obj) \
+ OBJECT_CHECK(VirtioBusState, (obj), TYPE_VIRTIO_MMIO_BUS)
+#define VIRTIO_MMIO_BUS_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(VirtioBusClass, (obj), TYPE_VIRTIO_MMIO_BUS)
+#define VIRTIO_MMIO_BUS_CLASS(klass) \
+ OBJECT_CLASS_CHECK(VirtioBusClass, (klass), TYPE_VIRTIO_MMIO_BUS)
+
+/* virtio-mmio */
+#define TYPE_VIRTIO_MMIO "virtio-mmio"
+#define VIRTIO_MMIO(obj) \
+ OBJECT_CHECK(VirtIOMMIOProxy, (obj), TYPE_VIRTIO_MMIO)
+
+#define VIRT_MAGIC 0x74726976 /* 'virt' */
+#define VIRT_VERSION 2
+#define VIRT_VERSION_LEGACY 1
+#define VIRT_VENDOR 0x554D4551 /* 'QEMU' */
+
+typedef struct VirtIOMMIOQueue {
+ uint16_t num;
+ bool enabled;
+ uint32_t desc[2];
+ uint32_t avail[2];
+ uint32_t used[2];
+} VirtIOMMIOQueue;
+
+typedef struct {
+ /* Generic */
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq;
+ bool legacy;
+ /* Guest accessible state needing migration and reset */
+ uint32_t host_features_sel;
+ uint32_t guest_features_sel;
+ uint32_t guest_page_shift;
+ /* virtio-bus */
+ VirtioBusState bus;
+ bool format_transport_address;
+ /* Fields only used for non-legacy (v2) devices */
+ uint32_t guest_features[2];
+ VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX];
+} VirtIOMMIOProxy;
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 08/39] hw/i386/pc: rename functions shared with non-PC machines
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (6 preceding siblings ...)
2019-10-24 14:03 ` [PULL 07/39] hw/virtio: Factorize virtio-mmio headers Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 09/39] hw/i386/pc: fix code style issues on functions that will be moved out Paolo Bonzini
` (32 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
The following functions are named *pc* but are not PC-machine specific
but generic to the X86 architecture, rename them:
load_linux -> x86_load_linux
pc_new_cpu -> x86_new_cpu
pc_cpus_init -> x86_cpus_init
pc_cpu_index_to_props -> x86_cpu_index_to_props
pc_get_default_cpu_node_id -> x86_get_default_cpu_node_id
pc_possible_cpu_arch_ids -> x86_possible_cpu_arch_ids
old_pc_system_rom_init -> x86_system_rom_init
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 28 ++++++++++++++--------------
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
hw/i386/pc_sysfw.c | 6 +++---
include/hw/i386/pc.h | 2 +-
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 4b19042..1c27223 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1019,8 +1019,8 @@ static bool load_elfboot(const char *kernel_filename,
return true;
}
-static void load_linux(PCMachineState *pcms,
- FWCfgState *fw_cfg)
+static void x86_load_linux(PCMachineState *pcms,
+ FWCfgState *fw_cfg)
{
uint16_t protocol;
int setup_size, kernel_size, cmdline_size;
@@ -1374,7 +1374,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
}
}
-static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
+static void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
{
Object *cpu = NULL;
Error *local_err = NULL;
@@ -1490,14 +1490,14 @@ void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
return;
}
- pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
+ x86_cpu_new(PC_MACHINE(ms), apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
}
-void pc_cpus_init(PCMachineState *pcms)
+void x86_cpus_init(PCMachineState *pcms)
{
int i;
const CPUArchIdList *possible_cpus;
@@ -1518,7 +1518,7 @@ void pc_cpus_init(PCMachineState *pcms)
ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < ms->smp.cpus; i++) {
- pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
+ x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
@@ -1621,7 +1621,7 @@ void xen_load_linux(PCMachineState *pcms)
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
rom_set_fw(fw_cfg);
- load_linux(pcms, fw_cfg);
+ x86_load_linux(pcms, fw_cfg);
for (i = 0; i < nb_option_roms; i++) {
assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
!strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
@@ -1756,7 +1756,7 @@ void pc_memory_init(PCMachineState *pcms,
}
if (linux_boot) {
- load_linux(pcms, fw_cfg);
+ x86_load_linux(pcms, fw_cfg);
}
for (i = 0; i < nb_option_roms; i++) {
@@ -2681,7 +2681,7 @@ static void pc_machine_wakeup(MachineState *machine)
}
static CpuInstanceProperties
-pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
@@ -2690,7 +2690,7 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
return possible_cpus->cpus[cpu_index].props;
}
-static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
+static int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
{
X86CPUTopoInfo topo;
PCMachineState *pcms = PC_MACHINE(ms);
@@ -2702,7 +2702,7 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
return topo.pkg_id % ms->numa_state->num_nodes;
}
-static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
+static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
{
PCMachineState *pcms = PC_MACHINE(ms);
int i;
@@ -2804,9 +2804,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = pc_get_hotplug_handler;
mc->hotplug_allowed = pc_hotplug_allowed;
- mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
- mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
- mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
+ mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
+ mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
+ mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
mc->auto_enable_numa_with_memhp = true;
mc->has_hotpluggable_cpus = true;
mc->default_boot_order = "cad";
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72..de09e07 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -152,7 +152,7 @@ static void pc_init1(MachineState *machine,
}
}
- pc_cpus_init(pcms);
+ x86_cpus_init(pcms);
if (kvm_enabled() && pcmc->kvmclock_enabled) {
kvmclock_create();
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8fad20f..894989b 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -179,7 +179,7 @@ static void pc_q35_init(MachineState *machine)
xen_hvm_init(pcms, &ram_memory);
}
- pc_cpus_init(pcms);
+ x86_cpus_init(pcms);
kvmclock_create();
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
index a9983f0..28cb1f6 100644
--- a/hw/i386/pc_sysfw.c
+++ b/hw/i386/pc_sysfw.c
@@ -211,7 +211,7 @@ static void pc_system_flash_map(PCMachineState *pcms,
}
}
-static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
+static void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
{
char *filename;
MemoryRegion *bios, *isa_bios;
@@ -272,7 +272,7 @@ void pc_system_firmware_init(PCMachineState *pcms,
BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)];
if (!pcmc->pci_enabled) {
- old_pc_system_rom_init(rom_memory, true);
+ x86_bios_rom_init(rom_memory, true);
return;
}
@@ -293,7 +293,7 @@ void pc_system_firmware_init(PCMachineState *pcms,
if (!pflash_blk[0]) {
/* Machine property pflash0 not set, use ROM mode */
- old_pc_system_rom_init(rom_memory, false);
+ x86_bios_rom_init(rom_memory, false);
} else {
if (kvm_enabled() && !kvm_readonly_mem_enabled()) {
/*
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 37bfd95..7082b06 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -198,7 +198,7 @@ bool pc_machine_is_smm_enabled(PCMachineState *pcms);
void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
-void pc_cpus_init(PCMachineState *pcms);
+void x86_cpus_init(PCMachineState *pcms);
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
void pc_smp_parse(MachineState *ms, QemuOpts *opts);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 09/39] hw/i386/pc: fix code style issues on functions that will be moved out
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (7 preceding siblings ...)
2019-10-24 14:03 ` [PULL 08/39] hw/i386/pc: rename functions shared with non-PC machines Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 10/39] hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux() Paolo Bonzini
` (31 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Fix code style issues detected by checkpatch.pl on functions that will
be moved out to x86.c.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
hw/i386/pc.c | 53 +++++++++++++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 1c27223..75a97c2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -866,7 +866,8 @@ static void handle_a20_line_change(void *opaque, int irq, int level)
x86_cpu_set_a20(cpu, level);
}
-/* Calculates initial APIC ID for a specific CPU index
+/*
+ * Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
@@ -1039,7 +1040,7 @@ static void x86_load_linux(PCMachineState *pcms,
const char *kernel_cmdline = machine->kernel_cmdline;
/* Align to 16 bytes as a paranoia measure */
- cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
+ cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
/* load the kernel header */
f = fopen(kernel_filename, "rb");
@@ -1055,8 +1056,8 @@ static void x86_load_linux(PCMachineState *pcms,
#if 0
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
#endif
- if (ldl_p(header+0x202) == 0x53726448) {
- protocol = lduw_p(header+0x206);
+ if (ldl_p(header + 0x202) == 0x53726448) {
+ protocol = lduw_p(header + 0x206);
} else {
/*
* This could be a multiboot kernel. If it is, let's stop treating it
@@ -1158,7 +1159,7 @@ static void x86_load_linux(PCMachineState *pcms,
/* highest address for loading the initrd */
if (protocol >= 0x20c &&
- lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
+ lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
/*
* Linux has supported initrd up to 4 GB for a very long time (2007,
* long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
@@ -1177,7 +1178,7 @@ static void x86_load_linux(PCMachineState *pcms,
*/
initrd_max = UINT32_MAX;
} else if (protocol >= 0x203) {
- initrd_max = ldl_p(header+0x22c);
+ initrd_max = ldl_p(header + 0x22c);
} else {
initrd_max = 0x37ffffff;
}
@@ -1187,14 +1188,14 @@ static void x86_load_linux(PCMachineState *pcms,
}
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
if (protocol >= 0x202) {
- stl_p(header+0x228, cmdline_addr);
+ stl_p(header + 0x228, cmdline_addr);
} else {
- stw_p(header+0x20, 0xA33F);
- stw_p(header+0x22, cmdline_addr-real_addr);
+ stw_p(header + 0x20, 0xA33F);
+ stw_p(header + 0x22, cmdline_addr - real_addr);
}
/* handle vga= parameter */
@@ -1212,20 +1213,22 @@ static void x86_load_linux(PCMachineState *pcms,
} else {
video_mode = strtol(vmode, NULL, 0);
}
- stw_p(header+0x1fa, video_mode);
+ stw_p(header + 0x1fa, video_mode);
}
/* loader type */
- /* High nybble = B reserved for QEMU; low nybble is revision number.
- If this code is substantially changed, you may want to consider
- incrementing the revision. */
+ /*
+ * High nybble = B reserved for QEMU; low nybble is revision number.
+ * If this code is substantially changed, you may want to consider
+ * incrementing the revision.
+ */
if (protocol >= 0x200) {
header[0x210] = 0xB0;
}
/* heap */
if (protocol >= 0x201) {
- header[0x211] |= 0x80; /* CAN_USE_HEAP */
- stw_p(header+0x224, cmdline_addr-real_addr-0x200);
+ header[0x211] |= 0x80; /* CAN_USE_HEAP */
+ stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
}
/* load initrd */
@@ -1257,14 +1260,14 @@ static void x86_load_linux(PCMachineState *pcms,
exit(1);
}
- initrd_addr = (initrd_max-initrd_size) & ~4095;
+ initrd_addr = (initrd_max - initrd_size) & ~4095;
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
- stl_p(header+0x218, initrd_addr);
- stl_p(header+0x21c, initrd_size);
+ stl_p(header + 0x218, initrd_addr);
+ stl_p(header + 0x21c, initrd_size);
}
/* load kernel and setup */
@@ -1272,7 +1275,7 @@ static void x86_load_linux(PCMachineState *pcms,
if (setup_size == 0) {
setup_size = 4;
}
- setup_size = (setup_size+1)*512;
+ setup_size = (setup_size + 1) * 512;
if (setup_size > kernel_size) {
fprintf(stderr, "qemu: invalid kernel header\n");
exit(1);
@@ -1310,7 +1313,7 @@ static void x86_load_linux(PCMachineState *pcms,
kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
kernel = g_realloc(kernel, kernel_size);
- stq_p(header+0x250, prot_addr + setup_data_offset);
+ stq_p(header + 0x250, prot_addr + setup_data_offset);
setup_data = (struct setup_data *)(kernel + setup_data_offset);
setup_data->next = 0;
@@ -1507,7 +1510,8 @@ void x86_cpus_init(PCMachineState *pcms)
x86_cpu_set_default_version(pcmc->default_cpu_version);
- /* Calculates the limit to CPU APIC ID values
+ /*
+ * Calculates the limit to CPU APIC ID values
*
* Limit for the APIC ID value, so that all
* CPU APIC IDs are < pcms->apic_id_limit.
@@ -2712,7 +2716,7 @@ static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
/*
* make sure that max_cpus hasn't changed since the first use, i.e.
* -smp hasn't been parsed after it
- */
+ */
assert(ms->possible_cpus->len == max_cpus);
return ms->possible_cpus;
}
@@ -2725,7 +2729,8 @@ static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
- ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
+ ms->possible_cpus->cpus[i].arch_id =
+ x86_cpu_apic_id_from_index(pcms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
pcms->smp_dies, ms->smp.cores,
ms->smp.threads, &topo);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 10/39] hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux()
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (8 preceding siblings ...)
2019-10-24 14:03 ` [PULL 09/39] hw/i386/pc: fix code style issues on functions that will be moved out Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 11/39] hw/i386/pc: avoid an assignment in if condition " Paolo Bonzini
` (30 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Follow checkpatch.pl recommendation and replace the use of strtol with
qemu_strtoui in x86_load_linux().
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
hw/i386/pc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 75a97c2..b5b660f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -68,6 +68,7 @@
#include "qemu/config-file.h"
#include "qemu/error-report.h"
#include "qemu/option.h"
+#include "qemu/cutils.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/boards.h"
@@ -1202,6 +1203,7 @@ static void x86_load_linux(PCMachineState *pcms,
vmode = strstr(kernel_cmdline, "vga=");
if (vmode) {
unsigned int video_mode;
+ int ret;
/* skip "vga=" */
vmode += 4;
if (!strncmp(vmode, "normal", 6)) {
@@ -1211,7 +1213,12 @@ static void x86_load_linux(PCMachineState *pcms,
} else if (!strncmp(vmode, "ask", 3)) {
video_mode = 0xfffd;
} else {
- video_mode = strtol(vmode, NULL, 0);
+ ret = qemu_strtoui(vmode, NULL, 0, &video_mode);
+ if (ret != 0) {
+ fprintf(stderr, "qemu: can't parse 'vga' parameter: %s\n",
+ strerror(-ret));
+ exit(1);
+ }
}
stw_p(header + 0x1fa, video_mode);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 11/39] hw/i386/pc: avoid an assignment in if condition in x86_load_linux()
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (9 preceding siblings ...)
2019-10-24 14:03 ` [PULL 10/39] hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux() Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 12/39] hw/i386/pc: remove commented out code from x86_load_linux() Paolo Bonzini
` (29 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Follow checkpatch.pl recommendation and avoid an assignment in if
condition in x86_load_linux().
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/pc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b5b660f..77198d5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1045,7 +1045,14 @@ static void x86_load_linux(PCMachineState *pcms,
/* load the kernel header */
f = fopen(kernel_filename, "rb");
- if (!f || !(kernel_size = get_file_size(f)) ||
+ if (!f) {
+ fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
+ kernel_filename, strerror(errno));
+ exit(1);
+ }
+
+ kernel_size = get_file_size(f);
+ if (!kernel_size ||
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
MIN(ARRAY_SIZE(header), kernel_size)) {
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 12/39] hw/i386/pc: remove commented out code from x86_load_linux()
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (10 preceding siblings ...)
2019-10-24 14:03 ` [PULL 11/39] hw/i386/pc: avoid an assignment in if condition " Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 13/39] hw/i386/pc: move shared x86 functions to x86.c and export them Paolo Bonzini
` (28 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Follow checkpatch.pl recommendation and remove commented out code from
x86_load_linux().
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/pc.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 77198d5..903bc05 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1061,9 +1061,6 @@ static void x86_load_linux(PCMachineState *pcms,
}
/* kernel protocol version */
-#if 0
- fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
-#endif
if (ldl_p(header + 0x202) == 0x53726448) {
protocol = lduw_p(header + 0x206);
} else {
@@ -1155,16 +1152,6 @@ static void x86_load_linux(PCMachineState *pcms,
prot_addr = 0x100000;
}
-#if 0
- fprintf(stderr,
- "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
- "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
- "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
- real_addr,
- cmdline_addr,
- prot_addr);
-#endif
-
/* highest address for loading the initrd */
if (protocol >= 0x20c &&
lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 13/39] hw/i386/pc: move shared x86 functions to x86.c and export them
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (11 preceding siblings ...)
2019-10-24 14:03 ` [PULL 12/39] hw/i386/pc: remove commented out code from x86_load_linux() Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 14/39] hw/i386: split PCMachineState deriving X86MachineState from it Paolo Bonzini
` (27 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Move x86 functions that will be shared between PC and non-PC machine
types to x86.c, along with their helpers.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/Makefile.objs | 1 +
hw/i386/pc.c | 587 +-----------------------------------------
hw/i386/pc_piix.c | 1 +
hw/i386/pc_q35.c | 1 +
hw/i386/pc_sysfw.c | 56 +---
hw/i386/x86.c | 690 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/i386/pc.h | 1 -
include/hw/i386/x86.h | 35 +++
8 files changed, 730 insertions(+), 642 deletions(-)
create mode 100644 hw/i386/x86.c
create mode 100644 include/hw/i386/x86.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index d3374e0..7ed80a4 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -1,5 +1,6 @@
obj-$(CONFIG_KVM) += kvm/
obj-y += e820_memory_layout.o multiboot.o
+obj-y += x86.o
obj-y += pc.o
obj-$(CONFIG_I440FX) += pc_piix.o
obj-$(CONFIG_Q35) += pc_q35.o
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 903bc05..4a1bc95 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
@@ -103,9 +104,6 @@
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
-/* Physical Address of PVH entry point read from kernel ELF NOTE */
-static size_t pvh_start_addr;
-
GlobalProperty pc_compat_4_1[] = {};
const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
@@ -867,481 +865,6 @@ static void handle_a20_line_change(void *opaque, int irq, int level)
x86_cpu_set_a20(cpu, level);
}
-/*
- * Calculates initial APIC ID for a specific CPU index
- *
- * Currently we need to be able to calculate the APIC ID from the CPU index
- * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
- * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
- * all CPUs up to max_cpus.
- */
-static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
- unsigned int cpu_index)
-{
- MachineState *ms = MACHINE(pcms);
- PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
- uint32_t correct_id;
- static bool warned;
-
- correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
- ms->smp.threads, cpu_index);
- if (pcmc->compat_apic_id_mode) {
- if (cpu_index != correct_id && !warned && !qtest_enabled()) {
- error_report("APIC IDs set in compatibility mode, "
- "CPU topology won't match the configuration");
- warned = true;
- }
- return cpu_index;
- } else {
- return correct_id;
- }
-}
-
-static long get_file_size(FILE *f)
-{
- long where, size;
-
- /* XXX: on Unix systems, using fstat() probably makes more sense */
-
- where = ftell(f);
- fseek(f, 0, SEEK_END);
- size = ftell(f);
- fseek(f, where, SEEK_SET);
-
- return size;
-}
-
-struct setup_data {
- uint64_t next;
- uint32_t type;
- uint32_t len;
- uint8_t data[0];
-} __attribute__((packed));
-
-
-/*
- * The entry point into the kernel for PVH boot is different from
- * the native entry point. The PVH entry is defined by the x86/HVM
- * direct boot ABI and is available in an ELFNOTE in the kernel binary.
- *
- * This function is passed to load_elf() when it is called from
- * load_elfboot() which then additionally checks for an ELF Note of
- * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
- * parse the PVH entry address from the ELF Note.
- *
- * Due to trickery in elf_opts.h, load_elf() is actually available as
- * load_elf32() or load_elf64() and this routine needs to be able
- * to deal with being called as 32 or 64 bit.
- *
- * The address of the PVH entry point is saved to the 'pvh_start_addr'
- * global variable. (although the entry point is 32-bit, the kernel
- * binary can be either 32-bit or 64-bit).
- */
-static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
-{
- size_t *elf_note_data_addr;
-
- /* Check if ELF Note header passed in is valid */
- if (arg1 == NULL) {
- return 0;
- }
-
- if (is64) {
- struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
- uint64_t nhdr_size64 = sizeof(struct elf64_note);
- uint64_t phdr_align = *(uint64_t *)arg2;
- uint64_t nhdr_namesz = nhdr64->n_namesz;
-
- elf_note_data_addr =
- ((void *)nhdr64) + nhdr_size64 +
- QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
- } else {
- struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
- uint32_t nhdr_size32 = sizeof(struct elf32_note);
- uint32_t phdr_align = *(uint32_t *)arg2;
- uint32_t nhdr_namesz = nhdr32->n_namesz;
-
- elf_note_data_addr =
- ((void *)nhdr32) + nhdr_size32 +
- QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
- }
-
- pvh_start_addr = *elf_note_data_addr;
-
- return pvh_start_addr;
-}
-
-static bool load_elfboot(const char *kernel_filename,
- int kernel_file_size,
- uint8_t *header,
- size_t pvh_xen_start_addr,
- FWCfgState *fw_cfg)
-{
- uint32_t flags = 0;
- uint32_t mh_load_addr = 0;
- uint32_t elf_kernel_size = 0;
- uint64_t elf_entry;
- uint64_t elf_low, elf_high;
- int kernel_size;
-
- if (ldl_p(header) != 0x464c457f) {
- return false; /* no elfboot */
- }
-
- bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
- flags = elf_is64 ?
- ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
-
- if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
- error_report("elfboot unsupported flags = %x", flags);
- exit(1);
- }
-
- uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
- kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
- NULL, &elf_note_type, &elf_entry,
- &elf_low, &elf_high, 0, I386_ELF_MACHINE,
- 0, 0);
-
- if (kernel_size < 0) {
- error_report("Error while loading elf kernel");
- exit(1);
- }
- mh_load_addr = elf_low;
- elf_kernel_size = elf_high - elf_low;
-
- if (pvh_start_addr == 0) {
- error_report("Error loading uncompressed kernel without PVH ELF Note");
- exit(1);
- }
- fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
-
- return true;
-}
-
-static void x86_load_linux(PCMachineState *pcms,
- FWCfgState *fw_cfg)
-{
- uint16_t protocol;
- int setup_size, kernel_size, cmdline_size;
- int dtb_size, setup_data_offset;
- uint32_t initrd_max;
- uint8_t header[8192], *setup, *kernel;
- hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
- FILE *f;
- char *vmode;
- MachineState *machine = MACHINE(pcms);
- PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
- struct setup_data *setup_data;
- const char *kernel_filename = machine->kernel_filename;
- const char *initrd_filename = machine->initrd_filename;
- const char *dtb_filename = machine->dtb;
- const char *kernel_cmdline = machine->kernel_cmdline;
-
- /* Align to 16 bytes as a paranoia measure */
- cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
-
- /* load the kernel header */
- f = fopen(kernel_filename, "rb");
- if (!f) {
- fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
- kernel_filename, strerror(errno));
- exit(1);
- }
-
- kernel_size = get_file_size(f);
- if (!kernel_size ||
- fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
- MIN(ARRAY_SIZE(header), kernel_size)) {
- fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
- kernel_filename, strerror(errno));
- exit(1);
- }
-
- /* kernel protocol version */
- if (ldl_p(header + 0x202) == 0x53726448) {
- protocol = lduw_p(header + 0x206);
- } else {
- /*
- * This could be a multiboot kernel. If it is, let's stop treating it
- * like a Linux kernel.
- * Note: some multiboot images could be in the ELF format (the same of
- * PVH), so we try multiboot first since we check the multiboot magic
- * header before to load it.
- */
- if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
- kernel_cmdline, kernel_size, header)) {
- return;
- }
- /*
- * Check if the file is an uncompressed kernel file (ELF) and load it,
- * saving the PVH entry point used by the x86/HVM direct boot ABI.
- * If load_elfboot() is successful, populate the fw_cfg info.
- */
- if (pcmc->pvh_enabled &&
- load_elfboot(kernel_filename, kernel_size,
- header, pvh_start_addr, fw_cfg)) {
- fclose(f);
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
- strlen(kernel_cmdline) + 1);
- fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
- header, sizeof(header));
-
- /* load initrd */
- if (initrd_filename) {
- GMappedFile *mapped_file;
- gsize initrd_size;
- gchar *initrd_data;
- GError *gerr = NULL;
-
- mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
- if (!mapped_file) {
- fprintf(stderr, "qemu: error reading initrd %s: %s\n",
- initrd_filename, gerr->message);
- exit(1);
- }
- pcms->initrd_mapped_file = mapped_file;
-
- initrd_data = g_mapped_file_get_contents(mapped_file);
- initrd_size = g_mapped_file_get_length(mapped_file);
- initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
- if (initrd_size >= initrd_max) {
- fprintf(stderr, "qemu: initrd is too large, cannot support."
- "(max: %"PRIu32", need %"PRId64")\n",
- initrd_max, (uint64_t)initrd_size);
- exit(1);
- }
-
- initrd_addr = (initrd_max - initrd_size) & ~4095;
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
- initrd_size);
- }
-
- option_rom[nb_option_roms].bootindex = 0;
- option_rom[nb_option_roms].name = "pvh.bin";
- nb_option_roms++;
-
- return;
- }
- protocol = 0;
- }
-
- if (protocol < 0x200 || !(header[0x211] & 0x01)) {
- /* Low kernel */
- real_addr = 0x90000;
- cmdline_addr = 0x9a000 - cmdline_size;
- prot_addr = 0x10000;
- } else if (protocol < 0x202) {
- /* High but ancient kernel */
- real_addr = 0x90000;
- cmdline_addr = 0x9a000 - cmdline_size;
- prot_addr = 0x100000;
- } else {
- /* High and recent kernel */
- real_addr = 0x10000;
- cmdline_addr = 0x20000;
- prot_addr = 0x100000;
- }
-
- /* highest address for loading the initrd */
- if (protocol >= 0x20c &&
- lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
- /*
- * Linux has supported initrd up to 4 GB for a very long time (2007,
- * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
- * though it only sets initrd_max to 2 GB to "work around bootloader
- * bugs". Luckily, QEMU firmware(which does something like bootloader)
- * has supported this.
- *
- * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
- * be loaded into any address.
- *
- * In addition, initrd_max is uint32_t simply because QEMU doesn't
- * support the 64-bit boot protocol (specifically the ext_ramdisk_image
- * field).
- *
- * Therefore here just limit initrd_max to UINT32_MAX simply as well.
- */
- initrd_max = UINT32_MAX;
- } else if (protocol >= 0x203) {
- initrd_max = ldl_p(header + 0x22c);
- } else {
- initrd_max = 0x37ffffff;
- }
-
- if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
- initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
- }
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
- fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
-
- if (protocol >= 0x202) {
- stl_p(header + 0x228, cmdline_addr);
- } else {
- stw_p(header + 0x20, 0xA33F);
- stw_p(header + 0x22, cmdline_addr - real_addr);
- }
-
- /* handle vga= parameter */
- vmode = strstr(kernel_cmdline, "vga=");
- if (vmode) {
- unsigned int video_mode;
- int ret;
- /* skip "vga=" */
- vmode += 4;
- if (!strncmp(vmode, "normal", 6)) {
- video_mode = 0xffff;
- } else if (!strncmp(vmode, "ext", 3)) {
- video_mode = 0xfffe;
- } else if (!strncmp(vmode, "ask", 3)) {
- video_mode = 0xfffd;
- } else {
- ret = qemu_strtoui(vmode, NULL, 0, &video_mode);
- if (ret != 0) {
- fprintf(stderr, "qemu: can't parse 'vga' parameter: %s\n",
- strerror(-ret));
- exit(1);
- }
- }
- stw_p(header + 0x1fa, video_mode);
- }
-
- /* loader type */
- /*
- * High nybble = B reserved for QEMU; low nybble is revision number.
- * If this code is substantially changed, you may want to consider
- * incrementing the revision.
- */
- if (protocol >= 0x200) {
- header[0x210] = 0xB0;
- }
- /* heap */
- if (protocol >= 0x201) {
- header[0x211] |= 0x80; /* CAN_USE_HEAP */
- stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
- }
-
- /* load initrd */
- if (initrd_filename) {
- GMappedFile *mapped_file;
- gsize initrd_size;
- gchar *initrd_data;
- GError *gerr = NULL;
-
- if (protocol < 0x200) {
- fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
- exit(1);
- }
-
- mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
- if (!mapped_file) {
- fprintf(stderr, "qemu: error reading initrd %s: %s\n",
- initrd_filename, gerr->message);
- exit(1);
- }
- pcms->initrd_mapped_file = mapped_file;
-
- initrd_data = g_mapped_file_get_contents(mapped_file);
- initrd_size = g_mapped_file_get_length(mapped_file);
- if (initrd_size >= initrd_max) {
- fprintf(stderr, "qemu: initrd is too large, cannot support."
- "(max: %"PRIu32", need %"PRId64")\n",
- initrd_max, (uint64_t)initrd_size);
- exit(1);
- }
-
- initrd_addr = (initrd_max - initrd_size) & ~4095;
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
-
- stl_p(header + 0x218, initrd_addr);
- stl_p(header + 0x21c, initrd_size);
- }
-
- /* load kernel and setup */
- setup_size = header[0x1f1];
- if (setup_size == 0) {
- setup_size = 4;
- }
- setup_size = (setup_size + 1) * 512;
- if (setup_size > kernel_size) {
- fprintf(stderr, "qemu: invalid kernel header\n");
- exit(1);
- }
- kernel_size -= setup_size;
-
- setup = g_malloc(setup_size);
- kernel = g_malloc(kernel_size);
- fseek(f, 0, SEEK_SET);
- if (fread(setup, 1, setup_size, f) != setup_size) {
- fprintf(stderr, "fread() failed\n");
- exit(1);
- }
- if (fread(kernel, 1, kernel_size, f) != kernel_size) {
- fprintf(stderr, "fread() failed\n");
- exit(1);
- }
- fclose(f);
-
- /* append dtb to kernel */
- if (dtb_filename) {
- if (protocol < 0x209) {
- fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
- exit(1);
- }
-
- dtb_size = get_image_size(dtb_filename);
- if (dtb_size <= 0) {
- fprintf(stderr, "qemu: error reading dtb %s: %s\n",
- dtb_filename, strerror(errno));
- exit(1);
- }
-
- setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
- kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
- kernel = g_realloc(kernel, kernel_size);
-
- stq_p(header + 0x250, prot_addr + setup_data_offset);
-
- setup_data = (struct setup_data *)(kernel + setup_data_offset);
- setup_data->next = 0;
- setup_data->type = cpu_to_le32(SETUP_DTB);
- setup_data->len = cpu_to_le32(dtb_size);
-
- load_image_size(dtb_filename, setup_data->data, dtb_size);
- }
-
- memcpy(setup, header, MIN(sizeof(header), setup_size));
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
-
- fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
- fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
-
- option_rom[nb_option_roms].bootindex = 0;
- option_rom[nb_option_roms].name = "linuxboot.bin";
- if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
- option_rom[nb_option_roms].name = "linuxboot_dma.bin";
- }
- nb_option_roms++;
-}
-
#define NE2000_NB_MAX 6
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
@@ -1378,24 +901,6 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
}
}
-static void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
-{
- Object *cpu = NULL;
- Error *local_err = NULL;
- CPUX86State *env = NULL;
-
- cpu = object_new(MACHINE(pcms)->cpu_type);
-
- env = &X86_CPU(cpu)->env;
- env->nr_dies = pcms->smp_dies;
-
- object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
- object_property_set_bool(cpu, true, "realized", &local_err);
-
- object_unref(cpu);
- error_propagate(errp, local_err);
-}
-
/*
* This function is very similar to smp_parse()
* in hw/core/machine.c but includes CPU die support.
@@ -1501,32 +1006,6 @@ void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
}
}
-void x86_cpus_init(PCMachineState *pcms)
-{
- int i;
- const CPUArchIdList *possible_cpus;
- MachineState *ms = MACHINE(pcms);
- MachineClass *mc = MACHINE_GET_CLASS(pcms);
- PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
-
- x86_cpu_set_default_version(pcmc->default_cpu_version);
-
- /*
- * Calculates the limit to CPU APIC ID values
- *
- * Limit for the APIC ID value, so that all
- * CPU APIC IDs are < pcms->apic_id_limit.
- *
- * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
- */
- pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
- ms->smp.max_cpus - 1) + 1;
- possible_cpus = mc->possible_cpu_arch_ids(ms);
- for (i = 0; i < ms->smp.cpus; i++) {
- x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
- }
-}
-
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
{
if (cpus_count > 0xff) {
@@ -2685,70 +2164,6 @@ static void pc_machine_wakeup(MachineState *machine)
cpu_synchronize_all_post_reset();
}
-static CpuInstanceProperties
-x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
-{
- MachineClass *mc = MACHINE_GET_CLASS(ms);
- const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
-
- assert(cpu_index < possible_cpus->len);
- return possible_cpus->cpus[cpu_index].props;
-}
-
-static int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
-{
- X86CPUTopoInfo topo;
- PCMachineState *pcms = PC_MACHINE(ms);
-
- assert(idx < ms->possible_cpus->len);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- pcms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo);
- return topo.pkg_id % ms->numa_state->num_nodes;
-}
-
-static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
-{
- PCMachineState *pcms = PC_MACHINE(ms);
- int i;
- unsigned int max_cpus = ms->smp.max_cpus;
-
- if (ms->possible_cpus) {
- /*
- * make sure that max_cpus hasn't changed since the first use, i.e.
- * -smp hasn't been parsed after it
- */
- assert(ms->possible_cpus->len == max_cpus);
- return ms->possible_cpus;
- }
-
- ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
- sizeof(CPUArchId) * max_cpus);
- ms->possible_cpus->len = max_cpus;
- for (i = 0; i < ms->possible_cpus->len; i++) {
- X86CPUTopoInfo topo;
-
- ms->possible_cpus->cpus[i].type = ms->cpu_type;
- ms->possible_cpus->cpus[i].vcpus_count = 1;
- ms->possible_cpus->cpus[i].arch_id =
- x86_cpu_apic_id_from_index(pcms, i);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- pcms->smp_dies, ms->smp.cores,
- ms->smp.threads, &topo);
- ms->possible_cpus->cpus[i].props.has_socket_id = true;
- ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
- if (pcms->smp_dies > 1) {
- ms->possible_cpus->cpus[i].props.has_die_id = true;
- ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
- }
- ms->possible_cpus->cpus[i].props.has_core_id = true;
- ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
- ms->possible_cpus->cpus[i].props.has_thread_id = true;
- ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
- }
- return ms->possible_cpus;
-}
-
static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
{
/* cpu index isn't used */
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index de09e07..1396451 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -27,6 +27,7 @@
#include "qemu/units.h"
#include "hw/loader.h"
+#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
#include "hw/display/ramfb.h"
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 894989b..8920bd8 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -41,6 +41,7 @@
#include "hw/pci-host/q35.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
+#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/i386/ich9.h"
#include "hw/i386/amd_iommu.h"
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
index 28cb1f6..f5f3f46 100644
--- a/hw/i386/pc_sysfw.c
+++ b/hw/i386/pc_sysfw.c
@@ -31,6 +31,7 @@
#include "qemu/option.h"
#include "qemu/units.h"
#include "hw/sysbus.h"
+#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/loader.h"
#include "hw/qdev-properties.h"
@@ -38,8 +39,6 @@
#include "hw/block/flash.h"
#include "sysemu/kvm.h"
-#define BIOS_FILENAME "bios.bin"
-
/*
* We don't have a theoretically justifiable exact lower bound on the base
* address of any flash mapping. In practice, the IO-APIC MMIO range is
@@ -211,59 +210,6 @@ static void pc_system_flash_map(PCMachineState *pcms,
}
}
-static void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
-{
- char *filename;
- MemoryRegion *bios, *isa_bios;
- int bios_size, isa_bios_size;
- int ret;
-
- /* BIOS load */
- if (bios_name == NULL) {
- bios_name = BIOS_FILENAME;
- }
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- if (filename) {
- bios_size = get_image_size(filename);
- } else {
- bios_size = -1;
- }
- if (bios_size <= 0 ||
- (bios_size % 65536) != 0) {
- goto bios_error;
- }
- bios = g_malloc(sizeof(*bios));
- memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal);
- if (!isapc_ram_fw) {
- memory_region_set_readonly(bios, true);
- }
- ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
- if (ret != 0) {
- bios_error:
- fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
- exit(1);
- }
- g_free(filename);
-
- /* map the last 128KB of the BIOS in ISA space */
- isa_bios_size = MIN(bios_size, 128 * KiB);
- isa_bios = g_malloc(sizeof(*isa_bios));
- memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
- bios_size - isa_bios_size, isa_bios_size);
- memory_region_add_subregion_overlap(rom_memory,
- 0x100000 - isa_bios_size,
- isa_bios,
- 1);
- if (!isapc_ram_fw) {
- memory_region_set_readonly(isa_bios, true);
- }
-
- /* map all the bios at the top of memory */
- memory_region_add_subregion(rom_memory,
- (uint32_t)(-bios_size),
- bios);
-}
-
void pc_system_firmware_init(PCMachineState *pcms,
MemoryRegion *rom_memory)
{
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
new file mode 100644
index 0000000..71fb093
--- /dev/null
+++ b/hw/i386/x86.c
@@ -0,0 +1,690 @@
+/*
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ * Copyright (c) 2019 Red Hat, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/option.h"
+#include "qemu/cutils.h"
+#include "qemu/units.h"
+#include "qemu-common.h"
+#include "qapi/error.h"
+#include "qapi/qmp/qerror.h"
+#include "qapi/qapi-visit-common.h"
+#include "qapi/visitor.h"
+#include "sysemu/qtest.h"
+#include "sysemu/numa.h"
+#include "sysemu/replay.h"
+#include "sysemu/sysemu.h"
+
+#include "hw/i386/x86.h"
+#include "hw/i386/pc.h"
+#include "target/i386/cpu.h"
+#include "hw/i386/topology.h"
+#include "hw/i386/fw_cfg.h"
+
+#include "hw/acpi/cpu_hotplug.h"
+#include "hw/nmi.h"
+#include "hw/loader.h"
+#include "multiboot.h"
+#include "elf.h"
+#include "standard-headers/asm-x86/bootparam.h"
+
+#define BIOS_FILENAME "bios.bin"
+
+/* Physical Address of PVH entry point read from kernel ELF NOTE */
+static size_t pvh_start_addr;
+
+/*
+ * Calculates initial APIC ID for a specific CPU index
+ *
+ * Currently we need to be able to calculate the APIC ID from the CPU index
+ * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
+ * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
+ * all CPUs up to max_cpus.
+ */
+uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
+ unsigned int cpu_index)
+{
+ MachineState *ms = MACHINE(pcms);
+ PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ uint32_t correct_id;
+ static bool warned;
+
+ correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
+ ms->smp.threads, cpu_index);
+ if (pcmc->compat_apic_id_mode) {
+ if (cpu_index != correct_id && !warned && !qtest_enabled()) {
+ error_report("APIC IDs set in compatibility mode, "
+ "CPU topology won't match the configuration");
+ warned = true;
+ }
+ return cpu_index;
+ } else {
+ return correct_id;
+ }
+}
+
+void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
+{
+ Object *cpu = NULL;
+ Error *local_err = NULL;
+ CPUX86State *env = NULL;
+
+ cpu = object_new(MACHINE(pcms)->cpu_type);
+
+ env = &X86_CPU(cpu)->env;
+ env->nr_dies = pcms->smp_dies;
+
+ object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
+ object_property_set_bool(cpu, true, "realized", &local_err);
+
+ object_unref(cpu);
+ error_propagate(errp, local_err);
+}
+
+void x86_cpus_init(PCMachineState *pcms)
+{
+ int i;
+ const CPUArchIdList *possible_cpus;
+ MachineState *ms = MACHINE(pcms);
+ MachineClass *mc = MACHINE_GET_CLASS(pcms);
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
+
+ x86_cpu_set_default_version(pcmc->default_cpu_version);
+
+ /*
+ * Calculates the limit to CPU APIC ID values
+ *
+ * Limit for the APIC ID value, so that all
+ * CPU APIC IDs are < pcms->apic_id_limit.
+ *
+ * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
+ */
+ pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
+ ms->smp.max_cpus - 1) + 1;
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
+ for (i = 0; i < ms->smp.cpus; i++) {
+ x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
+ }
+}
+
+CpuInstanceProperties
+x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+ const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+ assert(cpu_index < possible_cpus->len);
+ return possible_cpus->cpus[cpu_index].props;
+}
+
+int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
+{
+ X86CPUTopoInfo topo;
+ PCMachineState *pcms = PC_MACHINE(ms);
+
+ assert(idx < ms->possible_cpus->len);
+ x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ pcms->smp_dies, ms->smp.cores,
+ ms->smp.threads, &topo);
+ return topo.pkg_id % ms->numa_state->num_nodes;
+}
+
+const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
+{
+ PCMachineState *pcms = PC_MACHINE(ms);
+ int i;
+ unsigned int max_cpus = ms->smp.max_cpus;
+
+ if (ms->possible_cpus) {
+ /*
+ * make sure that max_cpus hasn't changed since the first use, i.e.
+ * -smp hasn't been parsed after it
+ */
+ assert(ms->possible_cpus->len == max_cpus);
+ return ms->possible_cpus;
+ }
+
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+ sizeof(CPUArchId) * max_cpus);
+ ms->possible_cpus->len = max_cpus;
+ for (i = 0; i < ms->possible_cpus->len; i++) {
+ X86CPUTopoInfo topo;
+
+ ms->possible_cpus->cpus[i].type = ms->cpu_type;
+ ms->possible_cpus->cpus[i].vcpus_count = 1;
+ ms->possible_cpus->cpus[i].arch_id =
+ x86_cpu_apic_id_from_index(pcms, i);
+ x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+ pcms->smp_dies, ms->smp.cores,
+ ms->smp.threads, &topo);
+ ms->possible_cpus->cpus[i].props.has_socket_id = true;
+ ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
+ if (pcms->smp_dies > 1) {
+ ms->possible_cpus->cpus[i].props.has_die_id = true;
+ ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
+ }
+ ms->possible_cpus->cpus[i].props.has_core_id = true;
+ ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
+ ms->possible_cpus->cpus[i].props.has_thread_id = true;
+ ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
+ }
+ return ms->possible_cpus;
+}
+
+static long get_file_size(FILE *f)
+{
+ long where, size;
+
+ /* XXX: on Unix systems, using fstat() probably makes more sense */
+
+ where = ftell(f);
+ fseek(f, 0, SEEK_END);
+ size = ftell(f);
+ fseek(f, where, SEEK_SET);
+
+ return size;
+}
+
+struct setup_data {
+ uint64_t next;
+ uint32_t type;
+ uint32_t len;
+ uint8_t data[0];
+} __attribute__((packed));
+
+
+/*
+ * The entry point into the kernel for PVH boot is different from
+ * the native entry point. The PVH entry is defined by the x86/HVM
+ * direct boot ABI and is available in an ELFNOTE in the kernel binary.
+ *
+ * This function is passed to load_elf() when it is called from
+ * load_elfboot() which then additionally checks for an ELF Note of
+ * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
+ * parse the PVH entry address from the ELF Note.
+ *
+ * Due to trickery in elf_opts.h, load_elf() is actually available as
+ * load_elf32() or load_elf64() and this routine needs to be able
+ * to deal with being called as 32 or 64 bit.
+ *
+ * The address of the PVH entry point is saved to the 'pvh_start_addr'
+ * global variable. (although the entry point is 32-bit, the kernel
+ * binary can be either 32-bit or 64-bit).
+ */
+static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
+{
+ size_t *elf_note_data_addr;
+
+ /* Check if ELF Note header passed in is valid */
+ if (arg1 == NULL) {
+ return 0;
+ }
+
+ if (is64) {
+ struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
+ uint64_t nhdr_size64 = sizeof(struct elf64_note);
+ uint64_t phdr_align = *(uint64_t *)arg2;
+ uint64_t nhdr_namesz = nhdr64->n_namesz;
+
+ elf_note_data_addr =
+ ((void *)nhdr64) + nhdr_size64 +
+ QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
+ } else {
+ struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
+ uint32_t nhdr_size32 = sizeof(struct elf32_note);
+ uint32_t phdr_align = *(uint32_t *)arg2;
+ uint32_t nhdr_namesz = nhdr32->n_namesz;
+
+ elf_note_data_addr =
+ ((void *)nhdr32) + nhdr_size32 +
+ QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
+ }
+
+ pvh_start_addr = *elf_note_data_addr;
+
+ return pvh_start_addr;
+}
+
+static bool load_elfboot(const char *kernel_filename,
+ int kernel_file_size,
+ uint8_t *header,
+ size_t pvh_xen_start_addr,
+ FWCfgState *fw_cfg)
+{
+ uint32_t flags = 0;
+ uint32_t mh_load_addr = 0;
+ uint32_t elf_kernel_size = 0;
+ uint64_t elf_entry;
+ uint64_t elf_low, elf_high;
+ int kernel_size;
+
+ if (ldl_p(header) != 0x464c457f) {
+ return false; /* no elfboot */
+ }
+
+ bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
+ flags = elf_is64 ?
+ ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
+
+ if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
+ error_report("elfboot unsupported flags = %x", flags);
+ exit(1);
+ }
+
+ uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
+ kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
+ NULL, &elf_note_type, &elf_entry,
+ &elf_low, &elf_high, 0, I386_ELF_MACHINE,
+ 0, 0);
+
+ if (kernel_size < 0) {
+ error_report("Error while loading elf kernel");
+ exit(1);
+ }
+ mh_load_addr = elf_low;
+ elf_kernel_size = elf_high - elf_low;
+
+ if (pvh_start_addr == 0) {
+ error_report("Error loading uncompressed kernel without PVH ELF Note");
+ exit(1);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
+
+ return true;
+}
+
+void x86_load_linux(PCMachineState *pcms,
+ FWCfgState *fw_cfg)
+{
+ uint16_t protocol;
+ int setup_size, kernel_size, cmdline_size;
+ int dtb_size, setup_data_offset;
+ uint32_t initrd_max;
+ uint8_t header[8192], *setup, *kernel;
+ hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ FILE *f;
+ char *vmode;
+ MachineState *machine = MACHINE(pcms);
+ PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ struct setup_data *setup_data;
+ const char *kernel_filename = machine->kernel_filename;
+ const char *initrd_filename = machine->initrd_filename;
+ const char *dtb_filename = machine->dtb;
+ const char *kernel_cmdline = machine->kernel_cmdline;
+
+ /* Align to 16 bytes as a paranoia measure */
+ cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
+
+ /* load the kernel header */
+ f = fopen(kernel_filename, "rb");
+ if (!f) {
+ fprintf(stderr, "qemu: could not open kernel file '%s': %s\n",
+ kernel_filename, strerror(errno));
+ exit(1);
+ }
+
+ kernel_size = get_file_size(f);
+ if (!kernel_size ||
+ fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
+ MIN(ARRAY_SIZE(header), kernel_size)) {
+ fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
+ kernel_filename, strerror(errno));
+ exit(1);
+ }
+
+ /* kernel protocol version */
+ if (ldl_p(header + 0x202) == 0x53726448) {
+ protocol = lduw_p(header + 0x206);
+ } else {
+ /*
+ * This could be a multiboot kernel. If it is, let's stop treating it
+ * like a Linux kernel.
+ * Note: some multiboot images could be in the ELF format (the same of
+ * PVH), so we try multiboot first since we check the multiboot magic
+ * header before to load it.
+ */
+ if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
+ kernel_cmdline, kernel_size, header)) {
+ return;
+ }
+ /*
+ * Check if the file is an uncompressed kernel file (ELF) and load it,
+ * saving the PVH entry point used by the x86/HVM direct boot ABI.
+ * If load_elfboot() is successful, populate the fw_cfg info.
+ */
+ if (pcmc->pvh_enabled &&
+ load_elfboot(kernel_filename, kernel_size,
+ header, pvh_start_addr, fw_cfg)) {
+ fclose(f);
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
+ strlen(kernel_cmdline) + 1);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
+ header, sizeof(header));
+
+ /* load initrd */
+ if (initrd_filename) {
+ GMappedFile *mapped_file;
+ gsize initrd_size;
+ gchar *initrd_data;
+ GError *gerr = NULL;
+
+ mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
+ if (!mapped_file) {
+ fprintf(stderr, "qemu: error reading initrd %s: %s\n",
+ initrd_filename, gerr->message);
+ exit(1);
+ }
+ pcms->initrd_mapped_file = mapped_file;
+
+ initrd_data = g_mapped_file_get_contents(mapped_file);
+ initrd_size = g_mapped_file_get_length(mapped_file);
+ initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ if (initrd_size >= initrd_max) {
+ fprintf(stderr, "qemu: initrd is too large, cannot support."
+ "(max: %"PRIu32", need %"PRId64")\n",
+ initrd_max, (uint64_t)initrd_size);
+ exit(1);
+ }
+
+ initrd_addr = (initrd_max - initrd_size) & ~4095;
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
+ initrd_size);
+ }
+
+ option_rom[nb_option_roms].bootindex = 0;
+ option_rom[nb_option_roms].name = "pvh.bin";
+ nb_option_roms++;
+
+ return;
+ }
+ protocol = 0;
+ }
+
+ if (protocol < 0x200 || !(header[0x211] & 0x01)) {
+ /* Low kernel */
+ real_addr = 0x90000;
+ cmdline_addr = 0x9a000 - cmdline_size;
+ prot_addr = 0x10000;
+ } else if (protocol < 0x202) {
+ /* High but ancient kernel */
+ real_addr = 0x90000;
+ cmdline_addr = 0x9a000 - cmdline_size;
+ prot_addr = 0x100000;
+ } else {
+ /* High and recent kernel */
+ real_addr = 0x10000;
+ cmdline_addr = 0x20000;
+ prot_addr = 0x100000;
+ }
+
+ /* highest address for loading the initrd */
+ if (protocol >= 0x20c &&
+ lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
+ /*
+ * Linux has supported initrd up to 4 GB for a very long time (2007,
+ * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
+ * though it only sets initrd_max to 2 GB to "work around bootloader
+ * bugs". Luckily, QEMU firmware(which does something like bootloader)
+ * has supported this.
+ *
+ * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
+ * be loaded into any address.
+ *
+ * In addition, initrd_max is uint32_t simply because QEMU doesn't
+ * support the 64-bit boot protocol (specifically the ext_ramdisk_image
+ * field).
+ *
+ * Therefore here just limit initrd_max to UINT32_MAX simply as well.
+ */
+ initrd_max = UINT32_MAX;
+ } else if (protocol >= 0x203) {
+ initrd_max = ldl_p(header + 0x22c);
+ } else {
+ initrd_max = 0x37ffffff;
+ }
+
+ if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
+ initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ }
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
+
+ if (protocol >= 0x202) {
+ stl_p(header + 0x228, cmdline_addr);
+ } else {
+ stw_p(header + 0x20, 0xA33F);
+ stw_p(header + 0x22, cmdline_addr - real_addr);
+ }
+
+ /* handle vga= parameter */
+ vmode = strstr(kernel_cmdline, "vga=");
+ if (vmode) {
+ unsigned int video_mode;
+ int ret;
+ /* skip "vga=" */
+ vmode += 4;
+ if (!strncmp(vmode, "normal", 6)) {
+ video_mode = 0xffff;
+ } else if (!strncmp(vmode, "ext", 3)) {
+ video_mode = 0xfffe;
+ } else if (!strncmp(vmode, "ask", 3)) {
+ video_mode = 0xfffd;
+ } else {
+ ret = qemu_strtoui(vmode, NULL, 0, &video_mode);
+ if (ret != 0) {
+ fprintf(stderr, "qemu: can't parse 'vga' parameter: %s\n",
+ strerror(-ret));
+ exit(1);
+ }
+ }
+ stw_p(header + 0x1fa, video_mode);
+ }
+
+ /* loader type */
+ /*
+ * High nybble = B reserved for QEMU; low nybble is revision number.
+ * If this code is substantially changed, you may want to consider
+ * incrementing the revision.
+ */
+ if (protocol >= 0x200) {
+ header[0x210] = 0xB0;
+ }
+ /* heap */
+ if (protocol >= 0x201) {
+ header[0x211] |= 0x80; /* CAN_USE_HEAP */
+ stw_p(header + 0x224, cmdline_addr - real_addr - 0x200);
+ }
+
+ /* load initrd */
+ if (initrd_filename) {
+ GMappedFile *mapped_file;
+ gsize initrd_size;
+ gchar *initrd_data;
+ GError *gerr = NULL;
+
+ if (protocol < 0x200) {
+ fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
+ exit(1);
+ }
+
+ mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
+ if (!mapped_file) {
+ fprintf(stderr, "qemu: error reading initrd %s: %s\n",
+ initrd_filename, gerr->message);
+ exit(1);
+ }
+ pcms->initrd_mapped_file = mapped_file;
+
+ initrd_data = g_mapped_file_get_contents(mapped_file);
+ initrd_size = g_mapped_file_get_length(mapped_file);
+ if (initrd_size >= initrd_max) {
+ fprintf(stderr, "qemu: initrd is too large, cannot support."
+ "(max: %"PRIu32", need %"PRId64")\n",
+ initrd_max, (uint64_t)initrd_size);
+ exit(1);
+ }
+
+ initrd_addr = (initrd_max - initrd_size) & ~4095;
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
+
+ stl_p(header + 0x218, initrd_addr);
+ stl_p(header + 0x21c, initrd_size);
+ }
+
+ /* load kernel and setup */
+ setup_size = header[0x1f1];
+ if (setup_size == 0) {
+ setup_size = 4;
+ }
+ setup_size = (setup_size + 1) * 512;
+ if (setup_size > kernel_size) {
+ fprintf(stderr, "qemu: invalid kernel header\n");
+ exit(1);
+ }
+ kernel_size -= setup_size;
+
+ setup = g_malloc(setup_size);
+ kernel = g_malloc(kernel_size);
+ fseek(f, 0, SEEK_SET);
+ if (fread(setup, 1, setup_size, f) != setup_size) {
+ fprintf(stderr, "fread() failed\n");
+ exit(1);
+ }
+ if (fread(kernel, 1, kernel_size, f) != kernel_size) {
+ fprintf(stderr, "fread() failed\n");
+ exit(1);
+ }
+ fclose(f);
+
+ /* append dtb to kernel */
+ if (dtb_filename) {
+ if (protocol < 0x209) {
+ fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
+ exit(1);
+ }
+
+ dtb_size = get_image_size(dtb_filename);
+ if (dtb_size <= 0) {
+ fprintf(stderr, "qemu: error reading dtb %s: %s\n",
+ dtb_filename, strerror(errno));
+ exit(1);
+ }
+
+ setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
+ kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
+ kernel = g_realloc(kernel, kernel_size);
+
+ stq_p(header + 0x250, prot_addr + setup_data_offset);
+
+ setup_data = (struct setup_data *)(kernel + setup_data_offset);
+ setup_data->next = 0;
+ setup_data->type = cpu_to_le32(SETUP_DTB);
+ setup_data->len = cpu_to_le32(dtb_size);
+
+ load_image_size(dtb_filename, setup_data->data, dtb_size);
+ }
+
+ memcpy(setup, header, MIN(sizeof(header), setup_size));
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
+
+ option_rom[nb_option_roms].bootindex = 0;
+ option_rom[nb_option_roms].name = "linuxboot.bin";
+ if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
+ option_rom[nb_option_roms].name = "linuxboot_dma.bin";
+ }
+ nb_option_roms++;
+}
+
+void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
+{
+ char *filename;
+ MemoryRegion *bios, *isa_bios;
+ int bios_size, isa_bios_size;
+ int ret;
+
+ /* BIOS load */
+ if (bios_name == NULL) {
+ bios_name = BIOS_FILENAME;
+ }
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (filename) {
+ bios_size = get_image_size(filename);
+ } else {
+ bios_size = -1;
+ }
+ if (bios_size <= 0 ||
+ (bios_size % 65536) != 0) {
+ goto bios_error;
+ }
+ bios = g_malloc(sizeof(*bios));
+ memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal);
+ if (!isapc_ram_fw) {
+ memory_region_set_readonly(bios, true);
+ }
+ ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
+ if (ret != 0) {
+ bios_error:
+ fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
+ exit(1);
+ }
+ g_free(filename);
+
+ /* map the last 128KB of the BIOS in ISA space */
+ isa_bios_size = MIN(bios_size, 128 * KiB);
+ isa_bios = g_malloc(sizeof(*isa_bios));
+ memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
+ bios_size - isa_bios_size, isa_bios_size);
+ memory_region_add_subregion_overlap(rom_memory,
+ 0x100000 - isa_bios_size,
+ isa_bios,
+ 1);
+ if (!isapc_ram_fw) {
+ memory_region_set_readonly(isa_bios, true);
+ }
+
+ /* map all the bios at the top of memory */
+ memory_region_add_subregion(rom_memory,
+ (uint32_t)(-bios_size),
+ bios);
+}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7082b06..f135ae8 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -198,7 +198,6 @@ bool pc_machine_is_smm_enabled(PCMachineState *pcms);
void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
-void x86_cpus_init(PCMachineState *pcms);
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
void pc_smp_parse(MachineState *ms, QemuOpts *opts);
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
new file mode 100644
index 0000000..71e2b69
--- /dev/null
+++ b/include/hw/i386/x86.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019 Red Hat, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_I386_X86_H
+#define HW_I386_X86_H
+
+#include "hw/boards.h"
+
+uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
+ unsigned int cpu_index);
+void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp);
+void x86_cpus_init(PCMachineState *pcms);
+CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
+ unsigned cpu_index);
+int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
+const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
+
+void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
+
+void x86_load_linux(PCMachineState *x86ms, FWCfgState *fw_cfg);
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 14/39] hw/i386: split PCMachineState deriving X86MachineState from it
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (12 preceding siblings ...)
2019-10-24 14:03 ` [PULL 13/39] hw/i386/pc: move shared x86 functions to x86.c and export them Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 15/39] hw/i386: make x86.c independent from PCMachineState Paolo Bonzini
` (26 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
Split up PCMachineState and PCMachineClass and derive X86MachineState
and X86MachineClass from them. This allows sharing code with non-PC
x86 machine types.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/cpu_hotplug.c | 10 +--
hw/i386/acpi-build.c | 29 ++++----
hw/i386/amd_iommu.c | 3 +-
hw/i386/intel_iommu.c | 3 +-
hw/i386/pc.c | 178 +++++++++++++++++---------------------------------
hw/i386/pc_piix.c | 43 ++++++------
hw/i386/pc_q35.c | 35 +++++-----
hw/i386/x86.c | 140 ++++++++++++++++++++++++++++++++++-----
hw/i386/xen/xen-hvm.c | 28 ++++----
hw/intc/ioapic.c | 2 +-
include/hw/i386/pc.h | 27 +-------
include/hw/i386/x86.h | 58 +++++++++++++++-
12 files changed, 326 insertions(+), 230 deletions(-)
diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c
index 6e8293a..3ac2045 100644
--- a/hw/acpi/cpu_hotplug.c
+++ b/hw/acpi/cpu_hotplug.c
@@ -128,7 +128,7 @@ void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine,
Aml *one = aml_int(1);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
- PCMachineState *pcms = PC_MACHINE(machine);
+ X86MachineState *x86ms = X86_MACHINE(machine);
/*
* _MAT method - creates an madt apic buffer
@@ -236,9 +236,9 @@ void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine,
/* The current AML generator can cover the APIC ID range [0..255],
* inclusive, for VCPU hotplug. */
QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
- if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
+ if (x86ms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
error_report("max_cpus is too large. APIC ID of last CPU is %u",
- pcms->apic_id_limit - 1);
+ x86ms->apic_id_limit - 1);
exit(1);
}
@@ -315,8 +315,8 @@ void build_legacy_cpu_hotplug_aml(Aml *ctx, MachineState *machine,
* ith up to 255 elements. Windows guests up to win2k8 fail when
* VarPackageOp is used.
*/
- pkg = pcms->apic_id_limit <= 255 ? aml_package(pcms->apic_id_limit) :
- aml_varpackage(pcms->apic_id_limit);
+ pkg = x86ms->apic_id_limit <= 255 ? aml_package(x86ms->apic_id_limit) :
+ aml_varpackage(x86ms->apic_id_limit);
for (i = 0, apic_idx = 0; i < apic_ids->len; i++) {
int apic_id = apic_ids->cpus[i].arch_id;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1d077a7..bc0256e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -361,6 +361,7 @@ static void
build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
{
MachineClass *mc = MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
int madt_start = table_data->len;
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
@@ -390,7 +391,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
io_apic->interrupt = cpu_to_le32(0);
- if (pcms->apic_xrupt_override) {
+ if (x86ms->apic_xrupt_override) {
intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
intsrcovr->length = sizeof(*intsrcovr);
@@ -1831,6 +1832,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
CrsRangeSet crs_range_set;
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
+ X86MachineState *x86ms = X86_MACHINE(machine);
AcpiMcfgInfo mcfg;
uint32_t nr_mem = machine->ram_slots;
int root_bus_limit = 0xFF;
@@ -2103,7 +2105,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
* with half of the 16-bit control register. Hence, the total size
* of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
* DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
- uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
+ uint8_t io_size = object_property_get_bool(OBJECT(x86ms->fw_cfg),
"dma_enabled", NULL) ?
ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
FW_CFG_CTL_SIZE;
@@ -2336,6 +2338,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
int srat_start, numa_start, slots;
uint64_t mem_len, mem_base, next_base;
MachineClass *mc = MACHINE_GET_CLASS(machine);
+ X86MachineState *x86ms = X86_MACHINE(machine);
const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
PCMachineState *pcms = PC_MACHINE(machine);
ram_addr_t hotplugabble_address_space_size =
@@ -2406,16 +2409,16 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
}
/* Cut out the ACPI_PCI hole */
- if (mem_base <= pcms->below_4g_mem_size &&
- next_base > pcms->below_4g_mem_size) {
- mem_len -= next_base - pcms->below_4g_mem_size;
+ if (mem_base <= x86ms->below_4g_mem_size &&
+ next_base > x86ms->below_4g_mem_size) {
+ mem_len -= next_base - x86ms->below_4g_mem_size;
if (mem_len > 0) {
numamem = acpi_data_push(table_data, sizeof *numamem);
build_srat_memory(numamem, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
mem_base = 1ULL << 32;
- mem_len = next_base - pcms->below_4g_mem_size;
+ mem_len = next_base - x86ms->below_4g_mem_size;
next_base = mem_base + mem_len;
}
@@ -2634,6 +2637,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(machine);
GArray *table_offsets;
unsigned facs, dsdt, rsdt, fadt;
AcpiPmInfo pm;
@@ -2795,7 +2799,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
*/
int legacy_aml_len =
pcmc->legacy_acpi_table_size +
- ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
+ ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
int legacy_table_size =
ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
ACPI_BUILD_ALIGN_SIZE);
@@ -2885,13 +2889,14 @@ void acpi_setup(void)
{
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
AcpiBuildTables tables;
AcpiBuildState *build_state;
Object *vmgenid_dev;
TPMIf *tpm;
static FwCfgTPMConfig tpm_config;
- if (!pcms->fw_cfg) {
+ if (!x86ms->fw_cfg) {
ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
return;
}
@@ -2922,7 +2927,7 @@ void acpi_setup(void)
acpi_add_rom_blob(acpi_build_update, build_state,
tables.linker->cmd_blob, "etc/table-loader", 0);
- fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
+ fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
tables.tcpalog->data, acpi_data_len(tables.tcpalog));
tpm = tpm_find();
@@ -2932,13 +2937,13 @@ void acpi_setup(void)
.tpm_version = tpm_get_version(tpm),
.tpmppi_version = TPM_PPI_VERSION_1_30
};
- fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config",
+ fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
&tpm_config, sizeof tpm_config);
}
vmgenid_dev = find_vmgenid_dev();
if (vmgenid_dev) {
- vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
+ vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
tables.vmgenid);
}
@@ -2951,7 +2956,7 @@ void acpi_setup(void)
uint32_t rsdp_size = acpi_data_len(tables.rsdp);
build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
- fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
+ fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
acpi_build_update, NULL, build_state,
build_state->rsdp, rsdp_size, true);
build_state->rsdp_mr = NULL;
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index d372636..d55dbf0 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1540,6 +1540,7 @@ static void amdvi_realize(DeviceState *dev, Error **err)
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
MachineState *ms = MACHINE(qdev_get_machine());
PCMachineState *pcms = PC_MACHINE(ms);
+ X86MachineState *x86ms = X86_MACHINE(ms);
PCIBus *bus = pcms->bus;
s->iotlb = g_hash_table_new_full(amdvi_uint64_hash,
@@ -1568,7 +1569,7 @@ static void amdvi_realize(DeviceState *dev, Error **err)
}
/* Pseudo address space under root PCI bus. */
- pcms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID);
+ x86ms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID);
/* set up MMIO */
memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 771bed2..14e4e6a 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3733,6 +3733,7 @@ static void vtd_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
PCMachineState *pcms = PC_MACHINE(ms);
+ X86MachineState *x86ms = X86_MACHINE(ms);
PCIBus *bus = pcms->bus;
IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
@@ -3773,7 +3774,7 @@ static void vtd_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
/* Pseudo address space under root PCI bus. */
- pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
+ x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
qemu_add_machine_init_done_notifier(&vtd_machine_done_notify);
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 4a1bc95..e6ad1f1 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -79,7 +79,6 @@
#include "qapi/qapi-visit-common.h"
#include "qapi/visitor.h"
#include "hw/core/cpu.h"
-#include "hw/nmi.h"
#include "hw/usb.h"
#include "hw/i386/intel_iommu.h"
#include "hw/net/ne2000-isa.h"
@@ -680,17 +679,18 @@ void pc_cmos_init(PCMachineState *pcms,
{
int val;
static pc_cmos_init_late_arg arg;
+ X86MachineState *x86ms = X86_MACHINE(pcms);
/* various important CMOS locations needed by PC/Bochs bios */
/* memory size */
/* base memory (first MiB) */
- val = MIN(pcms->below_4g_mem_size / KiB, 640);
+ val = MIN(x86ms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
- if (pcms->below_4g_mem_size > 1 * MiB) {
- val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
+ if (x86ms->below_4g_mem_size > 1 * MiB) {
+ val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
} else {
val = 0;
}
@@ -701,8 +701,8 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
- if (pcms->below_4g_mem_size > 16 * MiB) {
- val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
+ if (x86ms->below_4g_mem_size > 16 * MiB) {
+ val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
} else {
val = 0;
}
@@ -711,14 +711,14 @@ void pc_cmos_init(PCMachineState *pcms,
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
/* memory above 4GiB */
- val = pcms->above_4g_mem_size / 65536;
+ val = x86ms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
object_property_add_link(OBJECT(pcms), "rtc_state",
TYPE_ISA_DEVICE,
- (Object **)&pcms->rtc,
+ (Object **)&x86ms->rtc,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG, &error_abort);
object_property_set_link(OBJECT(pcms), OBJECT(s),
@@ -907,7 +907,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
*/
void pc_smp_parse(MachineState *ms, QemuOpts *opts)
{
- PCMachineState *pcms = PC_MACHINE(ms);
+ X86MachineState *x86ms = X86_MACHINE(ms);
if (opts) {
unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
@@ -971,7 +971,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
- pcms->smp_dies = dies;
+ x86ms->smp_dies = dies;
}
if (ms->smp.cpus > 1) {
@@ -1024,10 +1024,11 @@ void pc_machine_done(Notifier *notifier, void *data)
{
PCMachineState *pcms = container_of(notifier,
PCMachineState, machine_done);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
PCIBus *bus = pcms->bus;
/* set the number of CPUs */
- rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
+ rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
if (bus) {
int extra_hosts = 0;
@@ -1038,23 +1039,23 @@ void pc_machine_done(Notifier *notifier, void *data)
extra_hosts++;
}
}
- if (extra_hosts && pcms->fw_cfg) {
+ if (extra_hosts && x86ms->fw_cfg) {
uint64_t *val = g_malloc(sizeof(*val));
*val = cpu_to_le64(extra_hosts);
- fw_cfg_add_file(pcms->fw_cfg,
+ fw_cfg_add_file(x86ms->fw_cfg,
"etc/extra-pci-roots", val, sizeof(*val));
}
}
acpi_setup();
- if (pcms->fw_cfg) {
- fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg);
- fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg);
+ if (x86ms->fw_cfg) {
+ fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
+ fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
/* update FW_CFG_NB_CPUS to account for -device added CPUs */
- fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
+ fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
}
- if (pcms->apic_id_limit > 255 && !xen_enabled()) {
+ if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
@@ -1072,8 +1073,9 @@ void pc_guest_info_init(PCMachineState *pcms)
{
int i;
MachineState *ms = MACHINE(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
- pcms->apic_xrupt_override = kvm_allows_irq0_override();
+ x86ms->apic_xrupt_override = kvm_allows_irq0_override();
pcms->numa_nodes = ms->numa_state->num_nodes;
pcms->node_mem = g_malloc0(pcms->numa_nodes *
sizeof *pcms->node_mem);
@@ -1098,11 +1100,12 @@ void xen_load_linux(PCMachineState *pcms)
{
int i;
FWCfgState *fw_cfg;
+ X86MachineState *x86ms = X86_MACHINE(pcms);
assert(MACHINE(pcms)->kernel_filename != NULL);
fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
rom_set_fw(fw_cfg);
x86_load_linux(pcms, fw_cfg);
@@ -1113,7 +1116,7 @@ void xen_load_linux(PCMachineState *pcms)
!strcmp(option_rom[i].name, "multiboot.bin"));
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
}
- pcms->fw_cfg = fw_cfg;
+ x86ms->fw_cfg = fw_cfg;
}
void pc_memory_init(PCMachineState *pcms,
@@ -1128,9 +1131,10 @@ void pc_memory_init(PCMachineState *pcms,
MachineState *machine = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
- assert(machine->ram_size == pcms->below_4g_mem_size +
- pcms->above_4g_mem_size);
+ assert(machine->ram_size == x86ms->below_4g_mem_size +
+ x86ms->above_4g_mem_size);
linux_boot = (machine->kernel_filename != NULL);
@@ -1144,17 +1148,17 @@ void pc_memory_init(PCMachineState *pcms,
*ram_memory = ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
- 0, pcms->below_4g_mem_size);
+ 0, x86ms->below_4g_mem_size);
memory_region_add_subregion(system_memory, 0, ram_below_4g);
- e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
- if (pcms->above_4g_mem_size > 0) {
+ e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
+ if (x86ms->above_4g_mem_size > 0) {
ram_above_4g = g_malloc(sizeof(*ram_above_4g));
memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
- pcms->below_4g_mem_size,
- pcms->above_4g_mem_size);
+ x86ms->below_4g_mem_size,
+ x86ms->above_4g_mem_size);
memory_region_add_subregion(system_memory, 0x100000000ULL,
ram_above_4g);
- e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
+ e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
}
if (!pcmc->has_reserved_memory &&
@@ -1188,7 +1192,7 @@ void pc_memory_init(PCMachineState *pcms,
}
machine->device_memory->base =
- ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
+ ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
if (pcmc->enforce_aligned_dimm) {
/* size device region assuming 1G page max alignment per slot */
@@ -1223,7 +1227,7 @@ void pc_memory_init(PCMachineState *pcms,
1);
fw_cfg = fw_cfg_arch_create(machine,
- pcms->boot_cpus, pcms->apic_id_limit);
+ x86ms->boot_cpus, x86ms->apic_id_limit);
rom_set_fw(fw_cfg);
@@ -1246,10 +1250,10 @@ void pc_memory_init(PCMachineState *pcms,
for (i = 0; i < nb_option_roms; i++) {
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
}
- pcms->fw_cfg = fw_cfg;
+ x86ms->fw_cfg = fw_cfg;
/* Init default IOAPIC address space */
- pcms->ioapic_as = &address_space_memory;
+ x86ms->ioapic_as = &address_space_memory;
/* Init ACPI memory hotplug IO base address */
pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
@@ -1264,6 +1268,7 @@ uint64_t pc_pci_hole64_start(void)
PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
MachineState *ms = MACHINE(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
uint64_t hole64_start = 0;
if (pcmc->has_reserved_memory && ms->device_memory->base) {
@@ -1272,7 +1277,7 @@ uint64_t pc_pci_hole64_start(void)
hole64_start += memory_region_size(&ms->device_memory->mr);
}
} else {
- hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
+ hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
}
return ROUND_UP(hole64_start, 1 * GiB);
@@ -1611,6 +1616,7 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
Error *local_err = NULL;
X86CPU *cpu = X86_CPU(dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
if (pcms->acpi_dev) {
hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
@@ -1620,12 +1626,12 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
}
/* increment the number of CPUs */
- pcms->boot_cpus++;
- if (pcms->rtc) {
- rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
+ x86ms->boot_cpus++;
+ if (x86ms->rtc) {
+ rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
}
- if (pcms->fw_cfg) {
- fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
+ if (x86ms->fw_cfg) {
+ fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
}
found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
@@ -1671,6 +1677,7 @@ static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
Error *local_err = NULL;
X86CPU *cpu = X86_CPU(dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
if (local_err) {
@@ -1682,10 +1689,10 @@ static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
object_property_set_bool(OBJECT(dev), false, "realized", NULL);
/* decrement the number of CPUs */
- pcms->boot_cpus--;
+ x86ms->boot_cpus--;
/* Update the number of CPUs in CMOS */
- rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
- fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
+ rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
+ fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
out:
error_propagate(errp, local_err);
}
@@ -1701,6 +1708,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
CPUX86State *env = &cpu->env;
MachineState *ms = MACHINE(hotplug_dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
unsigned int smp_cores = ms->smp.cores;
unsigned int smp_threads = ms->smp.threads;
@@ -1710,7 +1718,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
- env->nr_dies = pcms->smp_dies;
+ env->nr_dies = x86ms->smp_dies;
/*
* If APIC ID is not set,
@@ -1718,13 +1726,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
*/
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
int max_socket = (ms->smp.max_cpus - 1) /
- smp_threads / smp_cores / pcms->smp_dies;
+ smp_threads / smp_cores / x86ms->smp_dies;
/*
* die-id was optional in QEMU 4.0 and older, so keep it optional
* if there's only one die per socket.
*/
- if (cpu->die_id < 0 && pcms->smp_dies == 1) {
+ if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
cpu->die_id = 0;
}
@@ -1739,9 +1747,9 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
if (cpu->die_id < 0) {
error_setg(errp, "CPU die-id is not set");
return;
- } else if (cpu->die_id > pcms->smp_dies - 1) {
+ } else if (cpu->die_id > x86ms->smp_dies - 1) {
error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
- cpu->die_id, pcms->smp_dies - 1);
+ cpu->die_id, x86ms->smp_dies - 1);
return;
}
if (cpu->core_id < 0) {
@@ -1765,7 +1773,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo.die_id = cpu->die_id;
topo.core_id = cpu->core_id;
topo.smt_id = cpu->thread_id;
- cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
+ cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
smp_threads, &topo);
}
@@ -1773,7 +1781,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
- x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
+ x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
smp_cores, smp_threads, &topo);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
@@ -1795,7 +1803,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
- x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
+ x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
smp_cores, smp_threads, &topo);
if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
@@ -1977,45 +1985,6 @@ pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
visit_type_int(v, name, &value, errp);
}
-static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
- const char *name, void *opaque,
- Error **errp)
-{
- PCMachineState *pcms = PC_MACHINE(obj);
- uint64_t value = pcms->max_ram_below_4g;
-
- visit_type_size(v, name, &value, errp);
-}
-
-static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
- const char *name, void *opaque,
- Error **errp)
-{
- PCMachineState *pcms = PC_MACHINE(obj);
- Error *error = NULL;
- uint64_t value;
-
- visit_type_size(v, name, &value, &error);
- if (error) {
- error_propagate(errp, error);
- return;
- }
- if (value > 4 * GiB) {
- error_setg(&error,
- "Machine option 'max-ram-below-4g=%"PRIu64
- "' expects size less than or equal to 4G", value);
- error_propagate(errp, error);
- return;
- }
-
- if (value < 1 * MiB) {
- warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
- "BIOS may not work with less than 1MiB", value);
- }
-
- pcms->max_ram_below_4g = value;
-}
-
static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2121,7 +2090,6 @@ static void pc_machine_initfn(Object *obj)
{
PCMachineState *pcms = PC_MACHINE(obj);
- pcms->max_ram_below_4g = 0; /* use default */
pcms->smm = ON_OFF_AUTO_AUTO;
#ifdef CONFIG_VMPORT
pcms->vmport = ON_OFF_AUTO_AUTO;
@@ -2133,7 +2101,6 @@ static void pc_machine_initfn(Object *obj)
pcms->smbus_enabled = true;
pcms->sata_enabled = true;
pcms->pit_enabled = true;
- pcms->smp_dies = 1;
pc_system_flash_create(pcms);
}
@@ -2164,23 +2131,6 @@ static void pc_machine_wakeup(MachineState *machine)
cpu_synchronize_all_post_reset();
}
-static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
-{
- /* cpu index isn't used */
- CPUState *cs;
-
- CPU_FOREACH(cs) {
- X86CPU *cpu = X86_CPU(cs);
-
- if (!cpu->apic_state) {
- cpu_interrupt(cs, CPU_INTERRUPT_NMI);
- } else {
- apic_deliver_nmi(cpu->apic_state);
- }
- }
-}
-
-
static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
{
X86IOMMUState *iommu = x86_iommu_get_default();
@@ -2205,7 +2155,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
- NMIClass *nc = NMI_CLASS(oc);
pcmc->pci_enabled = true;
pcmc->has_acpi_build = true;
@@ -2241,7 +2190,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
hc->plug = pc_machine_device_plug_cb;
hc->unplug_request = pc_machine_device_unplug_request_cb;
hc->unplug = pc_machine_device_unplug_cb;
- nc->nmi_monitor_handler = x86_nmi;
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->numa_mem_supported = true;
@@ -2250,13 +2198,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
pc_machine_get_device_memory_region_size, NULL,
NULL, NULL, &error_abort);
- object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
- pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
- NULL, NULL, &error_abort);
-
- object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
- "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
-
object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
pc_machine_get_smm, pc_machine_set_smm,
NULL, NULL, &error_abort);
@@ -2281,7 +2222,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo pc_machine_info = {
.name = TYPE_PC_MACHINE,
- .parent = TYPE_MACHINE,
+ .parent = TYPE_X86_MACHINE,
.abstract = true,
.instance_size = sizeof(PCMachineState),
.instance_init = pc_machine_initfn,
@@ -2289,7 +2230,6 @@ static const TypeInfo pc_machine_info = {
.class_init = pc_machine_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
- { TYPE_NMI },
{ }
},
};
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 1396451..0afa8fe 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -74,6 +74,7 @@ static void pc_init1(MachineState *machine,
{
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *system_io = get_system_io();
int i;
@@ -126,11 +127,11 @@ static void pc_init1(MachineState *machine,
if (xen_enabled()) {
xen_hvm_init(pcms, &ram_memory);
} else {
- if (!pcms->max_ram_below_4g) {
- pcms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */
+ if (!x86ms->max_ram_below_4g) {
+ x86ms->max_ram_below_4g = 0xe0000000; /* default: 3.5G */
}
- lowmem = pcms->max_ram_below_4g;
- if (machine->ram_size >= pcms->max_ram_below_4g) {
+ lowmem = x86ms->max_ram_below_4g;
+ if (machine->ram_size >= x86ms->max_ram_below_4g) {
if (pcmc->gigabyte_align) {
if (lowmem > 0xc0000000) {
lowmem = 0xc0000000;
@@ -139,17 +140,17 @@ static void pc_init1(MachineState *machine,
warn_report("Large machine and max_ram_below_4g "
"(%" PRIu64 ") not a multiple of 1G; "
"possible bad performance.",
- pcms->max_ram_below_4g);
+ x86ms->max_ram_below_4g);
}
}
}
if (machine->ram_size >= lowmem) {
- pcms->above_4g_mem_size = machine->ram_size - lowmem;
- pcms->below_4g_mem_size = lowmem;
+ x86ms->above_4g_mem_size = machine->ram_size - lowmem;
+ x86ms->below_4g_mem_size = lowmem;
} else {
- pcms->above_4g_mem_size = 0;
- pcms->below_4g_mem_size = machine->ram_size;
+ x86ms->above_4g_mem_size = 0;
+ x86ms->below_4g_mem_size = machine->ram_size;
}
}
@@ -191,19 +192,19 @@ static void pc_init1(MachineState *machine,
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pcmc->pci_enabled);
- pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
+ x86ms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
GSI_NUM_PINS);
} else {
- pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
if (pcmc->pci_enabled) {
pci_bus = i440fx_init(host_type,
pci_type,
- &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+ &i440fx_state, &piix3_devfn, &isa_bus, x86ms->gsi,
system_memory, system_io, machine->ram_size,
- pcms->below_4g_mem_size,
- pcms->above_4g_mem_size,
+ x86ms->below_4g_mem_size,
+ x86ms->above_4g_mem_size,
pci_memory, ram_memory);
pcms->bus = pci_bus;
} else {
@@ -213,7 +214,7 @@ static void pc_init1(MachineState *machine,
&error_abort);
no_hpet = 1;
}
- isa_bus_irqs(isa_bus, pcms->gsi);
+ isa_bus_irqs(isa_bus, x86ms->gsi);
if (kvm_pic_in_kernel()) {
i8259 = kvm_i8259_init(isa_bus);
@@ -231,7 +232,7 @@ static void pc_init1(MachineState *machine,
ioapic_init_gsi(gsi_state, "i440fx");
}
- pc_register_ferr_irq(pcms->gsi[13]);
+ pc_register_ferr_irq(x86ms->gsi[13]);
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
@@ -241,7 +242,7 @@ static void pc_init1(MachineState *machine,
}
/* init basic PC hardware */
- pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, true,
+ pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, true,
(pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
0x4);
@@ -288,7 +289,7 @@ else {
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
/* TODO: Populate SPD eeprom data. */
pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
- pcms->gsi[9], smi_irq,
+ x86ms->gsi[9], smi_irq,
pc_machine_is_smm_enabled(pcms),
&piix4_pm);
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
@@ -304,7 +305,7 @@ else {
if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
- pcms->fw_cfg, OBJECT(pcms));
+ x86ms->fw_cfg, OBJECT(pcms));
}
}
@@ -729,7 +730,7 @@ DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4_fn,
static void pc_i440fx_1_3_machine_options(MachineClass *m)
{
- PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+ X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
static GlobalProperty compat[] = {
PC_CPU_MODEL_IDS("1.3.0")
{ "usb-tablet", "usb_version", "1" },
@@ -740,7 +741,7 @@ static void pc_i440fx_1_3_machine_options(MachineClass *m)
pc_i440fx_1_4_machine_options(m);
m->hw_version = "1.3.0";
- pcmc->compat_apic_id_mode = true;
+ x86mc->compat_apic_id_mode = true;
compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat));
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 8920bd8..374ac6c 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -116,6 +116,7 @@ static void pc_q35_init(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(machine);
Q35PCIHost *q35_host;
PCIHostState *phb;
PCIBus *host_bus;
@@ -153,27 +154,27 @@ static void pc_q35_init(MachineState *machine)
/* Handle the machine opt max-ram-below-4g. It is basically doing
* min(qemu limit, user limit).
*/
- if (!pcms->max_ram_below_4g) {
- pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
+ if (!x86ms->max_ram_below_4g) {
+ x86ms->max_ram_below_4g = 4 * GiB;
}
- if (lowmem > pcms->max_ram_below_4g) {
- lowmem = pcms->max_ram_below_4g;
+ if (lowmem > x86ms->max_ram_below_4g) {
+ lowmem = x86ms->max_ram_below_4g;
if (machine->ram_size - lowmem > lowmem &&
lowmem & (1 * GiB - 1)) {
warn_report("There is possibly poor performance as the ram size "
" (0x%" PRIx64 ") is more then twice the size of"
" max-ram-below-4g (%"PRIu64") and"
" max-ram-below-4g is not a multiple of 1G.",
- (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
+ (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
}
}
if (machine->ram_size >= lowmem) {
- pcms->above_4g_mem_size = machine->ram_size - lowmem;
- pcms->below_4g_mem_size = lowmem;
+ x86ms->above_4g_mem_size = machine->ram_size - lowmem;
+ x86ms->below_4g_mem_size = lowmem;
} else {
- pcms->above_4g_mem_size = 0;
- pcms->below_4g_mem_size = machine->ram_size;
+ x86ms->above_4g_mem_size = 0;
+ x86ms->below_4g_mem_size = machine->ram_size;
}
if (xen_enabled()) {
@@ -214,10 +215,10 @@ static void pc_q35_init(MachineState *machine)
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pcmc->pci_enabled);
- pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
+ x86ms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
GSI_NUM_PINS);
} else {
- pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
/* create pci host bus */
@@ -232,9 +233,9 @@ static void pc_q35_init(MachineState *machine)
MCH_HOST_PROP_SYSTEM_MEM, NULL);
object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
MCH_HOST_PROP_IO_MEM, NULL);
- object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
+ object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size,
PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
- object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
+ object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size,
PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
/* pci */
qdev_init_nofail(DEVICE(q35_host));
@@ -256,7 +257,7 @@ static void pc_q35_init(MachineState *machine)
ich9_lpc = ICH9_LPC_DEVICE(lpc);
lpc_dev = DEVICE(lpc);
for (i = 0; i < GSI_NUM_PINS; i++) {
- qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
+ qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
}
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
ICH9_LPC_NB_PIRQS);
@@ -280,7 +281,7 @@ static void pc_q35_init(MachineState *machine)
ioapic_init_gsi(gsi_state, "q35");
}
- pc_register_ferr_irq(pcms->gsi[13]);
+ pc_register_ferr_irq(x86ms->gsi[13]);
assert(pcms->vmport != ON_OFF_AUTO__MAX);
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
@@ -288,7 +289,7 @@ static void pc_q35_init(MachineState *machine)
}
/* init basic PC hardware */
- pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
+ pc_basic_device_init(isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
(pcms->vmport != ON_OFF_AUTO_ON), pcms->pit_enabled,
0xff0104);
@@ -331,7 +332,7 @@ static void pc_q35_init(MachineState *machine)
if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
- pcms->fw_cfg, OBJECT(pcms));
+ x86ms->fw_cfg, OBJECT(pcms));
}
}
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 71fb093..de4fed0 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -65,13 +65,14 @@ uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
unsigned int cpu_index)
{
MachineState *ms = MACHINE(pcms);
- PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
+ X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
uint32_t correct_id;
static bool warned;
- correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
+ correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,
ms->smp.threads, cpu_index);
- if (pcmc->compat_apic_id_mode) {
+ if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
"CPU topology won't match the configuration");
@@ -88,11 +89,12 @@ void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
Object *cpu = NULL;
Error *local_err = NULL;
CPUX86State *env = NULL;
+ X86MachineState *x86ms = X86_MACHINE(pcms);
cpu = object_new(MACHINE(pcms)->cpu_type);
env = &X86_CPU(cpu)->env;
- env->nr_dies = pcms->smp_dies;
+ env->nr_dies = x86ms->smp_dies;
object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
object_property_set_bool(cpu, true, "realized", &local_err);
@@ -108,6 +110,7 @@ void x86_cpus_init(PCMachineState *pcms)
MachineState *ms = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(pcms);
PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
x86_cpu_set_default_version(pcmc->default_cpu_version);
@@ -119,8 +122,8 @@ void x86_cpus_init(PCMachineState *pcms)
*
* This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
*/
- pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
- ms->smp.max_cpus - 1) + 1;
+ x86ms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
+ ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < ms->smp.cpus; i++) {
x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
@@ -140,11 +143,11 @@ x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
{
X86CPUTopoInfo topo;
- PCMachineState *pcms = PC_MACHINE(ms);
+ X86MachineState *x86ms = X86_MACHINE(ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- pcms->smp_dies, ms->smp.cores,
+ x86ms->smp_dies, ms->smp.cores,
ms->smp.threads, &topo);
return topo.pkg_id % ms->numa_state->num_nodes;
}
@@ -152,6 +155,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
{
PCMachineState *pcms = PC_MACHINE(ms);
+ X86MachineState *x86ms = X86_MACHINE(ms);
int i;
unsigned int max_cpus = ms->smp.max_cpus;
@@ -175,11 +179,11 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].arch_id =
x86_cpu_apic_id_from_index(pcms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- pcms->smp_dies, ms->smp.cores,
+ x86ms->smp_dies, ms->smp.cores,
ms->smp.threads, &topo);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
- if (pcms->smp_dies > 1) {
+ if (x86ms->smp_dies > 1) {
ms->possible_cpus->cpus[i].props.has_die_id = true;
ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
}
@@ -191,6 +195,22 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
return ms->possible_cpus;
}
+static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
+{
+ /* cpu index isn't used */
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ X86CPU *cpu = X86_CPU(cs);
+
+ if (!cpu->apic_state) {
+ cpu_interrupt(cs, CPU_INTERRUPT_NMI);
+ } else {
+ apic_deliver_nmi(cpu->apic_state);
+ }
+ }
+}
+
static long get_file_size(FILE *f)
{
long where, size;
@@ -328,6 +348,7 @@ void x86_load_linux(PCMachineState *pcms,
char *vmode;
MachineState *machine = MACHINE(pcms);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+ X86MachineState *x86ms = X86_MACHINE(pcms);
struct setup_data *setup_data;
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
@@ -400,11 +421,12 @@ void x86_load_linux(PCMachineState *pcms,
initrd_filename, gerr->message);
exit(1);
}
- pcms->initrd_mapped_file = mapped_file;
+ x86ms->initrd_mapped_file = mapped_file;
initrd_data = g_mapped_file_get_contents(mapped_file);
initrd_size = g_mapped_file_get_length(mapped_file);
- initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ initrd_max =
+ x86ms->below_4g_mem_size - pcmc->acpi_data_size - 1;
if (initrd_size >= initrd_max) {
fprintf(stderr, "qemu: initrd is too large, cannot support."
"(max: %"PRIu32", need %"PRId64")\n",
@@ -472,8 +494,8 @@ void x86_load_linux(PCMachineState *pcms,
initrd_max = 0x37ffffff;
}
- if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
- initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ if (initrd_max >= x86ms->below_4g_mem_size - pcmc->acpi_data_size) {
+ initrd_max = x86ms->below_4g_mem_size - pcmc->acpi_data_size - 1;
}
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
@@ -544,7 +566,7 @@ void x86_load_linux(PCMachineState *pcms,
initrd_filename, gerr->message);
exit(1);
}
- pcms->initrd_mapped_file = mapped_file;
+ x86ms->initrd_mapped_file = mapped_file;
initrd_data = g_mapped_file_get_contents(mapped_file);
initrd_size = g_mapped_file_get_length(mapped_file);
@@ -688,3 +710,91 @@ void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
(uint32_t)(-bios_size),
bios);
}
+
+static void x86_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ X86MachineState *x86ms = X86_MACHINE(obj);
+ uint64_t value = x86ms->max_ram_below_4g;
+
+ visit_type_size(v, name, &value, errp);
+}
+
+static void x86_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ X86MachineState *x86ms = X86_MACHINE(obj);
+ Error *error = NULL;
+ uint64_t value;
+
+ visit_type_size(v, name, &value, &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ if (value > 4 * GiB) {
+ error_setg(&error,
+ "Machine option 'max-ram-below-4g=%"PRIu64
+ "' expects size less than or equal to 4G", value);
+ error_propagate(errp, error);
+ return;
+ }
+
+ if (value < 1 * MiB) {
+ warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
+ "BIOS may not work with less than 1MiB", value);
+ }
+
+ x86ms->max_ram_below_4g = value;
+}
+
+static void x86_machine_initfn(Object *obj)
+{
+ X86MachineState *x86ms = X86_MACHINE(obj);
+
+ x86ms->max_ram_below_4g = 0; /* use default */
+ x86ms->smp_dies = 1;
+}
+
+static void x86_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
+ NMIClass *nc = NMI_CLASS(oc);
+
+ mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
+ mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
+ mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
+ x86mc->compat_apic_id_mode = false;
+ nc->nmi_monitor_handler = x86_nmi;
+
+ object_class_property_add(oc, X86_MACHINE_MAX_RAM_BELOW_4G, "size",
+ x86_machine_get_max_ram_below_4g, x86_machine_set_max_ram_below_4g,
+ NULL, NULL, &error_abort);
+
+ object_class_property_set_description(oc, X86_MACHINE_MAX_RAM_BELOW_4G,
+ "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
+}
+
+static const TypeInfo x86_machine_info = {
+ .name = TYPE_X86_MACHINE,
+ .parent = TYPE_MACHINE,
+ .abstract = true,
+ .instance_size = sizeof(X86MachineState),
+ .instance_init = x86_machine_initfn,
+ .class_size = sizeof(X86MachineClass),
+ .class_init = x86_machine_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_NMI },
+ { }
+ },
+};
+
+static void x86_machine_register_types(void)
+{
+ type_register_static(&x86_machine_info);
+}
+
+type_init(x86_machine_register_types)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb..95f23a2 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -197,11 +197,13 @@ qemu_irq *xen_interrupt_controller_init(void)
static void xen_ram_init(PCMachineState *pcms,
ram_addr_t ram_size, MemoryRegion **ram_memory_p)
{
+ X86MachineState *x86ms = X86_MACHINE(pcms);
MemoryRegion *sysmem = get_system_memory();
ram_addr_t block_len;
- uint64_t user_lowmem = object_property_get_uint(qdev_get_machine(),
- PC_MACHINE_MAX_RAM_BELOW_4G,
- &error_abort);
+ uint64_t user_lowmem =
+ object_property_get_uint(qdev_get_machine(),
+ X86_MACHINE_MAX_RAM_BELOW_4G,
+ &error_abort);
/* Handle the machine opt max-ram-below-4g. It is basically doing
* min(xen limit, user limit).
@@ -214,20 +216,20 @@ static void xen_ram_init(PCMachineState *pcms,
}
if (ram_size >= user_lowmem) {
- pcms->above_4g_mem_size = ram_size - user_lowmem;
- pcms->below_4g_mem_size = user_lowmem;
+ x86ms->above_4g_mem_size = ram_size - user_lowmem;
+ x86ms->below_4g_mem_size = user_lowmem;
} else {
- pcms->above_4g_mem_size = 0;
- pcms->below_4g_mem_size = ram_size;
+ x86ms->above_4g_mem_size = 0;
+ x86ms->below_4g_mem_size = ram_size;
}
- if (!pcms->above_4g_mem_size) {
+ if (!x86ms->above_4g_mem_size) {
block_len = ram_size;
} else {
/*
* Xen does not allocate the memory continuously, it keeps a
* hole of the size computed above or passed in.
*/
- block_len = (1ULL << 32) + pcms->above_4g_mem_size;
+ block_len = (1ULL << 32) + x86ms->above_4g_mem_size;
}
memory_region_init_ram(&ram_memory, NULL, "xen.ram", block_len,
&error_fatal);
@@ -244,12 +246,12 @@ static void xen_ram_init(PCMachineState *pcms,
*/
memory_region_init_alias(&ram_lo, NULL, "xen.ram.lo",
&ram_memory, 0xc0000,
- pcms->below_4g_mem_size - 0xc0000);
+ x86ms->below_4g_mem_size - 0xc0000);
memory_region_add_subregion(sysmem, 0xc0000, &ram_lo);
- if (pcms->above_4g_mem_size > 0) {
+ if (x86ms->above_4g_mem_size > 0) {
memory_region_init_alias(&ram_hi, NULL, "xen.ram.hi",
&ram_memory, 0x100000000ULL,
- pcms->above_4g_mem_size);
+ x86ms->above_4g_mem_size);
memory_region_add_subregion(sysmem, 0x100000000ULL, &ram_hi);
}
}
@@ -265,7 +267,7 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, MemoryRegion *mr,
/* RAM already populated in Xen */
fprintf(stderr, "%s: do not alloc "RAM_ADDR_FMT
" bytes of ram at "RAM_ADDR_FMT" when runstate is INMIGRATE\n",
- __func__, size, ram_addr);
+ __func__, size, ram_addr);
return;
}
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 1ede055..ead14e1 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -89,7 +89,7 @@ static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
static void ioapic_service(IOAPICCommonState *s)
{
- AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
+ AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as;
struct ioapic_entry_info info;
uint8_t i;
uint32_t mask;
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index f135ae8..13c4eac 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -8,6 +8,7 @@
#include "hw/block/flash.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"
+#include "hw/i386/x86.h"
#include "qemu/range.h"
#include "qemu/bitmap.h"
@@ -27,7 +28,7 @@
*/
struct PCMachineState {
/*< private >*/
- MachineState parent_obj;
+ X86MachineState parent_obj;
/* <public> */
@@ -36,16 +37,11 @@ struct PCMachineState {
/* Pointers to devices and objects: */
HotplugHandler *acpi_dev;
- ISADevice *rtc;
PCIBus *bus;
I2CBus *smbus;
- FWCfgState *fw_cfg;
- qemu_irq *gsi;
PFlashCFI01 *flash[2];
- GMappedFile *initrd_mapped_file;
/* Configuration options: */
- uint64_t max_ram_below_4g;
OnOffAuto vmport;
OnOffAuto smm;
@@ -54,30 +50,16 @@ struct PCMachineState {
bool sata_enabled;
bool pit_enabled;
- /* RAM information (sizes, addresses, configuration): */
- ram_addr_t below_4g_mem_size, above_4g_mem_size;
-
- /* CPU and apic information: */
- bool apic_xrupt_override;
- unsigned apic_id_limit;
- uint16_t boot_cpus;
- unsigned smp_dies;
-
/* NUMA information: */
uint64_t numa_nodes;
uint64_t *node_mem;
- /* Address space used by IOAPIC device. All IOAPIC interrupts
- * will be translated to MSI messages in the address space. */
- AddressSpace *ioapic_as;
-
/* ACPI Memory hotplug IO base address */
hwaddr memhp_io_base;
};
#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
-#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
#define PC_MACHINE_VMPORT "vmport"
#define PC_MACHINE_SMM "smm"
#define PC_MACHINE_SMBUS "smbus"
@@ -102,7 +84,7 @@ struct PCMachineState {
*/
typedef struct PCMachineClass {
/*< private >*/
- MachineClass parent_class;
+ X86MachineClass parent_class;
/*< public >*/
@@ -144,9 +126,6 @@ typedef struct PCMachineClass {
/* use PVH to load kernels that support this feature */
bool pvh_enabled;
-
- /* Enables contiguous-apic-ID mode */
- bool compat_apic_id_mode;
} PCMachineClass;
#define TYPE_PC_MACHINE "generic-pc-machine"
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 71e2b69..d15713e 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -17,7 +17,63 @@
#ifndef HW_I386_X86_H
#define HW_I386_X86_H
+#include "qemu-common.h"
+#include "exec/hwaddr.h"
+#include "qemu/notify.h"
+
#include "hw/boards.h"
+#include "hw/nmi.h"
+
+typedef struct {
+ /*< private >*/
+ MachineClass parent;
+
+ /*< public >*/
+
+ /* Enables contiguous-apic-ID mode */
+ bool compat_apic_id_mode;
+} X86MachineClass;
+
+typedef struct {
+ /*< private >*/
+ MachineState parent;
+
+ /*< public >*/
+
+ /* Pointers to devices and objects: */
+ ISADevice *rtc;
+ FWCfgState *fw_cfg;
+ qemu_irq *gsi;
+ GMappedFile *initrd_mapped_file;
+
+ /* Configuration options: */
+ uint64_t max_ram_below_4g;
+
+ /* RAM information (sizes, addresses, configuration): */
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+
+ /* CPU and apic information: */
+ bool apic_xrupt_override;
+ unsigned apic_id_limit;
+ uint16_t boot_cpus;
+ unsigned smp_dies;
+
+ /*
+ * Address space used by IOAPIC device. All IOAPIC interrupts
+ * will be translated to MSI messages in the address space.
+ */
+ AddressSpace *ioapic_as;
+} X86MachineState;
+
+#define X86_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
+
+#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
+#define X86_MACHINE(obj) \
+ OBJECT_CHECK(X86MachineState, (obj), TYPE_X86_MACHINE)
+#define X86_MACHINE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(X86MachineClass, obj, TYPE_X86_MACHINE)
+#define X86_MACHINE_CLASS(class) \
+ OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
unsigned int cpu_index);
@@ -30,6 +86,6 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
-void x86_load_linux(PCMachineState *x86ms, FWCfgState *fw_cfg);
+void x86_load_linux(PCMachineState *pcms, FWCfgState *fw_cfg);
#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 15/39] hw/i386: make x86.c independent from PCMachineState
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (13 preceding siblings ...)
2019-10-24 14:03 ` [PULL 14/39] hw/i386: split PCMachineState deriving X86MachineState from it Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 16/39] fw_cfg: add "modify" functions for all types Paolo Bonzini
` (25 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
As a last step into splitting PCMachineState and deriving
X86MachineState from it, make the functions previously extracted from
pc.c to x86.c independent from PCMachineState, using X86MachineState
instead.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/pc.c | 14 +++++++++-----
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
hw/i386/x86.c | 53 +++++++++++++++++++++++----------------------------
include/hw/i386/x86.h | 13 +++++++++----
5 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e6ad1f1..a8888dd 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -983,8 +983,8 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
{
- PCMachineState *pcms = PC_MACHINE(ms);
- int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
+ X86MachineState *x86ms = X86_MACHINE(ms);
+ int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
Error *local_err = NULL;
if (id < 0) {
@@ -999,7 +999,8 @@ void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
return;
}
- x86_cpu_new(PC_MACHINE(ms), apic_id, &local_err);
+
+ x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -1100,6 +1101,7 @@ void xen_load_linux(PCMachineState *pcms)
{
int i;
FWCfgState *fw_cfg;
+ PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
assert(MACHINE(pcms)->kernel_filename != NULL);
@@ -1108,7 +1110,8 @@ void xen_load_linux(PCMachineState *pcms)
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
rom_set_fw(fw_cfg);
- x86_load_linux(pcms, fw_cfg);
+ x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
+ pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
for (i = 0; i < nb_option_roms; i++) {
assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
!strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
@@ -1244,7 +1247,8 @@ void pc_memory_init(PCMachineState *pcms,
}
if (linux_boot) {
- x86_load_linux(pcms, fw_cfg);
+ x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
+ pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
}
for (i = 0; i < nb_option_roms; i++) {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0afa8fe..a86317c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -154,7 +154,7 @@ static void pc_init1(MachineState *machine,
}
}
- x86_cpus_init(pcms);
+ x86_cpus_init(x86ms, pcmc->default_cpu_version);
if (kvm_enabled() && pcmc->kvmclock_enabled) {
kvmclock_create();
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 374ac6c..75c8caf 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -181,7 +181,7 @@ static void pc_q35_init(MachineState *machine)
xen_hvm_init(pcms, &ram_memory);
}
- x86_cpus_init(pcms);
+ x86_cpus_init(x86ms, pcmc->default_cpu_version);
kvmclock_create();
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index de4fed0..fd84b23 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -36,7 +36,6 @@
#include "sysemu/sysemu.h"
#include "hw/i386/x86.h"
-#include "hw/i386/pc.h"
#include "target/i386/cpu.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
@@ -61,11 +60,10 @@ static size_t pvh_start_addr;
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
* all CPUs up to max_cpus.
*/
-uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
+uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
unsigned int cpu_index)
{
- MachineState *ms = MACHINE(pcms);
- X86MachineState *x86ms = X86_MACHINE(pcms);
+ MachineState *ms = MACHINE(x86ms);
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
uint32_t correct_id;
static bool warned;
@@ -84,14 +82,14 @@ uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
}
}
-void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
+
+void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp)
{
Object *cpu = NULL;
Error *local_err = NULL;
CPUX86State *env = NULL;
- X86MachineState *x86ms = X86_MACHINE(pcms);
- cpu = object_new(MACHINE(pcms)->cpu_type);
+ cpu = object_new(MACHINE(x86ms)->cpu_type);
env = &X86_CPU(cpu)->env;
env->nr_dies = x86ms->smp_dies;
@@ -103,30 +101,28 @@ void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp)
error_propagate(errp, local_err);
}
-void x86_cpus_init(PCMachineState *pcms)
+void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version)
{
int i;
const CPUArchIdList *possible_cpus;
- MachineState *ms = MACHINE(pcms);
- MachineClass *mc = MACHINE_GET_CLASS(pcms);
- PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
- X86MachineState *x86ms = X86_MACHINE(pcms);
+ MachineState *ms = MACHINE(x86ms);
+ MachineClass *mc = MACHINE_GET_CLASS(x86ms);
- x86_cpu_set_default_version(pcmc->default_cpu_version);
+ x86_cpu_set_default_version(default_cpu_version);
/*
* Calculates the limit to CPU APIC ID values
*
* Limit for the APIC ID value, so that all
- * CPU APIC IDs are < pcms->apic_id_limit.
+ * CPU APIC IDs are < x86ms->apic_id_limit.
*
* This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
*/
- x86ms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
+ x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < ms->smp.cpus; i++) {
- x86_cpu_new(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
+ x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
@@ -154,7 +150,6 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx)
const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
{
- PCMachineState *pcms = PC_MACHINE(ms);
X86MachineState *x86ms = X86_MACHINE(ms);
int i;
unsigned int max_cpus = ms->smp.max_cpus;
@@ -177,7 +172,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id =
- x86_cpu_apic_id_from_index(pcms, i);
+ x86_cpu_apic_id_from_index(x86ms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
x86ms->smp_dies, ms->smp.cores,
ms->smp.threads, &topo);
@@ -335,8 +330,11 @@ static bool load_elfboot(const char *kernel_filename,
return true;
}
-void x86_load_linux(PCMachineState *pcms,
- FWCfgState *fw_cfg)
+void x86_load_linux(X86MachineState *x86ms,
+ FWCfgState *fw_cfg,
+ int acpi_data_size,
+ bool pvh_enabled,
+ bool linuxboot_dma_enabled)
{
uint16_t protocol;
int setup_size, kernel_size, cmdline_size;
@@ -346,9 +344,7 @@ void x86_load_linux(PCMachineState *pcms,
hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f;
char *vmode;
- MachineState *machine = MACHINE(pcms);
- PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
- X86MachineState *x86ms = X86_MACHINE(pcms);
+ MachineState *machine = MACHINE(x86ms);
struct setup_data *setup_data;
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
@@ -395,7 +391,7 @@ void x86_load_linux(PCMachineState *pcms,
* saving the PVH entry point used by the x86/HVM direct boot ABI.
* If load_elfboot() is successful, populate the fw_cfg info.
*/
- if (pcmc->pvh_enabled &&
+ if (pvh_enabled &&
load_elfboot(kernel_filename, kernel_size,
header, pvh_start_addr, fw_cfg)) {
fclose(f);
@@ -425,8 +421,7 @@ void x86_load_linux(PCMachineState *pcms,
initrd_data = g_mapped_file_get_contents(mapped_file);
initrd_size = g_mapped_file_get_length(mapped_file);
- initrd_max =
- x86ms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
if (initrd_size >= initrd_max) {
fprintf(stderr, "qemu: initrd is too large, cannot support."
"(max: %"PRIu32", need %"PRId64")\n",
@@ -494,8 +489,8 @@ void x86_load_linux(PCMachineState *pcms,
initrd_max = 0x37ffffff;
}
- if (initrd_max >= x86ms->below_4g_mem_size - pcmc->acpi_data_size) {
- initrd_max = x86ms->below_4g_mem_size - pcmc->acpi_data_size - 1;
+ if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) {
+ initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1;
}
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
@@ -652,7 +647,7 @@ void x86_load_linux(PCMachineState *pcms,
option_rom[nb_option_roms].bootindex = 0;
option_rom[nb_option_roms].name = "linuxboot.bin";
- if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
+ if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
option_rom[nb_option_roms].name = "linuxboot_dma.bin";
}
nb_option_roms++;
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index d15713e..82d09fd 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -75,10 +75,11 @@ typedef struct {
#define X86_MACHINE_CLASS(class) \
OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
-uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
+uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
unsigned int cpu_index);
-void x86_cpu_new(PCMachineState *pcms, int64_t apic_id, Error **errp);
-void x86_cpus_init(PCMachineState *pcms);
+
+void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
+void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
unsigned cpu_index);
int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
@@ -86,6 +87,10 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
-void x86_load_linux(PCMachineState *pcms, FWCfgState *fw_cfg);
+void x86_load_linux(X86MachineState *x86ms,
+ FWCfgState *fw_cfg,
+ int acpi_data_size,
+ bool pvh_enabled,
+ bool linuxboot_dma_enabled);
#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 16/39] fw_cfg: add "modify" functions for all types
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (14 preceding siblings ...)
2019-10-24 14:03 ` [PULL 15/39] hw/i386: make x86.c independent from PCMachineState Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 17/39] hw/intc/apic: reject pic ints if isa_pic == NULL Paolo Bonzini
` (24 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
This allows to alter the contents of an already added item.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
hw/nvram/fw_cfg.c | 29 +++++++++++++++++++++++++++++
include/hw/nvram/fw_cfg.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 7dc3ac3..aef1727 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -690,6 +690,15 @@ void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
}
+void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value)
+{
+ size_t sz = strlen(value) + 1;
+ char *old;
+
+ old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz);
+ g_free(old);
+}
+
void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
{
uint16_t *copy;
@@ -720,6 +729,16 @@ void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
fw_cfg_add_bytes(s, key, copy, sizeof(value));
}
+void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value)
+{
+ uint32_t *copy, *old;
+
+ copy = g_malloc(sizeof(value));
+ *copy = cpu_to_le32(value);
+ old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
+ g_free(old);
+}
+
void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
{
uint64_t *copy;
@@ -730,6 +749,16 @@ void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
fw_cfg_add_bytes(s, key, copy, sizeof(value));
}
+void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
+{
+ uint64_t *copy, *old;
+
+ copy = g_malloc(sizeof(value));
+ *copy = cpu_to_le64(value);
+ old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
+ g_free(old);
+}
+
void fw_cfg_set_order_override(FWCfgState *s, int order)
{
assert(s->fw_cfg_order_override == 0);
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 80e435d..b5291ee 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -99,6 +99,20 @@ void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len);
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value);
/**
+ * fw_cfg_modify_string:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: NUL-terminated ascii string
+ *
+ * Replace the fw_cfg item available by selecting the given key. The new
+ * data will consist of a dynamically allocated copy of the provided string,
+ * including its NUL terminator. The data being replaced, assumed to have
+ * been dynamically allocated during an earlier call to either
+ * fw_cfg_add_string() or fw_cfg_modify_string(), is freed before returning.
+ */
+void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value);
+
+/**
* fw_cfg_add_i16:
* @s: fw_cfg device being modified
* @key: selector key value for new fw_cfg item
@@ -137,6 +151,20 @@ void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value);
void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value);
/**
+ * fw_cfg_modify_i32:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 32-bit integer
+ *
+ * Replace the fw_cfg item available by selecting the given key. The new
+ * data will consist of a dynamically allocated copy of the given 32-bit
+ * value, converted to little-endian representation. The data being replaced,
+ * assumed to have been dynamically allocated during an earlier call to
+ * either fw_cfg_add_i32() or fw_cfg_modify_i32(), is freed before returning.
+ */
+void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value);
+
+/**
* fw_cfg_add_i64:
* @s: fw_cfg device being modified
* @key: selector key value for new fw_cfg item
@@ -149,6 +177,20 @@ void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value);
void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value);
/**
+ * fw_cfg_modify_i64:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 64-bit integer
+ *
+ * Replace the fw_cfg item available by selecting the given key. The new
+ * data will consist of a dynamically allocated copy of the given 64-bit
+ * value, converted to little-endian representation. The data being replaced,
+ * assumed to have been dynamically allocated during an earlier call to
+ * either fw_cfg_add_i64() or fw_cfg_modify_i64(), is freed before returning.
+ */
+void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value);
+
+/**
* fw_cfg_add_file:
* @s: fw_cfg device being modified
* @filename: name of new fw_cfg file item
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 17/39] hw/intc/apic: reject pic ints if isa_pic == NULL
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (15 preceding siblings ...)
2019-10-24 14:03 ` [PULL 16/39] fw_cfg: add "modify" functions for all types Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 18/39] roms: add microvm-bios (qboot) as binary and git submodule Paolo Bonzini
` (23 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
In apic_accept_pic_intr(), reject PIC interruptions if a i8259 PIC has
not been instantiated (isa_pic == NULL).
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/intc/apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index bce8991..2a74f7b 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -610,7 +610,7 @@ int apic_accept_pic_intr(DeviceState *dev)
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
(lvt0 & APIC_LVT_MASKED) == 0)
- return 1;
+ return isa_pic != NULL;
return 0;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 18/39] roms: add microvm-bios (qboot) as binary and git submodule
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (16 preceding siblings ...)
2019-10-24 14:03 ` [PULL 17/39] hw/intc/apic: reject pic ints if isa_pic == NULL Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 19/39] docs/microvm.rst: document the new microvm machine type Paolo Bonzini
` (22 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
qboot is a minimalist x86 firmware for booting Linux kernels. It does
the mininum amount of work required for the task, and it's able to
boot both PVH images and bzImages without relying on option roms.
This characteristics make it an ideal companion for the microvm
machine type.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
.gitmodules | 3 +++
pc-bios/bios-microvm.bin | Bin 0 -> 65536 bytes
roms/Makefile | 6 ++++++
roms/qboot | 1 +
4 files changed, 10 insertions(+)
create mode 100644 pc-bios/bios-microvm.bin
create mode 160000 roms/qboot
diff --git a/.gitmodules b/.gitmodules
index c5c4741..19792c9 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -58,3 +58,6 @@
[submodule "roms/opensbi"]
path = roms/opensbi
url = https://git.qemu.org/git/opensbi.git
+[submodule "roms/qboot"]
+ path = roms/qboot
+ url = https://github.com/bonzini/qboot
diff --git a/pc-bios/bios-microvm.bin b/pc-bios/bios-microvm.bin
new file mode 100644
index 0000000000000000000000000000000000000000..45eabc516692e2d134bbb630d133c7c2dcc9a9b6
GIT binary patch
literal 65536
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diff --git a/roms/Makefile b/roms/Makefile
index da4efa4..c150170 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -67,6 +67,7 @@ default help:
@echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine"
@echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine"
@echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine"
+ @echo " bios-microvm -- update bios-microvm.bin (qboot)"
@echo " clean -- delete the files generated by the previous" \
"build targets"
@@ -186,6 +187,10 @@ opensbi64-sifive_u:
PLATFORM="sifive/fu540"
cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
+bios-microvm:
+ $(MAKE) -C qboot
+ cp qboot/bios.bin ../pc-bios/bios-microvm.bin
+
clean:
rm -rf seabios/.config seabios/out seabios/builds
$(MAKE) -C sgabios clean
@@ -198,3 +203,4 @@ clean:
$(MAKE) -C skiboot clean
$(MAKE) -f Makefile.edk2 clean
$(MAKE) -C opensbi clean
+ $(MAKE) -C qboot clean
diff --git a/roms/qboot b/roms/qboot
new file mode 160000
index 0000000..cb1c49e
--- /dev/null
+++ b/roms/qboot
@@ -0,0 +1 @@
+Subproject commit cb1c49e0cfac99b9961d136ac0194da62c28cf64
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 19/39] docs/microvm.rst: document the new microvm machine type
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (17 preceding siblings ...)
2019-10-24 14:03 ` [PULL 18/39] roms: add microvm-bios (qboot) as binary and git submodule Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 20/39] hw/i386: Introduce the " Paolo Bonzini
` (21 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Document the new microvm machine type.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
docs/microvm.rst | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 docs/microvm.rst
diff --git a/docs/microvm.rst b/docs/microvm.rst
new file mode 100644
index 0000000..aae811a
--- /dev/null
+++ b/docs/microvm.rst
@@ -0,0 +1,108 @@
+====================
+microvm Machine Type
+====================
+
+``microvm`` is a machine type inspired by ``Firecracker`` and
+constructed after its machine model.
+
+It's a minimalist machine type without ``PCI`` nor ``ACPI`` support,
+designed for short-lived guests. microvm also establishes a baseline
+for benchmarking and optimizing both QEMU and guest operating systems,
+since it is optimized for both boot time and footprint.
+
+
+Supported devices
+-----------------
+
+The microvm machine type supports the following devices:
+
+- ISA bus
+- i8259 PIC (optional)
+- i8254 PIT (optional)
+- MC146818 RTC (optional)
+- One ISA serial port (optional)
+- LAPIC
+- IOAPIC (with kernel-irqchip=split by default)
+- kvmclock (if using KVM)
+- fw_cfg
+- Up to eight virtio-mmio devices (configured by the user)
+
+
+Limitations
+-----------
+
+Currently, microvm does *not* support the following features:
+
+ - PCI-only devices.
+ - Hotplug of any kind.
+ - Live migration across QEMU versions.
+
+
+Using the microvm machine type
+------------------------------
+
+Machine-specific options
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+It supports the following machine-specific options:
+
+- microvm.x-option-roms=bool (Set off to disable loading option ROMs)
+- microvm.pit=OnOffAuto (Enable i8254 PIT)
+- microvm.isa-serial=bool (Set off to disable the instantiation an ISA serial port)
+- microvm.pic=OnOffAuto (Enable i8259 PIC)
+- microvm.rtc=OnOffAuto (Enable MC146818 RTC)
+- microvm.auto-kernel-cmdline=bool (Set off to disable adding virtio-mmio devices to the kernel cmdline)
+
+
+Boot options
+~~~~~~~~~~~~
+
+By default, microvm uses ``qboot`` as its BIOS, to obtain better boot
+times, but it's also compatible with ``SeaBIOS``.
+
+As no current FW is able to boot from a block device using
+``virtio-mmio`` as its transport, a microvm-based VM needs to be run
+using a host-side kernel and, optionally, an initrd image.
+
+
+Running a microvm-based VM
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+By default, microvm aims for maximum compatibility, enabling both
+legacy and non-legacy devices. In this example, a VM is created
+without passing any additional machine-specific option, using the
+legacy ``ISA serial`` device as console::
+
+ $ qemu-system-x86_64 -M microvm \
+ -enable-kvm -cpu host -m 512m -smp 2 \
+ -kernel vmlinux -append "earlyprintk=ttyS0 console=ttyS0 root=/dev/vda" \
+ -nodefaults -no-user-config -nographic \
+ -serial stdio \
+ -drive id=test,file=test.img,format=raw,if=none \
+ -device virtio-blk-device,drive=test \
+ -netdev tap,id=tap0,script=no,downscript=no \
+ -device virtio-net-device,netdev=tap0
+
+While the example above works, you might be interested in reducing the
+footprint further by disabling some legacy devices. If you're using
+``KVM``, you can disable the ``RTC``, making the Guest rely on
+``kvmclock`` exclusively. Additionally, if your host's CPUs have the
+``TSC_DEADLINE`` feature, you can also disable both the i8259 PIC and
+the i8254 PIT (make sure you're also emulating a CPU with such feature
+in the guest).
+
+This is an example of a VM with all optional legacy features
+disabled::
+
+ $ qemu-system-x86_64 \
+ -M microvm,x-option-roms=off,pit=off,pic=off,isa-serial=off,rtc=off \
+ -enable-kvm -cpu host -m 512m -smp 2 \
+ -kernel vmlinux -append "console=hvc0 root=/dev/vda" \
+ -nodefaults -no-user-config -nographic \
+ -chardev stdio,id=virtiocon0 \
+ -device virtio-serial-device \
+ -device virtconsole,chardev=virtiocon0 \
+ -drive id=test,file=test.img,format=raw,if=none \
+ -device virtio-blk-device,drive=test \
+ -netdev tap,id=tap0,script=no,downscript=no \
+ -device virtio-net-device,netdev=tap0
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 20/39] hw/i386: Introduce the microvm machine type
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (18 preceding siblings ...)
2019-10-24 14:03 ` [PULL 19/39] docs/microvm.rst: document the new microvm machine type Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-11-12 10:18 ` Peter Maydell
2019-10-24 14:03 ` [PULL 21/39] MAINTAINERS: add microvm related files Paolo Bonzini
` (20 subsequent siblings)
40 siblings, 1 reply; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
microvm is a machine type inspired by Firecracker and constructed
after its machine model.
It's a minimalist machine type without PCI nor ACPI support, designed
for short-lived guests. microvm also establishes a baseline for
benchmarking and optimizing both QEMU and guest operating systems,
since it is optimized for both boot time and footprint.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
default-configs/i386-softmmu.mak | 1 +
hw/i386/Kconfig | 10 +
hw/i386/Makefile.objs | 1 +
hw/i386/microvm.c | 572 +++++++++++++++++++++++++++++++++++++++
include/hw/i386/microvm.h | 71 +++++
5 files changed, 655 insertions(+)
create mode 100644 hw/i386/microvm.c
create mode 100644 include/hw/i386/microvm.h
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 4229900..4cc64da 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -28,3 +28,4 @@
CONFIG_ISAPC=y
CONFIG_I440FX=y
CONFIG_Q35=y
+CONFIG_MICROVM=y
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d49..b25bb6d 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -92,6 +92,16 @@ config Q35
select SMBIOS
select FW_CFG_DMA
+config MICROVM
+ bool
+ imply SERIAL_ISA
+ select ISA_BUS
+ select APIC
+ select IOAPIC
+ select I8259
+ select MC146818RTC
+ select VIRTIO_MMIO
+
config VTD
bool
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 7ed80a4..0d195b5 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -4,6 +4,7 @@ obj-y += x86.o
obj-y += pc.o
obj-$(CONFIG_I440FX) += pc_piix.o
obj-$(CONFIG_Q35) += pc_q35.o
+obj-$(CONFIG_MICROVM) += microvm.o
obj-y += fw_cfg.o pc_sysfw.o
obj-y += x86-iommu.o
obj-$(CONFIG_VTD) += intel_iommu.o
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
new file mode 100644
index 0000000..20d2189
--- /dev/null
+++ b/hw/i386/microvm.c
@@ -0,0 +1,572 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ * Copyright (c) 2019 Red Hat, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/cutils.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "qapi/qapi-visit-common.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/cpus.h"
+#include "sysemu/numa.h"
+#include "sysemu/reset.h"
+
+#include "hw/loader.h"
+#include "hw/irq.h"
+#include "hw/kvm/clock.h"
+#include "hw/i386/microvm.h"
+#include "hw/i386/x86.h"
+#include "hw/i386/pc.h"
+#include "target/i386/cpu.h"
+#include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
+#include "hw/char/serial.h"
+#include "hw/i386/topology.h"
+#include "hw/i386/e820_memory_layout.h"
+#include "hw/i386/fw_cfg.h"
+#include "hw/virtio/virtio-mmio.h"
+
+#include "cpu.h"
+#include "elf.h"
+#include "kvm_i386.h"
+#include "hw/xen/start_info.h"
+
+#define MICROVM_BIOS_FILENAME "bios-microvm.bin"
+
+static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
+{
+ X86MachineState *x86ms = X86_MACHINE(mms);
+ int val;
+
+ val = MIN(x86ms->below_4g_mem_size / KiB, 640);
+ rtc_set_memory(s, 0x15, val);
+ rtc_set_memory(s, 0x16, val >> 8);
+ /* extended memory (next 64MiB) */
+ if (x86ms->below_4g_mem_size > 1 * MiB) {
+ val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
+ } else {
+ val = 0;
+ }
+ if (val > 65535) {
+ val = 65535;
+ }
+ rtc_set_memory(s, 0x17, val);
+ rtc_set_memory(s, 0x18, val >> 8);
+ rtc_set_memory(s, 0x30, val);
+ rtc_set_memory(s, 0x31, val >> 8);
+ /* memory between 16MiB and 4GiB */
+ if (x86ms->below_4g_mem_size > 16 * MiB) {
+ val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
+ } else {
+ val = 0;
+ }
+ if (val > 65535) {
+ val = 65535;
+ }
+ rtc_set_memory(s, 0x34, val);
+ rtc_set_memory(s, 0x35, val >> 8);
+ /* memory above 4GiB */
+ val = x86ms->above_4g_mem_size / 65536;
+ rtc_set_memory(s, 0x5b, val);
+ rtc_set_memory(s, 0x5c, val >> 8);
+ rtc_set_memory(s, 0x5d, val >> 16);
+}
+
+static void microvm_gsi_handler(void *opaque, int n, int level)
+{
+ GSIState *s = opaque;
+
+ qemu_set_irq(s->ioapic_irq[n], level);
+}
+
+static void microvm_devices_init(MicrovmMachineState *mms)
+{
+ X86MachineState *x86ms = X86_MACHINE(mms);
+ ISABus *isa_bus;
+ ISADevice *rtc_state;
+ GSIState *gsi_state;
+ int i;
+
+ /* Core components */
+
+ gsi_state = g_malloc0(sizeof(*gsi_state));
+ if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
+ x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ } else {
+ x86ms->gsi = qemu_allocate_irqs(microvm_gsi_handler,
+ gsi_state, GSI_NUM_PINS);
+ }
+
+ isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
+ &error_abort);
+ isa_bus_irqs(isa_bus, x86ms->gsi);
+
+ ioapic_init_gsi(gsi_state, "machine");
+
+ kvmclock_create();
+
+ for (i = 0; i < VIRTIO_NUM_TRANSPORTS; i++) {
+ sysbus_create_simple("virtio-mmio",
+ VIRTIO_MMIO_BASE + i * 512,
+ x86ms->gsi[VIRTIO_IRQ_BASE + i]);
+ }
+
+ /* Optional and legacy devices */
+
+ if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
+ qemu_irq *i8259;
+
+ i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ gsi_state->i8259_irq[i] = i8259[i];
+ }
+ g_free(i8259);
+ }
+
+ if (mms->pit == ON_OFF_AUTO_ON || mms->pit == ON_OFF_AUTO_AUTO) {
+ if (kvm_pit_in_kernel()) {
+ kvm_pit_init(isa_bus, 0x40);
+ } else {
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+ }
+ }
+
+ if (mms->rtc == ON_OFF_AUTO_ON ||
+ (mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
+ rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
+ microvm_set_rtc(mms, rtc_state);
+ }
+
+ if (mms->isa_serial) {
+ serial_hds_isa_init(isa_bus, 0, 1);
+ }
+
+ if (bios_name == NULL) {
+ bios_name = MICROVM_BIOS_FILENAME;
+ }
+ x86_bios_rom_init(get_system_memory(), true);
+}
+
+static void microvm_memory_init(MicrovmMachineState *mms)
+{
+ MachineState *machine = MACHINE(mms);
+ X86MachineState *x86ms = X86_MACHINE(mms);
+ MemoryRegion *ram, *ram_below_4g, *ram_above_4g;
+ MemoryRegion *system_memory = get_system_memory();
+ FWCfgState *fw_cfg;
+ ram_addr_t lowmem;
+ int i;
+
+ /*
+ * Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
+ * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
+ * also known as MMCFG).
+ * If it doesn't, we need to split it in chunks below and above 4G.
+ * In any case, try to make sure that guest addresses aligned at
+ * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
+ */
+ if (machine->ram_size >= 0xb0000000) {
+ lowmem = 0x80000000;
+ } else {
+ lowmem = 0xb0000000;
+ }
+
+ /*
+ * Handle the machine opt max-ram-below-4g. It is basically doing
+ * min(qemu limit, user limit).
+ */
+ if (!x86ms->max_ram_below_4g) {
+ x86ms->max_ram_below_4g = 4 * GiB;
+ }
+ if (lowmem > x86ms->max_ram_below_4g) {
+ lowmem = x86ms->max_ram_below_4g;
+ if (machine->ram_size - lowmem > lowmem &&
+ lowmem & (1 * GiB - 1)) {
+ warn_report("There is possibly poor performance as the ram size "
+ " (0x%" PRIx64 ") is more then twice the size of"
+ " max-ram-below-4g (%"PRIu64") and"
+ " max-ram-below-4g is not a multiple of 1G.",
+ (uint64_t)machine->ram_size, x86ms->max_ram_below_4g);
+ }
+ }
+
+ if (machine->ram_size > lowmem) {
+ x86ms->above_4g_mem_size = machine->ram_size - lowmem;
+ x86ms->below_4g_mem_size = lowmem;
+ } else {
+ x86ms->above_4g_mem_size = 0;
+ x86ms->below_4g_mem_size = machine->ram_size;
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_allocate_system_memory(ram, NULL, "microvm.ram",
+ machine->ram_size);
+
+ ram_below_4g = g_malloc(sizeof(*ram_below_4g));
+ memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
+ 0, x86ms->below_4g_mem_size);
+ memory_region_add_subregion(system_memory, 0, ram_below_4g);
+
+ e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
+
+ if (x86ms->above_4g_mem_size > 0) {
+ ram_above_4g = g_malloc(sizeof(*ram_above_4g));
+ memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
+ x86ms->below_4g_mem_size,
+ x86ms->above_4g_mem_size);
+ memory_region_add_subregion(system_memory, 0x100000000ULL,
+ ram_above_4g);
+ e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
+ }
+
+ fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
+ &address_space_memory);
+
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
+ &e820_reserve, sizeof(e820_reserve));
+ fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
+ sizeof(struct e820_entry) * e820_get_num_entries());
+
+ rom_set_fw(fw_cfg);
+
+ if (machine->kernel_filename != NULL) {
+ x86_load_linux(x86ms, fw_cfg, 0, true, true);
+ }
+
+ if (mms->option_roms) {
+ for (i = 0; i < nb_option_roms; i++) {
+ rom_add_option(option_rom[i].name, option_rom[i].bootindex);
+ }
+ }
+
+ x86ms->fw_cfg = fw_cfg;
+ x86ms->ioapic_as = &address_space_memory;
+}
+
+static gchar *microvm_get_mmio_cmdline(gchar *name)
+{
+ gchar *cmdline;
+ gchar *separator;
+ long int index;
+ int ret;
+
+ separator = g_strrstr(name, ".");
+ if (!separator) {
+ return NULL;
+ }
+
+ if (qemu_strtol(separator + 1, NULL, 10, &index) != 0) {
+ return NULL;
+ }
+
+ cmdline = g_malloc0(VIRTIO_CMDLINE_MAXLEN);
+ ret = g_snprintf(cmdline, VIRTIO_CMDLINE_MAXLEN,
+ " virtio_mmio.device=512@0x%lx:%ld",
+ VIRTIO_MMIO_BASE + index * 512,
+ VIRTIO_IRQ_BASE + index);
+ if (ret < 0 || ret >= VIRTIO_CMDLINE_MAXLEN) {
+ g_free(cmdline);
+ return NULL;
+ }
+
+ return cmdline;
+}
+
+static void microvm_fix_kernel_cmdline(MachineState *machine)
+{
+ X86MachineState *x86ms = X86_MACHINE(machine);
+ BusState *bus;
+ BusChild *kid;
+ char *cmdline;
+
+ /*
+ * Find MMIO transports with attached devices, and add them to the kernel
+ * command line.
+ *
+ * Yes, this is a hack, but one that heavily improves the UX without
+ * introducing any significant issues.
+ */
+ cmdline = g_strdup(machine->kernel_cmdline);
+ bus = sysbus_get_default();
+ QTAILQ_FOREACH(kid, &bus->children, sibling) {
+ DeviceState *dev = kid->child;
+ ObjectClass *class = object_get_class(OBJECT(dev));
+
+ if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) {
+ VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
+ VirtioBusState *mmio_virtio_bus = &mmio->bus;
+ BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
+
+ if (!QTAILQ_EMPTY(&mmio_bus->children)) {
+ gchar *mmio_cmdline = microvm_get_mmio_cmdline(mmio_bus->name);
+ if (mmio_cmdline) {
+ char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
+ g_free(mmio_cmdline);
+ g_free(cmdline);
+ cmdline = newcmd;
+ }
+ }
+ }
+ }
+
+ fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
+ fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
+}
+
+static void microvm_machine_state_init(MachineState *machine)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(machine);
+ X86MachineState *x86ms = X86_MACHINE(machine);
+ Error *local_err = NULL;
+
+ microvm_memory_init(mms);
+
+ x86_cpus_init(x86ms, CPU_VERSION_LATEST);
+ if (local_err) {
+ error_report_err(local_err);
+ exit(1);
+ }
+
+ microvm_devices_init(mms);
+}
+
+static void microvm_machine_reset(MachineState *machine)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(machine);
+ CPUState *cs;
+ X86CPU *cpu;
+
+ if (machine->kernel_filename != NULL &&
+ mms->auto_kernel_cmdline && !mms->kernel_cmdline_fixed) {
+ microvm_fix_kernel_cmdline(machine);
+ mms->kernel_cmdline_fixed = true;
+ }
+
+ qemu_devices_reset();
+
+ CPU_FOREACH(cs) {
+ cpu = X86_CPU(cs);
+
+ if (cpu->apic_state) {
+ device_reset(cpu->apic_state);
+ }
+ }
+}
+
+static void microvm_machine_get_pic(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+ OnOffAuto pic = mms->pic;
+
+ visit_type_OnOffAuto(v, name, &pic, errp);
+}
+
+static void microvm_machine_set_pic(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &mms->pic, errp);
+}
+
+static void microvm_machine_get_pit(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+ OnOffAuto pit = mms->pit;
+
+ visit_type_OnOffAuto(v, name, &pit, errp);
+}
+
+static void microvm_machine_set_pit(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &mms->pit, errp);
+}
+
+static void microvm_machine_get_rtc(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+ OnOffAuto rtc = mms->rtc;
+
+ visit_type_OnOffAuto(v, name, &rtc, errp);
+}
+
+static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ visit_type_OnOffAuto(v, name, &mms->rtc, errp);
+}
+
+static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ return mms->isa_serial;
+}
+
+static void microvm_machine_set_isa_serial(Object *obj, bool value,
+ Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ mms->isa_serial = value;
+}
+
+static bool microvm_machine_get_option_roms(Object *obj, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ return mms->option_roms;
+}
+
+static void microvm_machine_set_option_roms(Object *obj, bool value,
+ Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ mms->option_roms = value;
+}
+
+static bool microvm_machine_get_auto_kernel_cmdline(Object *obj, Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ return mms->auto_kernel_cmdline;
+}
+
+static void microvm_machine_set_auto_kernel_cmdline(Object *obj, bool value,
+ Error **errp)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ mms->auto_kernel_cmdline = value;
+}
+
+static void microvm_machine_initfn(Object *obj)
+{
+ MicrovmMachineState *mms = MICROVM_MACHINE(obj);
+
+ /* Configuration */
+ mms->pic = ON_OFF_AUTO_AUTO;
+ mms->pit = ON_OFF_AUTO_AUTO;
+ mms->rtc = ON_OFF_AUTO_AUTO;
+ mms->isa_serial = true;
+ mms->option_roms = true;
+ mms->auto_kernel_cmdline = true;
+
+ /* State */
+ mms->kernel_cmdline_fixed = false;
+}
+
+static void microvm_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->init = microvm_machine_state_init;
+
+ mc->family = "microvm_i386";
+ mc->desc = "microvm (i386)";
+ mc->units_per_default_bus = 1;
+ mc->no_floppy = 1;
+ mc->max_cpus = 288;
+ mc->has_hotpluggable_cpus = false;
+ mc->auto_enable_numa_with_memhp = false;
+ mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
+ mc->nvdimm_supported = false;
+
+ /* Avoid relying too much on kernel components */
+ mc->default_kernel_irqchip_split = true;
+
+ /* Machine class handlers */
+ mc->reset = microvm_machine_reset;
+
+ object_class_property_add(oc, MICROVM_MACHINE_PIC, "OnOffAuto",
+ microvm_machine_get_pic,
+ microvm_machine_set_pic,
+ NULL, NULL, &error_abort);
+ object_class_property_set_description(oc, MICROVM_MACHINE_PIC,
+ "Enable i8259 PIC", &error_abort);
+
+ object_class_property_add(oc, MICROVM_MACHINE_PIT, "OnOffAuto",
+ microvm_machine_get_pit,
+ microvm_machine_set_pit,
+ NULL, NULL, &error_abort);
+ object_class_property_set_description(oc, MICROVM_MACHINE_PIT,
+ "Enable i8254 PIT", &error_abort);
+
+ object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto",
+ microvm_machine_get_rtc,
+ microvm_machine_set_rtc,
+ NULL, NULL, &error_abort);
+ object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
+ "Enable MC146818 RTC", &error_abort);
+
+ object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
+ microvm_machine_get_isa_serial,
+ microvm_machine_set_isa_serial,
+ &error_abort);
+ object_class_property_set_description(oc, MICROVM_MACHINE_ISA_SERIAL,
+ "Set off to disable the instantiation an ISA serial port",
+ &error_abort);
+
+ object_class_property_add_bool(oc, MICROVM_MACHINE_OPTION_ROMS,
+ microvm_machine_get_option_roms,
+ microvm_machine_set_option_roms,
+ &error_abort);
+ object_class_property_set_description(oc, MICROVM_MACHINE_OPTION_ROMS,
+ "Set off to disable loading option ROMs", &error_abort);
+
+ object_class_property_add_bool(oc, MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
+ microvm_machine_get_auto_kernel_cmdline,
+ microvm_machine_set_auto_kernel_cmdline,
+ &error_abort);
+ object_class_property_set_description(oc,
+ MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
+ "Set off to disable adding virtio-mmio devices to the kernel cmdline",
+ &error_abort);
+}
+
+static const TypeInfo microvm_machine_info = {
+ .name = TYPE_MICROVM_MACHINE,
+ .parent = TYPE_X86_MACHINE,
+ .instance_size = sizeof(MicrovmMachineState),
+ .instance_init = microvm_machine_initfn,
+ .class_size = sizeof(MicrovmMachineClass),
+ .class_init = microvm_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { }
+ },
+};
+
+static void microvm_machine_init(void)
+{
+ type_register_static(µvm_machine_info);
+}
+type_init(microvm_machine_init);
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
new file mode 100644
index 0000000..ba68d1f
--- /dev/null
+++ b/include/hw/i386/microvm.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ * Copyright (c) 2019 Red Hat, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_I386_MICROVM_H
+#define HW_I386_MICROVM_H
+
+#include "qemu-common.h"
+#include "exec/hwaddr.h"
+#include "qemu/notify.h"
+
+#include "hw/boards.h"
+#include "hw/i386/x86.h"
+
+/* Platform virtio definitions */
+#define VIRTIO_MMIO_BASE 0xc0000000
+#define VIRTIO_IRQ_BASE 5
+#define VIRTIO_NUM_TRANSPORTS 8
+#define VIRTIO_CMDLINE_MAXLEN 64
+
+/* Machine type options */
+#define MICROVM_MACHINE_PIT "pit"
+#define MICROVM_MACHINE_PIC "pic"
+#define MICROVM_MACHINE_RTC "rtc"
+#define MICROVM_MACHINE_ISA_SERIAL "isa-serial"
+#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
+#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
+
+typedef struct {
+ X86MachineClass parent;
+ HotplugHandler *(*orig_hotplug_handler)(MachineState *machine,
+ DeviceState *dev);
+} MicrovmMachineClass;
+
+typedef struct {
+ X86MachineState parent;
+
+ /* Machine type options */
+ OnOffAuto pic;
+ OnOffAuto pit;
+ OnOffAuto rtc;
+ bool isa_serial;
+ bool option_roms;
+ bool auto_kernel_cmdline;
+
+ /* Machine state */
+ bool kernel_cmdline_fixed;
+} MicrovmMachineState;
+
+#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
+#define MICROVM_MACHINE(obj) \
+ OBJECT_CHECK(MicrovmMachineState, (obj), TYPE_MICROVM_MACHINE)
+#define MICROVM_MACHINE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(MicrovmMachineClass, obj, TYPE_MICROVM_MACHINE)
+#define MICROVM_MACHINE_CLASS(class) \
+ OBJECT_CLASS_CHECK(MicrovmMachineClass, class, TYPE_MICROVM_MACHINE)
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PULL 20/39] hw/i386: Introduce the microvm machine type
2019-10-24 14:03 ` [PULL 20/39] hw/i386: Introduce the " Paolo Bonzini
@ 2019-11-12 10:18 ` Peter Maydell
2019-11-12 11:57 ` Sergio Lopez
0 siblings, 1 reply; 51+ messages in thread
From: Peter Maydell @ 2019-11-12 10:18 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers, Sergio Lopez
On Thu, 24 Oct 2019 at 16:19, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> From: Sergio Lopez <slp@redhat.com>
>
> microvm is a machine type inspired by Firecracker and constructed
> after its machine model.
>
> It's a minimalist machine type without PCI nor ACPI support, designed
> for short-lived guests. microvm also establishes a baseline for
> benchmarking and optimizing both QEMU and guest operating systems,
> since it is optimized for both boot time and footprint.
Hi; Coverity points out a memory leak in this commit
(CID 1407218):
> +static void microvm_fix_kernel_cmdline(MachineState *machine)
> +{
> + X86MachineState *x86ms = X86_MACHINE(machine);
> + BusState *bus;
> + BusChild *kid;
> + char *cmdline;
> +
> + /*
> + * Find MMIO transports with attached devices, and add them to the kernel
> + * command line.
> + *
> + * Yes, this is a hack, but one that heavily improves the UX without
> + * introducing any significant issues.
> + */
> + cmdline = g_strdup(machine->kernel_cmdline);
Here we allocate memory for cmdline...
> + bus = sysbus_get_default();
> + QTAILQ_FOREACH(kid, &bus->children, sibling) {
> + DeviceState *dev = kid->child;
> + ObjectClass *class = object_get_class(OBJECT(dev));
> +
> + if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) {
> + VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
> + VirtioBusState *mmio_virtio_bus = &mmio->bus;
> + BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
> +
> + if (!QTAILQ_EMPTY(&mmio_bus->children)) {
> + gchar *mmio_cmdline = microvm_get_mmio_cmdline(mmio_bus->name);
> + if (mmio_cmdline) {
> + char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
> + g_free(mmio_cmdline);
> + g_free(cmdline);
> + cmdline = newcmd;
> + }
> + }
> + }
> + }
> +
> + fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
> + fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
...but fw_cfg_modify_string() takes a copy of the string it's passed,
so we still have ownership of 'cmdline' and need to free it here
to avoid a leak.
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PULL 20/39] hw/i386: Introduce the microvm machine type
2019-11-12 10:18 ` Peter Maydell
@ 2019-11-12 11:57 ` Sergio Lopez
0 siblings, 0 replies; 51+ messages in thread
From: Sergio Lopez @ 2019-11-12 11:57 UTC (permalink / raw)
To: Peter Maydell; +Cc: Paolo Bonzini, QEMU Developers
Peter Maydell <peter.maydell@linaro.org> writes:
> On Thu, 24 Oct 2019 at 16:19, Paolo Bonzini <pbonzini@redhat.com> wrote:
>>
>> From: Sergio Lopez <slp@redhat.com>
>>
>> microvm is a machine type inspired by Firecracker and constructed
>> after its machine model.
>>
>> It's a minimalist machine type without PCI nor ACPI support, designed
>> for short-lived guests. microvm also establishes a baseline for
>> benchmarking and optimizing both QEMU and guest operating systems,
>> since it is optimized for both boot time and footprint.
>
> Hi; Coverity points out a memory leak in this commit
> (CID 1407218):
>
>
>> +static void microvm_fix_kernel_cmdline(MachineState *machine)
>> +{
>> + X86MachineState *x86ms = X86_MACHINE(machine);
>> + BusState *bus;
>> + BusChild *kid;
>> + char *cmdline;
>> +
>> + /*
>> + * Find MMIO transports with attached devices, and add them to the kernel
>> + * command line.
>> + *
>> + * Yes, this is a hack, but one that heavily improves the UX without
>> + * introducing any significant issues.
>> + */
>> + cmdline = g_strdup(machine->kernel_cmdline);
>
> Here we allocate memory for cmdline...
>
>> + bus = sysbus_get_default();
>> + QTAILQ_FOREACH(kid, &bus->children, sibling) {
>> + DeviceState *dev = kid->child;
>> + ObjectClass *class = object_get_class(OBJECT(dev));
>> +
>> + if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) {
>> + VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
>> + VirtioBusState *mmio_virtio_bus = &mmio->bus;
>> + BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
>> +
>> + if (!QTAILQ_EMPTY(&mmio_bus->children)) {
>> + gchar *mmio_cmdline = microvm_get_mmio_cmdline(mmio_bus->name);
>> + if (mmio_cmdline) {
>> + char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
>> + g_free(mmio_cmdline);
>> + g_free(cmdline);
>> + cmdline = newcmd;
>> + }
>> + }
>> + }
>> + }
>> +
>> + fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
>> + fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
>
> ...but fw_cfg_modify_string() takes a copy of the string it's passed,
> so we still have ownership of 'cmdline' and need to free it here
> to avoid a leak.
Ack, will send a patch ASAP.
Thanks,
Sergio.
>> +}
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PULL 21/39] MAINTAINERS: add microvm related files
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (19 preceding siblings ...)
2019-10-24 14:03 ` [PULL 20/39] hw/i386: Introduce the " Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 22/39] checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE) Paolo Bonzini
` (19 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Lopez
From: Sergio Lopez <slp@redhat.com>
Add a new "microvm" section under "X86 Machines" with the new files
related to this machine type.
Signed-off-by: Sergio Lopez <slp@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 250ce8e..72ab731 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1275,6 +1275,15 @@ F: include/hw/timer/hpet.h
F: include/hw/timer/i8254*
F: include/hw/timer/mc146818rtc*
+microvm
+M: Sergio Lopez <slp@redhat.com>
+M: Paolo Bonzini <pbonzini@redhat.com>
+S: Maintained
+F: docs/microvm.rst
+F: hw/i386/microvm.c
+F: include/hw/i386/microvm.h
+F: pc-bios/bios-microvm.bin
+
Machine core
M: Eduardo Habkost <ehabkost@redhat.com>
M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 22/39] checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE)
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (20 preceding siblings ...)
2019-10-24 14:03 ` [PULL 21/39] MAINTAINERS: add microvm related files Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 23/39] runstate: ignore exit request in finish migrate state Paolo Bonzini
` (18 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Wei Yang, Stefan Hajnoczi
From: Wei Yang <richardw.yang@linux.intel.com>
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
CC: Richard Henderson <richard.henderson@linaro.org>
CC: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20191017004633.13229-1-richardw.yang@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
scripts/checkpatch.pl | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index aa9a354..ab68a16 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2915,6 +2915,12 @@ sub process {
if ($line =~ /\bbzero\(/) {
ERROR("use memset() instead of bzero()\n" . $herecurr);
}
+ if ($line =~ /\bgetpagesize\(\)/) {
+ ERROR("use qemu_real_host_page_size instead of getpagesize()\n" . $herecurr);
+ }
+ if ($line =~ /\bsysconf\(_SC_PAGESIZE\)/) {
+ ERROR("use qemu_real_host_page_size instead of sysconf(_SC_PAGESIZE)\n" . $herecurr);
+ }
my $non_exit_glib_asserts = qr{g_assert_cmpstr|
g_assert_cmpint|
g_assert_cmpuint|
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 23/39] runstate: ignore exit request in finish migrate state
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (21 preceding siblings ...)
2019-10-24 14:03 ` [PULL 22/39] checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE) Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 24/39] hw/timer/mc146818rtc: Only include qapi-commands-misc on I386 Paolo Bonzini
` (17 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier
From: Laurent Vivier <lvivier@redhat.com>
Trying to reboot a VM while a migration is running can
move to the prelaunch state (because of the reset) while
the runstate is in finish migrate state.
As the logical step after the finish migrate is postmigrate,
this can create an invalid state transition from prelaunch state
to postmigrate state and this raises an error and aborts:
invalid runstate transition: 'prelaunch' -> 'postmigrate'
As we are not able to manage reset in finish migrate state the
best we can do is to ignore any changes and delay them until
the next state which should be postmigrate and which should allow
this kind of transition.
Reported-by: Lukáš Doktor <ldoktor@redhat.com>
Suggested-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20191017101806.3644-1-lvivier@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
vl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/vl.c b/vl.c
index 4489cfb..4a7d011 100644
--- a/vl.c
+++ b/vl.c
@@ -1744,6 +1744,9 @@ static bool main_loop_should_exit(void)
RunState r;
ShutdownCause request;
+ if (runstate_check(RUN_STATE_FINISH_MIGRATE)) {
+ return false;
+ }
if (preconfig_exit_requested) {
if (runstate_check(RUN_STATE_PRECONFIG)) {
runstate_set(RUN_STATE_PRELAUNCH);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 24/39] hw/timer/mc146818rtc: Only include qapi-commands-misc on I386
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (22 preceding siblings ...)
2019-10-24 14:03 ` [PULL 23/39] runstate: ignore exit request in finish migrate state Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 25/39] x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE Paolo Bonzini
` (16 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Commit a6c7040fb09 restricted the rtc-reset-reinjection command
to the I386 target.
Restrict the "qapi/qapi-commands-misc-target.h" header to it too.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191017162614.21327-1-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/timer/mc146818rtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 0e7cf97..c979db0 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -37,12 +37,12 @@
#include "hw/timer/mc146818rtc.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
-#include "qapi/qapi-commands-misc-target.h"
#include "qapi/qapi-events-misc-target.h"
#include "qapi/visitor.h"
#include "exec/address-spaces.h"
#ifdef TARGET_I386
+#include "qapi/qapi-commands-misc-target.h"
#include "hw/i386/apic.h"
#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 25/39] x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (23 preceding siblings ...)
2019-10-24 14:03 ` [PULL 24/39] hw/timer/mc146818rtc: Only include qapi-commands-misc on I386 Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 26/39] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR Paolo Bonzini
` (15 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Jingqi Liu, Tao Xu
From: Tao Xu <tao3.xu@intel.com>
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of the user wait instructions is indicated by the presence of the CPUID
feature flag WAITPKG CPUID.0x07.0x0:ECX[5]. User wait instructions may
be executed at any privilege level, and use IA32_UMWAIT_CONTROL MSR to
set the maximum time.
The patch enable the umonitor, umwait and tpause features in KVM.
Because umwait and tpause can put a (psysical) CPU into a power saving
state, by default we dont't expose it to kvm and enable it only when
guest CPUID has it. And use QEMU command-line "-overcommit cpu-pm=on"
(enable_cpu_pm is enabled), a VM can use UMONITOR, UMWAIT and TPAUSE
instructions. If the instruction causes a delay, the amount of time
delayed is called here the physical delay. The physical delay is first
computed by determining the virtual delay (the time to delay relative to
the VM’s timestamp counter). Otherwise, UMONITOR, UMWAIT and TPAUSE cause
an invalid-opcode exception(#UD).
The release document ref below link:
https://software.intel.com/sites/default/files/\
managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191011074103.30393-2-tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 6 ++++++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6c87c99..b635302 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1058,7 +1058,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
- NULL /* ospke */, NULL, "avx512vbmi2", NULL,
+ NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
"gfni", "vaes", "vpclmulqdq", "avx512vnni",
"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
"la57", NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c50a9c7..112f867 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -731,6 +731,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_ECX_PKU (1U << 3)
/* OS Enable Protection Keys */
#define CPUID_7_0_ECX_OSPKE (1U << 4)
+/* UMONITOR/UMWAIT/TPAUSE Instructions */
+#define CPUID_7_0_ECX_WAITPKG (1U << 5)
/* Additional AVX-512 Vector Byte Manipulation Instruction */
#define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
/* Galois Field New Instructions */
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 49a3011..94c2339 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -401,6 +401,12 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
if (host_tsx_blacklisted()) {
ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
}
+ } else if (function == 7 && index == 0 && reg == R_ECX) {
+ if (enable_cpu_pm) {
+ ret |= CPUID_7_0_ECX_WAITPKG;
+ } else {
+ ret &= ~CPUID_7_0_ECX_WAITPKG;
+ }
} else if (function == 7 && index == 0 && reg == R_EDX) {
/*
* Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 26/39] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (24 preceding siblings ...)
2019-10-24 14:03 ` [PULL 25/39] x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 27/39] hw/i386/pc: Extract pc_gsi_create() Paolo Bonzini
` (14 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Jingqi Liu, Tao Xu
From: Tao Xu <tao3.xu@intel.com>
UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR
index E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191011074103.30393-3-tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 13 +++++++++++++
target/i386/machine.c | 20 ++++++++++++++++++++
3 files changed, 35 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 112f867..b772e82 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -452,6 +452,7 @@ typedef enum X86Seg {
#define MSR_IA32_BNDCFGS 0x00000d90
#define MSR_IA32_XSS 0x00000da0
+#define MSR_IA32_UMWAIT_CONTROL 0xe1
#define MSR_IA32_VMX_BASIC 0x00000480
#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
@@ -1587,6 +1588,7 @@ typedef struct CPUX86State {
uint16_t fpregs_format_vmstate;
uint64_t xss;
+ uint32_t umwait;
TPRAccess tpr_access_type;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 94c2339..bfd09bd 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -95,6 +95,7 @@ static bool has_msr_hv_stimer;
static bool has_msr_hv_frequencies;
static bool has_msr_hv_reenlightenment;
static bool has_msr_xss;
+static bool has_msr_umwait;
static bool has_msr_spec_ctrl;
static bool has_msr_virt_ssbd;
static bool has_msr_smi_count;
@@ -2005,6 +2006,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_XSS:
has_msr_xss = true;
break;
+ case MSR_IA32_UMWAIT_CONTROL:
+ has_msr_umwait = true;
+ break;
case HV_X64_MSR_CRASH_CTL:
has_msr_hv_crash = true;
break;
@@ -2684,6 +2688,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_xss) {
kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
}
+ if (has_msr_umwait) {
+ kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
+ }
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
@@ -3097,6 +3104,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_xss) {
kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
}
+ if (has_msr_umwait) {
+ kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
+ }
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
@@ -3349,6 +3359,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_XSS:
env->xss = msrs[i].data;
break;
+ case MSR_IA32_UMWAIT_CONTROL:
+ env->umwait = msrs[i].data;
+ break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 2767b30..6481f84 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -943,6 +943,25 @@ static const VMStateDescription vmstate_xss = {
}
};
+static bool umwait_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->umwait != 0;
+}
+
+static const VMStateDescription vmstate_umwait = {
+ .name = "cpu/umwait",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = umwait_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(env.umwait, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
#ifdef TARGET_X86_64
static bool pkru_needed(void *opaque)
{
@@ -1391,6 +1410,7 @@ VMStateDescription vmstate_x86_cpu = {
&vmstate_msr_hyperv_reenlightenment,
&vmstate_avx512,
&vmstate_xss,
+ &vmstate_umwait,
&vmstate_tsc_khz,
&vmstate_msr_smi_count,
#ifdef TARGET_X86_64
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 27/39] hw/i386/pc: Extract pc_gsi_create()
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (25 preceding siblings ...)
2019-10-24 14:03 ` [PULL 26/39] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 28/39] hw/i386/pc: Move gsi_state creation code Paolo Bonzini
` (13 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The GSI creation code is common to all PC machines, extract the
common code.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018135910.24286-2-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc.c | 15 +++++++++++++++
hw/i386/pc_piix.c | 9 +--------
hw/i386/pc_q35.c | 9 +--------
include/hw/i386/pc.h | 2 ++
4 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a8888dd..e8a54ac 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -355,6 +355,21 @@ void gsi_handler(void *opaque, int n, int level)
qemu_set_irq(s->ioapic_irq[n], level);
}
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
+{
+ GSIState *s;
+
+ s = g_new0(GSIState, 1);
+ if (kvm_ioapic_in_kernel()) {
+ kvm_pc_setup_irq_routing(pci_enabled);
+ *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
+ } else {
+ *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
+ }
+
+ return s;
+}
+
static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index a86317c..0cc951a 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -189,14 +189,7 @@ static void pc_init1(MachineState *machine,
xen_load_linux(pcms);
}
- gsi_state = g_malloc0(sizeof(*gsi_state));
- if (kvm_ioapic_in_kernel()) {
- kvm_pc_setup_irq_routing(pcmc->pci_enabled);
- x86ms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
- GSI_NUM_PINS);
- } else {
- x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
- }
+ gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
if (pcmc->pci_enabled) {
pci_bus = i440fx_init(host_type,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 75c8caf..255c803 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -212,14 +212,7 @@ static void pc_q35_init(MachineState *machine)
}
/* irq lines */
- gsi_state = g_malloc0(sizeof(*gsi_state));
- if (kvm_ioapic_in_kernel()) {
- kvm_pc_setup_irq_routing(pcmc->pci_enabled);
- x86ms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
- GSI_NUM_PINS);
- } else {
- x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
- }
+ gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
/* create pci host bus */
q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 13c4eac..8c5dc39 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -157,6 +157,8 @@ typedef struct GSIState {
void gsi_handler(void *opaque, int n, int level);
+GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
+
/* vmport.c */
#define TYPE_VMPORT "vmport"
typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 28/39] hw/i386/pc: Move gsi_state creation code
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (26 preceding siblings ...)
2019-10-24 14:03 ` [PULL 27/39] hw/i386/pc: Extract pc_gsi_create() Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 29/39] hw/i386/pc: Extract pc_i8259_create() Paolo Bonzini
` (12 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The code block related to IRQ starts few lines later. Move
the comment and the pc_gsi_create() invocation where we start
to use the IRQs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018135910.24286-4-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_q35.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 255c803..6cf12b7 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -211,9 +211,6 @@ static void pc_q35_init(MachineState *machine)
rom_memory, &ram_memory);
}
- /* irq lines */
- gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
-
/* create pci host bus */
q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
@@ -247,6 +244,9 @@ static void pc_q35_init(MachineState *machine)
object_property_set_link(OBJECT(machine), OBJECT(lpc),
PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
+ /* irq lines */
+ gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
+
ich9_lpc = ICH9_LPC_DEVICE(lpc);
lpc_dev = DEVICE(lpc);
for (i = 0; i < GSI_NUM_PINS; i++) {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 29/39] hw/i386/pc: Extract pc_i8259_create()
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (27 preceding siblings ...)
2019-10-24 14:03 ` [PULL 28/39] hw/i386/pc: Move gsi_state creation code Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 30/39] hw/i386/pc: Remove kvm_i386.h include Paolo Bonzini
` (11 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
The i8259 creation code is common to all PC machines, extract the
common code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018135910.24286-5-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc.c | 19 +++++++++++++++++++
hw/i386/pc_piix.c | 13 +------------
hw/i386/pc_q35.c | 14 +-------------
include/hw/i386/pc.h | 1 +
4 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e8a54ac..5fce60c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1474,6 +1474,25 @@ void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
rom_reset_order_override();
}
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
+{
+ qemu_irq *i8259;
+
+ if (kvm_pic_in_kernel()) {
+ i8259 = kvm_i8259_init(isa_bus);
+ } else if (xen_enabled()) {
+ i8259 = xen_interrupt_controller_init();
+ } else {
+ i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
+ }
+
+ for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
+ i8259_irqs[i] = i8259[i];
+ }
+
+ g_free(i8259);
+}
+
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
{
DeviceState *dev;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0cc951a..648dc9a 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -82,7 +82,6 @@ static void pc_init1(MachineState *machine,
ISABus *isa_bus;
PCII440FXState *i440fx_state;
int piix3_devfn = -1;
- qemu_irq *i8259;
qemu_irq smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -209,18 +208,8 @@ static void pc_init1(MachineState *machine,
}
isa_bus_irqs(isa_bus, x86ms->gsi);
- if (kvm_pic_in_kernel()) {
- i8259 = kvm_i8259_init(isa_bus);
- } else if (xen_enabled()) {
- i8259 = xen_interrupt_controller_init();
- } else {
- i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
- }
+ pc_i8259_create(isa_bus, gsi_state->i8259_irq);
- for (i = 0; i < ISA_NUM_IRQS; i++) {
- gsi_state->i8259_irq[i] = i8259[i];
- }
- g_free(i8259);
if (pcmc->pci_enabled) {
ioapic_init_gsi(gsi_state, "i440fx");
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 6cf12b7..157d1da 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -130,7 +130,6 @@ static void pc_q35_init(MachineState *machine)
MemoryRegion *ram_memory;
GSIState *gsi_state;
ISABus *isa_bus;
- qemu_irq *i8259;
int i;
ICH9LPCState *ich9_lpc;
PCIDevice *ahci;
@@ -257,18 +256,7 @@ static void pc_q35_init(MachineState *machine)
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
- if (kvm_pic_in_kernel()) {
- i8259 = kvm_i8259_init(isa_bus);
- } else if (xen_enabled()) {
- i8259 = xen_interrupt_controller_init();
- } else {
- i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
- }
-
- for (i = 0; i < ISA_NUM_IRQS; i++) {
- gsi_state->i8259_irq[i] = i8259[i];
- }
- g_free(i8259);
+ pc_i8259_create(isa_bus, gsi_state->i8259_irq);
if (pcmc->pci_enabled) {
ioapic_init_gsi(gsi_state, "q35");
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 8c5dc39..5923318 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -219,6 +219,7 @@ void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
+void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
ISADevice *pc_find_fdc0(void);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 30/39] hw/i386/pc: Remove kvm_i386.h include
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (28 preceding siblings ...)
2019-10-24 14:03 ` [PULL 29/39] hw/i386/pc: Extract pc_i8259_create() Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 31/39] mc146818rtc: move structure to header file Paolo Bonzini
` (10 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@redhat.com>
By extracting pc_gsi_create() and pc_i8259_create() we removed
the access to "kvm_i386.h" from the machine code. We can now
remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191015162705.28087-25-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_piix.c | 1 -
hw/i386/pc_q35.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 648dc9a..3a4a64a 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -57,7 +57,6 @@
#endif
#include "migration/global_state.h"
#include "migration/misc.h"
-#include "kvm_i386.h"
#include "sysemu/numa.h"
#define MAX_IDE_BUS 2
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 157d1da..def3bc2 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -36,7 +36,6 @@
#include "hw/timer/mc146818rtc.h"
#include "hw/xen/xen.h"
#include "sysemu/kvm.h"
-#include "kvm_i386.h"
#include "hw/kvm/clock.h"
#include "hw/pci-host/q35.h"
#include "hw/qdev-properties.h"
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 31/39] mc146818rtc: move structure to header file
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (29 preceding siblings ...)
2019-10-24 14:03 ` [PULL 30/39] hw/i386/pc: Remove kvm_i386.h include Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 32/39] mc146818rtc: Move RTC_ISA_IRQ definition Paolo Bonzini
` (9 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Hervé Poussineau
From: Hervé Poussineau <hpoussin@reactos.org>
We are now able to embed a timer in another object.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-4-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018133547.10936-2-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/timer/mc146818rtc.c | 30 ------------------------------
include/hw/timer/mc146818rtc.h | 33 +++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 30 deletions(-)
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index c979db0..09edb93 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -71,36 +71,6 @@
#define RTC_CLOCK_RATE 32768
#define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
-#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
-
-typedef struct RTCState {
- ISADevice parent_obj;
-
- MemoryRegion io;
- MemoryRegion coalesced_io;
- uint8_t cmos_data[128];
- uint8_t cmos_index;
- int32_t base_year;
- uint64_t base_rtc;
- uint64_t last_update;
- int64_t offset;
- qemu_irq irq;
- int it_shift;
- /* periodic timer */
- QEMUTimer *periodic_timer;
- int64_t next_periodic_time;
- /* update-ended timer */
- QEMUTimer *update_timer;
- uint64_t next_alarm_time;
- uint16_t irq_reinject_on_ack_count;
- uint32_t irq_coalesced;
- uint32_t period;
- QEMUTimer *coalesced_timer;
- LostTickPolicy lost_tick_policy;
- Notifier suspend_notifier;
- QLIST_ENTRY(RTCState) link;
-} RTCState;
-
static void rtc_set_time(RTCState *s);
static void rtc_update_time(RTCState *s);
static void rtc_set_cmos(RTCState *s, const struct tm *tm);
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index fe6ed63..0f1c886 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -1,10 +1,43 @@
#ifndef MC146818RTC_H
#define MC146818RTC_H
+#include "qapi/qapi-types-misc.h"
+#include "qemu/queue.h"
+#include "qemu/timer.h"
#include "hw/isa/isa.h"
#include "hw/timer/mc146818rtc_regs.h"
#define TYPE_MC146818_RTC "mc146818rtc"
+#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
+
+typedef struct RTCState {
+ ISADevice parent_obj;
+
+ MemoryRegion io;
+ MemoryRegion coalesced_io;
+ uint8_t cmos_data[128];
+ uint8_t cmos_index;
+ int32_t base_year;
+ uint64_t base_rtc;
+ uint64_t last_update;
+ int64_t offset;
+ qemu_irq irq;
+ int it_shift;
+ /* periodic timer */
+ QEMUTimer *periodic_timer;
+ int64_t next_periodic_time;
+ /* update-ended timer */
+ QEMUTimer *update_timer;
+ uint64_t next_alarm_time;
+ uint16_t irq_reinject_on_ack_count;
+ uint32_t irq_coalesced;
+ uint32_t period;
+ QEMUTimer *coalesced_timer;
+ Notifier clock_reset_notifier;
+ LostTickPolicy lost_tick_policy;
+ Notifier suspend_notifier;
+ QLIST_ENTRY(RTCState) link;
+} RTCState;
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 32/39] mc146818rtc: Move RTC_ISA_IRQ definition
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (30 preceding siblings ...)
2019-10-24 14:03 ` [PULL 31/39] mc146818rtc: move structure to header file Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 33/39] mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c Paolo Bonzini
` (8 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The ISA default number for the RTC devices is not related to its
registers neither. Move this definition to "hw/timer/mc146818rtc.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018133547.10936-3-philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/timer/mc146818rtc.h | 2 ++
include/hw/timer/mc146818rtc_regs.h | 2 --
tests/rtc-test.c | 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 0f1c886..17761cf 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -39,6 +39,8 @@ typedef struct RTCState {
QLIST_ENTRY(RTCState) link;
} RTCState;
+#define RTC_ISA_IRQ 8
+
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);
void rtc_set_memory(ISADevice *dev, int addr, int val);
diff --git a/include/hw/timer/mc146818rtc_regs.h b/include/hw/timer/mc146818rtc_regs.h
index bfbb57e..631f71c 100644
--- a/include/hw/timer/mc146818rtc_regs.h
+++ b/include/hw/timer/mc146818rtc_regs.h
@@ -27,8 +27,6 @@
#include "qemu/timer.h"
-#define RTC_ISA_IRQ 8
-
#define RTC_SECONDS 0
#define RTC_SECONDS_ALARM 1
#define RTC_MINUTES 2
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 6309b0e..18f8956 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -15,6 +15,7 @@
#include "libqtest-single.h"
#include "qemu/timer.h"
+#include "hw/timer/mc146818rtc.h"
#include "hw/timer/mc146818rtc_regs.h"
#define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 33/39] mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (31 preceding siblings ...)
2019-10-24 14:03 ` [PULL 32/39] mc146818rtc: Move RTC_ISA_IRQ definition Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 34/39] mc146818rtc: always register rtc to rtc list Paolo Bonzini
` (7 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Devices/boards wanting to use the MC146818 RTC don't need
the knowledge its internal registers. Move the "mc146818rtc_regs.h"
inclusion to mc146818rtc.c where it is required.
We can not move this file from include/hw/timer/ to hw/timer/ for
local inclusion because the ACPI FADT table use the RTC_CENTURY
register address.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018133547.10936-4-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/timer/mc146818rtc.c | 1 +
include/hw/timer/mc146818rtc.h | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index 09edb93..dce4dae 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -40,6 +40,7 @@
#include "qapi/qapi-events-misc-target.h"
#include "qapi/visitor.h"
#include "exec/address-spaces.h"
+#include "hw/timer/mc146818rtc_regs.h"
#ifdef TARGET_I386
#include "qapi/qapi-commands-misc-target.h"
diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h
index 17761cf..a857dcd 100644
--- a/include/hw/timer/mc146818rtc.h
+++ b/include/hw/timer/mc146818rtc.h
@@ -5,7 +5,6 @@
#include "qemu/queue.h"
#include "qemu/timer.h"
#include "hw/isa/isa.h"
-#include "hw/timer/mc146818rtc_regs.h"
#define TYPE_MC146818_RTC "mc146818rtc"
#define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 34/39] mc146818rtc: always register rtc to rtc list
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (32 preceding siblings ...)
2019-10-24 14:03 ` [PULL 33/39] mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 35/39] audio: fix missing break Paolo Bonzini
` (6 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Hervé Poussineau
From: Hervé Poussineau <hpoussin@reactos.org>
We are not required anymore to use rtc_init() function.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-5-hpoussin@reactos.org>
[PMD: rebased, fix OBJECT() value]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191018133547.10936-5-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/timer/mc146818rtc.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index dce4dae..0d7784b 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -964,17 +964,16 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
qdev_init_gpio_out(dev, &s->irq, 1);
+ QLIST_INSERT_HEAD(&rtc_devices, s, link);
}
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
{
DeviceState *dev;
ISADevice *isadev;
- RTCState *s;
isadev = isa_create(bus, TYPE_MC146818_RTC);
dev = DEVICE(isadev);
- s = MC146818_RTC(isadev);
qdev_prop_set_int32(dev, "base_year", base_year);
qdev_init_nofail(dev);
if (intercept_irq) {
@@ -982,9 +981,8 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
} else {
isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
}
- QLIST_INSERT_HEAD(&rtc_devices, s, link);
- object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s),
+ object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
"date", NULL);
return isadev;
@@ -1016,8 +1014,6 @@ static void rtc_class_initfn(ObjectClass *klass, void *data)
dc->reset = rtc_resetdev;
dc->vmsd = &vmstate_rtc;
dc->props = mc146818rtc_properties;
- /* Reason: needs to be wired up by rtc_init() */
- dc->user_creatable = false;
}
static const TypeInfo mc146818rtc_info = {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 35/39] audio: fix missing break
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (33 preceding siblings ...)
2019-10-24 14:03 ` [PULL 34/39] mc146818rtc: always register rtc to rtc list Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 15:14 ` Philippe Mathieu-Daudé
2019-10-24 14:03 ` [PULL 36/39] core: replace getpagesize() with qemu_real_host_page_size Paolo Bonzini
` (5 subsequent siblings)
40 siblings, 1 reply; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel
Reported by Coverity (CID 1406449).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
audio/paaudio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/audio/paaudio.c b/audio/paaudio.c
index df541a7..55a91f8 100644
--- a/audio/paaudio.c
+++ b/audio/paaudio.c
@@ -385,6 +385,7 @@ static pa_stream *qpa_simple_new (
map.map[5] = PA_CHANNEL_POSITION_REAR_RIGHT;
map.map[6] = PA_CHANNEL_POSITION_SIDE_LEFT;
map.map[7] = PA_CHANNEL_POSITION_SIDE_RIGHT;
+ break;
default:
dolog("Internal error: unsupported channel count %d\n", ss->channels);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PULL 35/39] audio: fix missing break
2019-10-24 14:03 ` [PULL 35/39] audio: fix missing break Paolo Bonzini
@ 2019-10-24 15:14 ` Philippe Mathieu-Daudé
2019-10-24 16:02 ` Paolo Bonzini
0 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-24 15:14 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel
On 10/24/19 4:03 PM, Paolo Bonzini wrote:
> Reported by Coverity (CID 1406449).
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
I reviewed this one.
> ---
> audio/paaudio.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/audio/paaudio.c b/audio/paaudio.c
> index df541a7..55a91f8 100644
> --- a/audio/paaudio.c
> +++ b/audio/paaudio.c
> @@ -385,6 +385,7 @@ static pa_stream *qpa_simple_new (
> map.map[5] = PA_CHANNEL_POSITION_REAR_RIGHT;
> map.map[6] = PA_CHANNEL_POSITION_SIDE_LEFT;
> map.map[7] = PA_CHANNEL_POSITION_SIDE_RIGHT;
> + break;
>
> default:
> dolog("Internal error: unsupported channel count %d\n", ss->channels);
>
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PULL 35/39] audio: fix missing break
2019-10-24 15:14 ` Philippe Mathieu-Daudé
@ 2019-10-24 16:02 ` Paolo Bonzini
0 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 16:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 24/10/19 17:14, Philippe Mathieu-Daudé wrote:
> On 10/24/19 4:03 PM, Paolo Bonzini wrote:
>> Reported by Coverity (CID 1406449).
>>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>
> I reviewed this one.
Oops, sorry. I must have lost your R-b when moving the patch from one
computer to the other.
Paolo
>> ---
>> audio/paaudio.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/audio/paaudio.c b/audio/paaudio.c
>> index df541a7..55a91f8 100644
>> --- a/audio/paaudio.c
>> +++ b/audio/paaudio.c
>> @@ -385,6 +385,7 @@ static pa_stream *qpa_simple_new (
>> map.map[5] = PA_CHANNEL_POSITION_REAR_RIGHT;
>> map.map[6] = PA_CHANNEL_POSITION_SIDE_LEFT;
>> map.map[7] = PA_CHANNEL_POSITION_SIDE_RIGHT;
>> + break;
>> default:
>> dolog("Internal error: unsupported channel count %d\n",
>> ss->channels);
>>
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PULL 36/39] core: replace getpagesize() with qemu_real_host_page_size
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (34 preceding siblings ...)
2019-10-24 14:03 ` [PULL 35/39] audio: fix missing break Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 37/39] target/i386: move FERR handling to target/i386 Paolo Bonzini
` (4 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Wei Yang
From: Wei Yang <richardw.yang@linux.intel.com>
There are three page size in qemu:
real host page size
host page size
target page size
All of them have dedicate variable to represent. For the last two, we
use the same form in the whole qemu project, while for the first one we
use two forms: qemu_real_host_page_size and getpagesize().
qemu_real_host_page_size is defined to be a replacement of
getpagesize(), so let it serve the role.
[Note] Not fully tested for some arch or device.
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
Message-Id: <20191013021145.16011-3-richardw.yang@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
accel/kvm/kvm-all.c | 6 +++---
backends/hostmem.c | 2 +-
block.c | 4 ++--
block/file-posix.c | 9 +++++----
block/io.c | 2 +-
block/parallels.c | 2 +-
block/qcow2-cache.c | 2 +-
contrib/vhost-user-gpu/vugbm.c | 2 +-
exec.c | 6 +++---
hw/intc/s390_flic_kvm.c | 2 +-
hw/ppc/mac_newworld.c | 2 +-
hw/ppc/spapr_pci.c | 2 +-
hw/rdma/vmw/pvrdma_main.c | 2 +-
hw/vfio/spapr.c | 7 ++++---
include/exec/ram_addr.h | 2 +-
include/qemu/osdep.h | 4 ++--
migration/migration.c | 2 +-
migration/postcopy-ram.c | 4 ++--
monitor/misc.c | 2 +-
target/ppc/kvm.c | 2 +-
tests/vhost-user-bridge.c | 8 ++++----
util/mmap-alloc.c | 10 +++++-----
util/oslib-posix.c | 4 ++--
util/oslib-win32.c | 2 +-
util/vfio-helpers.c | 12 ++++++------
25 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index d2d96d7..140b0bd 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -52,7 +52,7 @@
/* KVM uses PAGE_SIZE in its definition of KVM_COALESCED_MMIO_MAX. We
* need to use the real host PAGE_SIZE, as that's what KVM will use.
*/
-#define PAGE_SIZE getpagesize()
+#define PAGE_SIZE qemu_real_host_page_size
//#define DEBUG_KVM
@@ -507,7 +507,7 @@ static int kvm_get_dirty_pages_log_range(MemoryRegionSection *section,
{
ram_addr_t start = section->offset_within_region +
memory_region_get_ram_addr(section->mr);
- ram_addr_t pages = int128_get64(section->size) / getpagesize();
+ ram_addr_t pages = int128_get64(section->size) / qemu_real_host_page_size;
cpu_physical_memory_set_dirty_lebitmap(bitmap, start, pages);
return 0;
@@ -1841,7 +1841,7 @@ static int kvm_init(MachineState *ms)
* even with KVM. TARGET_PAGE_SIZE is assumed to be the minimum
* page size for the system though.
*/
- assert(TARGET_PAGE_SIZE <= getpagesize());
+ assert(TARGET_PAGE_SIZE <= qemu_real_host_page_size);
s->sigmask_len = 8;
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 6d333dc..e773bdf 100644
--- a/backends/hostmem.c
+++ b/backends/hostmem.c
@@ -304,7 +304,7 @@ size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)
#else
size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)
{
- return getpagesize();
+ return qemu_real_host_page_size;
}
#endif
diff --git a/block.c b/block.c
index dad5a3d..4cffc2b 100644
--- a/block.c
+++ b/block.c
@@ -106,7 +106,7 @@ size_t bdrv_opt_mem_align(BlockDriverState *bs)
{
if (!bs || !bs->drv) {
/* page size or 4k (hdd sector size) should be on the safe side */
- return MAX(4096, getpagesize());
+ return MAX(4096, qemu_real_host_page_size);
}
return bs->bl.opt_mem_alignment;
@@ -116,7 +116,7 @@ size_t bdrv_min_mem_align(BlockDriverState *bs)
{
if (!bs || !bs->drv) {
/* page size or 4k (hdd sector size) should be on the safe side */
- return MAX(4096, getpagesize());
+ return MAX(4096, qemu_real_host_page_size);
}
return bs->bl.min_mem_alignment;
diff --git a/block/file-posix.c b/block/file-posix.c
index 695fcf7..5d1995a 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -327,7 +327,7 @@ static void raw_probe_alignment(BlockDriverState *bs, int fd, Error **errp)
{
BDRVRawState *s = bs->opaque;
char *buf;
- size_t max_align = MAX(MAX_BLOCKSIZE, getpagesize());
+ size_t max_align = MAX(MAX_BLOCKSIZE, qemu_real_host_page_size);
size_t alignments[] = {1, 512, 1024, 2048, 4096};
/* For SCSI generic devices the alignment is not really used.
@@ -1136,13 +1136,14 @@ static void raw_refresh_limits(BlockDriverState *bs, Error **errp)
ret = sg_get_max_segments(s->fd);
if (ret > 0) {
- bs->bl.max_transfer = MIN(bs->bl.max_transfer, ret * getpagesize());
+ bs->bl.max_transfer = MIN(bs->bl.max_transfer,
+ ret * qemu_real_host_page_size);
}
}
raw_probe_alignment(bs, s->fd, errp);
bs->bl.min_mem_alignment = s->buf_align;
- bs->bl.opt_mem_alignment = MAX(s->buf_align, getpagesize());
+ bs->bl.opt_mem_alignment = MAX(s->buf_align, qemu_real_host_page_size);
}
static int check_for_dasd(int fd)
@@ -1705,7 +1706,7 @@ static int allocate_first_block(int fd, size_t max_size)
size_t write_size = (max_size < MAX_BLOCKSIZE)
? BDRV_SECTOR_SIZE
: MAX_BLOCKSIZE;
- size_t max_align = MAX(MAX_BLOCKSIZE, getpagesize());
+ size_t max_align = MAX(MAX_BLOCKSIZE, qemu_real_host_page_size);
void *buf;
ssize_t n;
int ret;
diff --git a/block/io.c b/block/io.c
index f0b86c1..e46d9e8 100644
--- a/block/io.c
+++ b/block/io.c
@@ -160,7 +160,7 @@ void bdrv_refresh_limits(BlockDriverState *bs, Error **errp)
bdrv_merge_limits(&bs->bl, &bs->file->bs->bl);
} else {
bs->bl.min_mem_alignment = 512;
- bs->bl.opt_mem_alignment = getpagesize();
+ bs->bl.opt_mem_alignment = qemu_real_host_page_size;
/* Safe default since most protocols use readv()/writev()/etc */
bs->bl.max_iov = IOV_MAX;
diff --git a/block/parallels.c b/block/parallels.c
index 7cd2714..f1dfb03 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -847,7 +847,7 @@ static int parallels_open(BlockDriverState *bs, QDict *options, int flags,
}
}
- s->bat_dirty_block = 4 * getpagesize();
+ s->bat_dirty_block = 4 * qemu_real_host_page_size;
s->bat_dirty_bmap =
bitmap_new(DIV_ROUND_UP(s->header_size, s->bat_dirty_block));
diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c
index d29b038..7444b9c 100644
--- a/block/qcow2-cache.c
+++ b/block/qcow2-cache.c
@@ -74,7 +74,7 @@ static void qcow2_cache_table_release(Qcow2Cache *c, int i, int num_tables)
/* Using MADV_DONTNEED to discard memory is a Linux-specific feature */
#ifdef CONFIG_LINUX
void *t = qcow2_cache_get_table_addr(c, i);
- int align = getpagesize();
+ int align = qemu_real_host_page_size;
size_t mem_size = (size_t) c->table_size * num_tables;
size_t offset = QEMU_ALIGN_UP((uintptr_t) t, align) - (uintptr_t) t;
size_t length = QEMU_ALIGN_DOWN(mem_size - offset, align);
diff --git a/contrib/vhost-user-gpu/vugbm.c b/contrib/vhost-user-gpu/vugbm.c
index d3bb82f..9c357b6 100644
--- a/contrib/vhost-user-gpu/vugbm.c
+++ b/contrib/vhost-user-gpu/vugbm.c
@@ -52,7 +52,7 @@ struct udmabuf_create {
static size_t
udmabuf_get_size(struct vugbm_buffer *buf)
{
- return ROUND_UP(buf->width * buf->height * 4, getpagesize());
+ return ROUND_UP(buf->width * buf->height * 4, qemu_real_host_page_size);
}
static bool
diff --git a/exec.c b/exec.c
index fb0943c..9fc0d01 100644
--- a/exec.c
+++ b/exec.c
@@ -1756,11 +1756,11 @@ long qemu_maxrampagesize(void)
#else
long qemu_minrampagesize(void)
{
- return getpagesize();
+ return qemu_real_host_page_size;
}
long qemu_maxrampagesize(void)
{
- return getpagesize();
+ return qemu_real_host_page_size;
}
#endif
@@ -2417,7 +2417,7 @@ RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
new_block->max_length = max_size;
assert(max_size >= size);
new_block->fd = -1;
- new_block->page_size = getpagesize();
+ new_block->page_size = qemu_real_host_page_size;
new_block->host = host;
if (host) {
new_block->flags |= RAM_PREALLOC;
diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c
index cedccba..c9ee80e 100644
--- a/hw/intc/s390_flic_kvm.c
+++ b/hw/intc/s390_flic_kvm.c
@@ -25,7 +25,7 @@
#include "migration/qemu-file-types.h"
#include "trace.h"
-#define FLIC_SAVE_INITIAL_SIZE getpagesize()
+#define FLIC_SAVE_INITIAL_SIZE qemu_real_host_page_size
#define FLIC_FAILED (-1UL)
#define FLIC_SAVEVM_VERSION 1
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index c5bbcc7..3594517 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -439,7 +439,7 @@ static void ppc_core99_init(MachineState *machine)
}
/* The NewWorld NVRAM is not located in the MacIO device */
- if (kvm_enabled() && getpagesize() > 4096) {
+ if (kvm_enabled() && qemu_real_host_page_size > 4096) {
/* We can't combine read-write and read-only in a single page, so
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 01ff41d..191b295 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1942,7 +1942,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
* our memory slot is of page size granularity.
*/
if (kvm_enabled()) {
- msi_window_size = getpagesize();
+ msi_window_size = qemu_real_host_page_size;
}
memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c
index 3e36e13..3722d9e 100644
--- a/hw/rdma/vmw/pvrdma_main.c
+++ b/hw/rdma/vmw/pvrdma_main.c
@@ -601,7 +601,7 @@ static void pvrdma_realize(PCIDevice *pdev, Error **errp)
rdma_info_report("Initializing device %s %x.%x", pdev->name,
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
- if (TARGET_PAGE_SIZE != getpagesize()) {
+ if (TARGET_PAGE_SIZE != qemu_real_host_page_size) {
error_setg(errp, "Target page size must be the same as host page size");
return;
}
diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c
index e853eeb..33692fc 100644
--- a/hw/vfio/spapr.c
+++ b/hw/vfio/spapr.c
@@ -196,14 +196,15 @@ int vfio_spapr_create_window(VFIOContainer *container,
* bits_per_level is a safe guess of how much we can allocate per level:
* 8 is the current minimum for CONFIG_FORCE_MAX_ZONEORDER and MAX_ORDER
* is usually bigger than that.
- * Below we look at getpagesize() as TCEs are allocated from system pages.
+ * Below we look at qemu_real_host_page_size as TCEs are allocated from
+ * system pages.
*/
- bits_per_level = ctz64(getpagesize()) + 8;
+ bits_per_level = ctz64(qemu_real_host_page_size) + 8;
create.levels = bits_total / bits_per_level;
if (bits_total % bits_per_level) {
++create.levels;
}
- max_levels = (64 - create.page_shift) / ctz64(getpagesize());
+ max_levels = (64 - create.page_shift) / ctz64(qemu_real_host_page_size);
for ( ; create.levels <= max_levels; ++create.levels) {
ret = ioctl(container->fd, VFIO_IOMMU_SPAPR_TCE_CREATE, &create);
if (!ret) {
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index ad158bb..bed0554 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -373,7 +373,7 @@ static inline void cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap,
hwaddr addr;
ram_addr_t ram_addr;
unsigned long len = (pages + HOST_LONG_BITS - 1) / HOST_LONG_BITS;
- unsigned long hpratio = getpagesize() / TARGET_PAGE_SIZE;
+ unsigned long hpratio = qemu_real_host_page_size / TARGET_PAGE_SIZE;
unsigned long page = BIT_WORD(start >> TARGET_PAGE_BITS);
/* start address is aligned at the start of a word? */
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index c7d242f..0f97d68 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -423,9 +423,9 @@ void qemu_anon_ram_free(void *ptr, size_t size);
# define QEMU_VMALLOC_ALIGN (256 * 4096)
#elif defined(__linux__) && defined(__sparc__)
#include <sys/shm.h>
-# define QEMU_VMALLOC_ALIGN MAX(getpagesize(), SHMLBA)
+# define QEMU_VMALLOC_ALIGN MAX(qemu_real_host_page_size, SHMLBA)
#else
-# define QEMU_VMALLOC_ALIGN getpagesize()
+# define QEMU_VMALLOC_ALIGN qemu_real_host_page_size
#endif
#ifdef CONFIG_POSIX
diff --git a/migration/migration.c b/migration/migration.c
index 3febd0f..4133ed2 100644
--- a/migration/migration.c
+++ b/migration/migration.c
@@ -2284,7 +2284,7 @@ static struct rp_cmd_args {
static void migrate_handle_rp_req_pages(MigrationState *ms, const char* rbname,
ram_addr_t start, size_t len)
{
- long our_host_ps = getpagesize();
+ long our_host_ps = qemu_real_host_page_size;
trace_migrate_handle_rp_req_pages(rbname, start, len);
diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c
index abccafc..a364027 100644
--- a/migration/postcopy-ram.c
+++ b/migration/postcopy-ram.c
@@ -308,7 +308,7 @@ static bool ufd_check_and_apply(int ufd, MigrationIncomingState *mis)
return false;
}
- if (getpagesize() != ram_pagesize_summary()) {
+ if (qemu_real_host_page_size != ram_pagesize_summary()) {
bool have_hp = false;
/* We've got a huge page */
#ifdef UFFD_FEATURE_MISSING_HUGETLBFS
@@ -346,7 +346,7 @@ static int test_ramblock_postcopiable(RAMBlock *rb, void *opaque)
*/
bool postcopy_ram_supported_by_host(MigrationIncomingState *mis)
{
- long pagesize = getpagesize();
+ long pagesize = qemu_real_host_page_size;
int ufd = -1;
bool ret = false; /* Error unless we change it */
void *testarea = NULL;
diff --git a/monitor/misc.c b/monitor/misc.c
index aef16f6..3baa15f 100644
--- a/monitor/misc.c
+++ b/monitor/misc.c
@@ -862,7 +862,7 @@ static uint64_t vtop(void *ptr, Error **errp)
uint64_t pinfo;
uint64_t ret = -1;
uintptr_t addr = (uintptr_t) ptr;
- uintptr_t pagesize = getpagesize();
+ uintptr_t pagesize = qemu_real_host_page_size;
off_t offset = addr / pagesize * sizeof(pinfo);
int fd;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 820724c..7d2e896 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -411,7 +411,7 @@ void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
* will be a normal mapping, not a special hugepage one used
* for RAM.
*/
- if (getpagesize() < 0x10000) {
+ if (qemu_real_host_page_size < 0x10000) {
error_setg(errp,
"KVM can't supply 64kiB CI pages, which guest expects");
}
diff --git a/tests/vhost-user-bridge.c b/tests/vhost-user-bridge.c
index c4e350e..6c3d490 100644
--- a/tests/vhost-user-bridge.c
+++ b/tests/vhost-user-bridge.c
@@ -468,8 +468,8 @@ vubr_queue_set_started(VuDev *dev, int qidx, bool started)
if (started && vubr->notifier.fd >= 0) {
vu_set_queue_host_notifier(dev, vq, vubr->notifier.fd,
- getpagesize(),
- qidx * getpagesize());
+ qemu_real_host_page_size,
+ qidx * qemu_real_host_page_size);
}
if (qidx % 2 == 1) {
@@ -594,7 +594,7 @@ static void *notifier_thread(void *arg)
{
VuDev *dev = (VuDev *)arg;
VubrDev *vubr = container_of(dev, VubrDev, vudev);
- int pagesize = getpagesize();
+ int pagesize = qemu_real_host_page_size;
int qidx;
while (true) {
@@ -630,7 +630,7 @@ vubr_host_notifier_setup(VubrDev *dev)
void *addr;
int fd;
- length = getpagesize() * VHOST_USER_BRIDGE_MAX_QUEUES;
+ length = qemu_real_host_page_size * VHOST_USER_BRIDGE_MAX_QUEUES;
fd = mkstemp(template);
if (fd < 0) {
diff --git a/util/mmap-alloc.c b/util/mmap-alloc.c
index f7f177d..27dcccd 100644
--- a/util/mmap-alloc.c
+++ b/util/mmap-alloc.c
@@ -48,7 +48,7 @@ size_t qemu_fd_getpagesize(int fd)
#endif
#endif
- return getpagesize();
+ return qemu_real_host_page_size;
}
size_t qemu_mempath_getpagesize(const char *mem_path)
@@ -79,7 +79,7 @@ size_t qemu_mempath_getpagesize(const char *mem_path)
#endif
#endif
- return getpagesize();
+ return qemu_real_host_page_size;
}
void *qemu_ram_mmap(int fd,
@@ -114,7 +114,7 @@ void *qemu_ram_mmap(int fd,
*/
flags = MAP_PRIVATE;
pagesize = qemu_fd_getpagesize(fd);
- if (fd == -1 || pagesize == getpagesize()) {
+ if (fd == -1 || pagesize == qemu_real_host_page_size) {
guardfd = -1;
flags |= MAP_ANONYMOUS;
} else {
@@ -123,7 +123,7 @@ void *qemu_ram_mmap(int fd,
}
#else
guardfd = -1;
- pagesize = getpagesize();
+ pagesize = qemu_real_host_page_size;
flags = MAP_PRIVATE | MAP_ANONYMOUS;
#endif
@@ -205,7 +205,7 @@ void qemu_ram_munmap(int fd, void *ptr, size_t size)
#if defined(__powerpc64__) && defined(__linux__)
pagesize = qemu_fd_getpagesize(fd);
#else
- pagesize = getpagesize();
+ pagesize = qemu_real_host_page_size;
#endif
munmap(ptr, size + pagesize);
}
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index f869338..5a291cc 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -617,7 +617,7 @@ void *qemu_alloc_stack(size_t *sz)
#ifdef CONFIG_DEBUG_STACK_USAGE
void *ptr2;
#endif
- size_t pagesz = getpagesize();
+ size_t pagesz = qemu_real_host_page_size;
#ifdef _SC_THREAD_STACK_MIN
/* avoid stacks smaller than _SC_THREAD_STACK_MIN */
long min_stack_sz = sysconf(_SC_THREAD_STACK_MIN);
@@ -679,7 +679,7 @@ void qemu_free_stack(void *stack, size_t sz)
unsigned int usage;
void *ptr;
- for (ptr = stack + getpagesize(); ptr < stack + sz;
+ for (ptr = stack + qemu_real_host_page_size; ptr < stack + sz;
ptr += sizeof(uint32_t)) {
if (*(uint32_t *)ptr != 0xdeadbeaf) {
break;
diff --git a/util/oslib-win32.c b/util/oslib-win32.c
index 886e400..e9b14ab 100644
--- a/util/oslib-win32.c
+++ b/util/oslib-win32.c
@@ -554,7 +554,7 @@ void os_mem_prealloc(int fd, char *area, size_t memory, int smp_cpus,
Error **errp)
{
int i;
- size_t pagesize = getpagesize();
+ size_t pagesize = qemu_real_host_page_size;
memory = (memory + pagesize - 1) & -pagesize;
for (i = 0; i < memory / pagesize; i++) {
diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
index 26ffd0d..813f7ec 100644
--- a/util/vfio-helpers.c
+++ b/util/vfio-helpers.c
@@ -514,9 +514,9 @@ static IOVAMapping *qemu_vfio_add_mapping(QEMUVFIOState *s,
IOVAMapping m = {.host = host, .size = size, .iova = iova};
IOVAMapping *insert;
- assert(QEMU_IS_ALIGNED(size, getpagesize()));
- assert(QEMU_IS_ALIGNED(s->low_water_mark, getpagesize()));
- assert(QEMU_IS_ALIGNED(s->high_water_mark, getpagesize()));
+ assert(QEMU_IS_ALIGNED(size, qemu_real_host_page_size));
+ assert(QEMU_IS_ALIGNED(s->low_water_mark, qemu_real_host_page_size));
+ assert(QEMU_IS_ALIGNED(s->high_water_mark, qemu_real_host_page_size));
trace_qemu_vfio_new_mapping(s, host, size, index, iova);
assert(index >= 0);
@@ -567,7 +567,7 @@ static void qemu_vfio_undo_mapping(QEMUVFIOState *s, IOVAMapping *mapping,
index = mapping - s->mappings;
assert(mapping->size > 0);
- assert(QEMU_IS_ALIGNED(mapping->size, getpagesize()));
+ assert(QEMU_IS_ALIGNED(mapping->size, qemu_real_host_page_size));
assert(index >= 0 && index < s->nr_mappings);
if (ioctl(s->container, VFIO_IOMMU_UNMAP_DMA, &unmap)) {
error_setg(errp, "VFIO_UNMAP_DMA failed: %d", -errno);
@@ -613,8 +613,8 @@ int qemu_vfio_dma_map(QEMUVFIOState *s, void *host, size_t size,
IOVAMapping *mapping;
uint64_t iova0;
- assert(QEMU_PTR_IS_ALIGNED(host, getpagesize()));
- assert(QEMU_IS_ALIGNED(size, getpagesize()));
+ assert(QEMU_PTR_IS_ALIGNED(host, qemu_real_host_page_size));
+ assert(QEMU_IS_ALIGNED(size, qemu_real_host_page_size));
trace_qemu_vfio_dma_map(s, host, size, temporary, iova);
qemu_mutex_lock(&s->lock);
mapping = qemu_vfio_find_mapping(s, host, &index);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 37/39] target/i386: move FERR handling to target/i386
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (35 preceding siblings ...)
2019-10-24 14:03 ` [PULL 36/39] core: replace getpagesize() with qemu_real_host_page_size Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 38/39] target/i386: introduce cpu_set_fpus Paolo Bonzini
` (3 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel
Move it out of pc.c since it is strictly tied to TCG. This is
almost exclusively code movement, the next patch will implement
IGNNE.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc.c | 17 +++--------------
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
include/hw/i386/pc.h | 1 -
target/i386/cpu.h | 3 ++-
target/i386/fpu_helper.c | 26 +++++++++++++++++++++++++-
6 files changed, 32 insertions(+), 19 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5fce60c..66d865b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -381,23 +381,12 @@ static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
}
/* MSDOS compatibility mode FPU exception support */
-static qemu_irq ferr_irq;
-
-void pc_register_ferr_irq(qemu_irq irq)
-{
- ferr_irq = irq;
-}
-
-/* XXX: add IGNNE support */
-void cpu_set_ferr(CPUX86State *s)
-{
- qemu_irq_raise(ferr_irq);
-}
-
static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
- qemu_irq_lower(ferr_irq);
+ if (tcg_enabled()) {
+ cpu_clear_ferr();
+ }
}
static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 3a4a64a..431d657 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -213,7 +213,7 @@ static void pc_init1(MachineState *machine,
ioapic_init_gsi(gsi_state, "i440fx");
}
- pc_register_ferr_irq(x86ms->gsi[13]);
+ x86_register_ferr_irq(x86ms->gsi[13]);
pc_vga_init(isa_bus, pcmc->pci_enabled ? pci_bus : NULL);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index def3bc2..c9cdac8 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -261,7 +261,7 @@ static void pc_q35_init(MachineState *machine)
ioapic_init_gsi(gsi_state, "q35");
}
- pc_register_ferr_irq(x86ms->gsi[13]);
+ x86_register_ferr_irq(x86ms->gsi[13]);
assert(pcms->vmport != ON_OFF_AUTO__MAX);
if (pcms->vmport == ON_OFF_AUTO_AUTO) {
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 5923318..f040a72 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -176,7 +176,6 @@ void vmmouse_set_data(const uint32_t *data);
extern int fd_bootchk;
bool pc_machine_is_smm_enabled(PCMachineState *pcms);
-void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index b772e82..01e052b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1761,7 +1761,8 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
-void cpu_set_ferr(CPUX86State *s);
+void x86_register_ferr_irq(qemu_irq irq);
+void cpu_clear_ferr(void);
/* mpx_helper.c */
void cpu_sync_bndcs_hflags(CPUX86State *env);
diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
index 005f1f6..4db0059 100644
--- a/target/i386/fpu_helper.c
+++ b/target/i386/fpu_helper.c
@@ -26,6 +26,10 @@
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
+#ifdef CONFIG_SOFTMMU
+#include "hw/irq.h"
+#endif
+
#define FPU_RC_MASK 0xc00
#define FPU_RC_NEAR 0x000
#define FPU_RC_DOWN 0x400
@@ -58,6 +62,26 @@
#define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
#define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
+#if !defined(CONFIG_USER_ONLY)
+static qemu_irq ferr_irq;
+
+void x86_register_ferr_irq(qemu_irq irq)
+{
+ ferr_irq = irq;
+}
+
+void cpu_clear_ferr(void)
+{
+ qemu_irq_lower(ferr_irq);
+}
+
+static void cpu_set_ferr(void)
+{
+ qemu_irq_raise(ferr_irq);
+}
+#endif
+
+
static inline void fpush(CPUX86State *env)
{
env->fpstt = (env->fpstt - 1) & 7;
@@ -137,7 +161,7 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
}
#if !defined(CONFIG_USER_ONLY)
else {
- cpu_set_ferr(env);
+ cpu_set_ferr();
}
#endif
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 38/39] target/i386: introduce cpu_set_fpus
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (36 preceding siblings ...)
2019-10-24 14:03 ` [PULL 37/39] target/i386: move FERR handling to target/i386 Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-24 14:03 ` [PULL 39/39] i386: implement IGNNE Paolo Bonzini
` (2 subsequent siblings)
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel
In the next patch, this will provide a hook to detect clearing of
FSW.ES.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/fpu_helper.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
index 4db0059..6825024 100644
--- a/target/i386/fpu_helper.c
+++ b/target/i386/fpu_helper.c
@@ -1053,6 +1053,12 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
do_fstenv(env, ptr, data32, GETPC());
}
+static void cpu_set_fpus(CPUX86State *env, uint16_t fpus)
+{
+ env->fpstt = (fpus >> 11) & 7;
+ env->fpus = fpus & ~0x3800;
+}
+
static void do_fldenv(CPUX86State *env, target_ulong ptr, int data32,
uintptr_t retaddr)
{
@@ -1067,8 +1073,7 @@ static void do_fldenv(CPUX86State *env, target_ulong ptr, int data32,
fpus = cpu_lduw_data_ra(env, ptr + 2, retaddr);
fptag = cpu_lduw_data_ra(env, ptr + 4, retaddr);
}
- env->fpstt = (fpus >> 11) & 7;
- env->fpus = fpus & ~0x3800;
+ cpu_set_fpus(env, fpus);
for (i = 0; i < 8; i++) {
env->fptags[i] = ((fptag & 3) == 3);
fptag >>= 2;
@@ -1316,8 +1321,7 @@ static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
fpus = cpu_lduw_data_ra(env, ptr + XO(legacy.fsw), ra);
fptag = cpu_lduw_data_ra(env, ptr + XO(legacy.ftw), ra);
cpu_set_fpuc(env, fpuc);
- env->fpstt = (fpus >> 11) & 7;
- env->fpus = fpus & ~0x3800;
+ cpu_set_fpus(env, fpus);
fptag ^= 0xff;
for (i = 0; i < 8; i++) {
env->fptags[i] = ((fptag >> i) & 1);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* [PULL 39/39] i386: implement IGNNE
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (37 preceding siblings ...)
2019-10-24 14:03 ` [PULL 38/39] target/i386: introduce cpu_set_fpus Paolo Bonzini
@ 2019-10-24 14:03 ` Paolo Bonzini
2019-10-25 8:43 ` [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 no-reply
2019-10-25 10:46 ` Peter Maydell
40 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-24 14:03 UTC (permalink / raw)
To: qemu-devel
Change the handling of port F0h writes and FPU exceptions to implement IGNNE.
The implementation mixes a bit what the chipset and processor do in real
hardware, but the effect is the same as what happens with actual FERR#
and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering
FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc.c | 2 +-
target/i386/cpu.h | 4 +++-
target/i386/fpu_helper.c | 34 +++++++++++++++++++++++++++-------
3 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 66d865b..174b0bd 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -385,7 +385,7 @@ static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
if (tcg_enabled()) {
- cpu_clear_ferr();
+ cpu_set_ignne();
}
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 01e052b..5352c9f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -203,6 +203,7 @@ typedef enum X86Seg {
#define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
#define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
#define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
+#define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
@@ -211,6 +212,7 @@ typedef enum X86Seg {
#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
#define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
+#define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
#define CR0_PE_SHIFT 0
#define CR0_MP_SHIFT 1
@@ -1762,7 +1764,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void x86_register_ferr_irq(qemu_irq irq);
-void cpu_clear_ferr(void);
+void cpu_set_ignne(void);
/* mpx_helper.c */
void cpu_sync_bndcs_hflags(CPUX86State *env);
diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
index 6825024..99f28f2 100644
--- a/target/i386/fpu_helper.c
+++ b/target/i386/fpu_helper.c
@@ -70,14 +70,24 @@ void x86_register_ferr_irq(qemu_irq irq)
ferr_irq = irq;
}
-void cpu_clear_ferr(void)
+static void cpu_clear_ignne(void)
{
- qemu_irq_lower(ferr_irq);
+ CPUX86State *env = &X86_CPU(first_cpu)->env;
+ env->hflags2 &= ~HF2_IGNNE_MASK;
}
-static void cpu_set_ferr(void)
+void cpu_set_ignne(void)
{
- qemu_irq_raise(ferr_irq);
+ CPUX86State *env = &X86_CPU(first_cpu)->env;
+ env->hflags2 |= HF2_IGNNE_MASK;
+ /*
+ * We get here in response to a write to port F0h. The chipset should
+ * deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
+ * cleared, because FERR# and FP_IRQ are two separate pins on real
+ * hardware. However, we don't model FERR# as a qemu_irq, so we just
+ * do directly what the chipset would do, i.e. deassert FP_IRQ.
+ */
+ qemu_irq_lower(ferr_irq);
}
#endif
@@ -160,8 +170,8 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
raise_exception_ra(env, EXCP10_COPR, retaddr);
}
#if !defined(CONFIG_USER_ONLY)
- else {
- cpu_set_ferr();
+ else if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
+ qemu_irq_raise(ferr_irq);
}
#endif
}
@@ -1056,7 +1066,17 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
static void cpu_set_fpus(CPUX86State *env, uint16_t fpus)
{
env->fpstt = (fpus >> 11) & 7;
- env->fpus = fpus & ~0x3800;
+ env->fpus = fpus & ~0x3800 & ~FPUS_B;
+ env->fpus |= env->fpus & FPUS_SE ? FPUS_B : 0;
+#if !defined(CONFIG_USER_ONLY)
+ if (!(env->fpus & FPUS_SE)) {
+ /*
+ * Here the processor deasserts FERR#; in response, the chipset deasserts
+ * IGNNE#.
+ */
+ cpu_clear_ignne();
+ }
+#endif
}
static void do_fldenv(CPUX86State *env, target_ulong ptr, int data32,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (38 preceding siblings ...)
2019-10-24 14:03 ` [PULL 39/39] i386: implement IGNNE Paolo Bonzini
@ 2019-10-25 8:43 ` no-reply
2019-10-25 10:46 ` Peter Maydell
40 siblings, 0 replies; 51+ messages in thread
From: no-reply @ 2019-10-25 8:43 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/1571925835-31930-1-git-send-email-pbonzini@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
Type: series
Message-id: 1571925835-31930-1-git-send-email-pbonzini@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
4f4f906 i386: implement IGNNE
d2fd259 target/i386: introduce cpu_set_fpus
52ffa84 target/i386: move FERR handling to target/i386
6ab413e core: replace getpagesize() with qemu_real_host_page_size
b11b965 audio: fix missing break
6d328cf mc146818rtc: always register rtc to rtc list
2dee65a mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c
4950ef7 mc146818rtc: Move RTC_ISA_IRQ definition
a020047 mc146818rtc: move structure to header file
43bb622 hw/i386/pc: Remove kvm_i386.h include
435f326 hw/i386/pc: Extract pc_i8259_create()
75cc1a0 hw/i386/pc: Move gsi_state creation code
c130e98 hw/i386/pc: Extract pc_gsi_create()
ed6079c target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR
a1cf070 x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE
175fcf8 hw/timer/mc146818rtc: Only include qapi-commands-misc on I386
8cb9887 runstate: ignore exit request in finish migrate state
ccabb3b checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE)
a790c48 MAINTAINERS: add microvm related files
5581800 hw/i386: Introduce the microvm machine type
f069a21 docs/microvm.rst: document the new microvm machine type
12fc113 roms: add microvm-bios (qboot) as binary and git submodule
7616d00 hw/intc/apic: reject pic ints if isa_pic == NULL
7610afb fw_cfg: add "modify" functions for all types
b02e61c hw/i386: make x86.c independent from PCMachineState
06ab7d0 hw/i386: split PCMachineState deriving X86MachineState from it
c6d1465 hw/i386/pc: move shared x86 functions to x86.c and export them
efb2fb8 hw/i386/pc: remove commented out code from x86_load_linux()
7ca3f4d hw/i386/pc: avoid an assignment in if condition in x86_load_linux()
76f87f6 hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux()
2b1d644 hw/i386/pc: fix code style issues on functions that will be moved out
5cf9b30 hw/i386/pc: rename functions shared with non-PC machines
342ded8 hw/virtio: Factorize virtio-mmio headers
9fcf46c memory-device: simplify Makefile.objs conditions
b9e7378 Do not use %m in common code to print error messages
165f7c9 i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenment
69ba817 Updated Bulgarian translation (19) - 4.1.0
5fb33e9 mc146818rtc: fix timer interrupt reinjection
d56989d target/i386: log MCE guest and host addresses
=== OUTPUT BEGIN ===
1/39 Checking commit d56989d83eb2 (target/i386: log MCE guest and host addresses)
2/39 Checking commit 5fb33e988fbe (mc146818rtc: fix timer interrupt reinjection)
3/39 Checking commit 69ba817e6717 (Updated Bulgarian translation (19) - 4.1.0)
4/39 Checking commit 165f7c93fe47 (i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenment)
5/39 Checking commit b9e737803b9a (Do not use %m in common code to print error messages)
6/39 Checking commit 9fcf46c30b49 (memory-device: simplify Makefile.objs conditions)
7/39 Checking commit 342ded81f836 (hw/virtio: Factorize virtio-mmio headers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#80:
new file mode 100644
total: 0 errors, 1 warnings, 131 lines checked
Patch 7/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/39 Checking commit 5cf9b30de456 (hw/i386/pc: rename functions shared with non-PC machines)
9/39 Checking commit 2b1d64422081 (hw/i386/pc: fix code style issues on functions that will be moved out)
10/39 Checking commit 76f87f6ca7d9 (hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux())
11/39 Checking commit 7ca3f4d5c4cc (hw/i386/pc: avoid an assignment in if condition in x86_load_linux())
12/39 Checking commit efb2fb89cbde (hw/i386/pc: remove commented out code from x86_load_linux())
13/39 Checking commit c6d14657ad32 (hw/i386/pc: move shared x86 functions to x86.c and export them)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#767:
new file mode 100644
total: 0 errors, 1 warnings, 1449 lines checked
Patch 13/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/39 Checking commit 06ab7d08e59d (hw/i386: split PCMachineState deriving X86MachineState from it)
15/39 Checking commit b02e61c98802 (hw/i386: make x86.c independent from PCMachineState)
16/39 Checking commit 7610afb385a7 (fw_cfg: add "modify" functions for all types)
17/39 Checking commit 7616d00f9fe2 (hw/intc/apic: reject pic ints if isa_pic == NULL)
18/39 Checking commit 12fc113d9d76 (roms: add microvm-bios (qboot) as binary and git submodule)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 28 lines checked
Patch 18/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/39 Checking commit f069a218c30a (docs/microvm.rst: document the new microvm machine type)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 108 lines checked
Patch 19/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/39 Checking commit 5581800c1da8 (hw/i386: Introduce the microvm machine type)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#62:
new file mode 100644
total: 0 errors, 1 warnings, 670 lines checked
Patch 20/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/39 Checking commit a790c48b0f93 (MAINTAINERS: add microvm related files)
22/39 Checking commit ccabb3bb815b (checkpatch: suggest qemu_real_host_page_size instead of getpagesize() or sysconf(_SC_PAGESIZE))
ERROR: line over 90 characters
#26: FILE: scripts/checkpatch.pl:2919:
+ ERROR("use qemu_real_host_page_size instead of getpagesize()\n" . $herecurr);
ERROR: line over 90 characters
#29: FILE: scripts/checkpatch.pl:2922:
+ ERROR("use qemu_real_host_page_size instead of sysconf(_SC_PAGESIZE)\n" . $herecurr);
total: 2 errors, 0 warnings, 12 lines checked
Patch 22/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/39 Checking commit 8cb98874af80 (runstate: ignore exit request in finish migrate state)
24/39 Checking commit 175fcf87450d (hw/timer/mc146818rtc: Only include qapi-commands-misc on I386)
25/39 Checking commit a1cf0708ef9d (x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE)
WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/i386/cpu.c:1061:
+ NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
total: 0 errors, 1 warnings, 28 lines checked
Patch 25/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/39 Checking commit ed6079c493d0 (target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR)
27/39 Checking commit c130e98ab1fd (hw/i386/pc: Extract pc_gsi_create())
28/39 Checking commit 75cc1a087bb6 (hw/i386/pc: Move gsi_state creation code)
29/39 Checking commit 435f326bf1bd (hw/i386/pc: Extract pc_i8259_create())
30/39 Checking commit 43bb6226ffe3 (hw/i386/pc: Remove kvm_i386.h include)
31/39 Checking commit a02004740c2b (mc146818rtc: move structure to header file)
32/39 Checking commit 4950ef7063d6 (mc146818rtc: Move RTC_ISA_IRQ definition)
33/39 Checking commit 2dee65acb4d0 (mc146818rtc: Include mc146818rtc_regs.h directly in mc146818rtc.c)
34/39 Checking commit 6d328cf20bb3 (mc146818rtc: always register rtc to rtc list)
35/39 Checking commit b11b96565a6b (audio: fix missing break)
36/39 Checking commit 6ab413ef38d9 (core: replace getpagesize() with qemu_real_host_page_size)
37/39 Checking commit 52ffa842a569 (target/i386: move FERR handling to target/i386)
38/39 Checking commit d2fd2595f5e5 (target/i386: introduce cpu_set_fpus)
39/39 Checking commit 4f4f9069846a (i386: implement IGNNE)
WARNING: line over 80 characters
#113: FILE: target/i386/fpu_helper.c:1074:
+ * Here the processor deasserts FERR#; in response, the chipset deasserts
total: 0 errors, 1 warnings, 86 lines checked
Patch 39/39 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1571925835-31930-1-git-send-email-pbonzini@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
2019-10-24 14:03 [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 Paolo Bonzini
` (39 preceding siblings ...)
2019-10-25 8:43 ` [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 no-reply
@ 2019-10-25 10:46 ` Peter Maydell
2019-10-25 11:17 ` Paolo Bonzini
40 siblings, 1 reply; 51+ messages in thread
From: Peter Maydell @ 2019-10-25 10:46 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers
On Thu, 24 Oct 2019 at 15:21, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> The following changes since commit e9d42461920f6f40f4d847a5ba18e90d095ed0b9:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/audio-20191018-pull-request' into staging (2019-10-18 14:13:11 +0100)
>
> are available in the git repository at:
>
>
> git://github.com/bonzini/qemu.git tags/for-upstream
>
> for you to fetch changes up to a263f81cb4b302eb392898bdc4ad4381e1961629:
>
> i386: implement IGNNE (2019-10-24 16:02:04 +0200)
>
> ----------------------------------------------------------------
> * Bulgarian translation update (Alexander)
> * RTC and PC refactorings (Hervé, Philippe, Sergio)
> * RTC fix (Marcelo)
> * More comprehensive MCE logging (Mario)
> * x86 IGNNE implementation (Paolo)
> * Microvm machine type (Sergio)
> * Support for UMONITOR/UMWAIT/TPAUSE (Tao)
> * Do not use %m in common code (Thomas)
> * NoNonArchitecturalCoreSharing Hyper-V enlightenment (Vitaly)
> * getpagesize cleanups (Wei)
>
I got a link failure building the --disable-tcg config on x86-64:
LINK x86_64-softmmu/qemu-system-x86_64
hw/i386/pc_piix.o: In function `pc_init1':
/home/petmay01/linaro/qemu-for-merges/hw/i386/pc_piix.c:216: undefined
reference to `x86_register_ferr_irq'
hw/i386/pc_q35.o: In function `pc_q35_init':
/home/petmay01/linaro/qemu-for-merges/hw/i386/pc_q35.c:264: undefined
reference to `x86_register_ferr_irq'
collect2: error: ld returned 1 exit status
Makefile:206: recipe for target 'qemu-system-x86_64' failed
make[1]: *** [qemu-system-x86_64] Error 1
Makefile:482: recipe for target 'x86_64-softmmu/all' failed
make: *** [x86_64-softmmu/all] Error 2
make: *** Waiting for unfinished jobs....
LINK i386-softmmu/qemu-system-i386
hw/i386/pc_piix.o: In function `pc_init1':
/home/petmay01/linaro/qemu-for-merges/hw/i386/pc_piix.c:216: undefined
reference to `x86_register_ferr_irq'
hw/i386/pc_q35.o: In function `pc_q35_init':
/home/petmay01/linaro/qemu-for-merges/hw/i386/pc_q35.c:264: undefined
reference to `x86_register_ferr_irq'
collect2: error: ld returned 1 exit status
x86_register_ferr_irq() is defined in target/i386/fpu_helper.c,
which is only built if CONFIG_TCG, but the callers don't
seem to be similarly guarded and there's no stub fallback.
thanks
-- PMM
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
2019-10-25 10:46 ` Peter Maydell
@ 2019-10-25 11:17 ` Paolo Bonzini
2019-10-26 13:20 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-25 11:17 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 25/10/19 12:46, Peter Maydell wrote:
>
> x86_register_ferr_irq() is defined in target/i386/fpu_helper.c,
> which is only built if CONFIG_TCG, but the callers don't
> seem to be similarly guarded and there's no stub fallback.
Indeed, thanks. I'll add an "if (tcg_enabled())" since this feature is
not supported by accelerators other than TCG.
Paolo
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
2019-10-25 11:17 ` Paolo Bonzini
@ 2019-10-26 13:20 ` Philippe Mathieu-Daudé
2019-10-26 13:39 ` Paolo Bonzini
0 siblings, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-26 13:20 UTC (permalink / raw)
To: Paolo Bonzini, Peter Maydell; +Cc: QEMU Developers
On 10/25/19 1:17 PM, Paolo Bonzini wrote:
> On 25/10/19 12:46, Peter Maydell wrote:
>>
>> x86_register_ferr_irq() is defined in target/i386/fpu_helper.c,
>> which is only built if CONFIG_TCG, but the callers don't
>> seem to be similarly guarded and there's no stub fallback.
>
> Indeed, thanks. I'll add an "if (tcg_enabled())" since this feature is
> not supported by accelerators other than TCG.
Paolo, since the "Split timer <-> rtc" series got merged via
the trivial tree, you need to squash this fix to patch #33
("mc146818rtc: Include mc146818rtc_regs.h directly in
mc146818rtc.c") to avoid build failure:
-- >8 --
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index bbe6783898..9f5dd47fb6 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -42,7 +42,7 @@
#include "qapi/qapi-events-misc-target.h"
#include "qapi/visitor.h"
#include "exec/address-spaces.h"
-#include "hw/timer/mc146818rtc_regs.h"
+#include "hw/rtc/mc146818rtc_regs.h"
#ifdef TARGET_I386
#include "hw/i386/apic.h"
---
Regards,
Phil.
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24
2019-10-26 13:20 ` Philippe Mathieu-Daudé
@ 2019-10-26 13:39 ` Paolo Bonzini
0 siblings, 0 replies; 51+ messages in thread
From: Paolo Bonzini @ 2019-10-26 13:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell; +Cc: QEMU Developers
On 26/10/19 15:20, Philippe Mathieu-Daudé wrote:
> On 10/25/19 1:17 PM, Paolo Bonzini wrote:
>> On 25/10/19 12:46, Peter Maydell wrote:
>>>
>>> x86_register_ferr_irq() is defined in target/i386/fpu_helper.c,
>>> which is only built if CONFIG_TCG, but the callers don't
>>> seem to be similarly guarded and there's no stub fallback.
>>
>> Indeed, thanks. I'll add an "if (tcg_enabled())" since this feature is
>> not supported by accelerators other than TCG.
>
> Paolo, since the "Split timer <-> rtc" series got merged via
> the trivial tree, you need to squash this fix to patch #33
> ("mc146818rtc: Include mc146818rtc_regs.h directly in
> mc146818rtc.c") to avoid build failure:
There are a couple other semantic conflicts, so I pushed again the tag.
Paolo
^ permalink raw reply [flat|nested] 51+ messages in thread