Re: [PULL 00/52] target-arm queue

[no-reply@patchew.org]

Patchew URL: https://patchew.org/QEMU/20200221130740.7583-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/52] target-arm queue
Message-id: 20200221130740.7583-1-peter.maydell@linaro.org
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   9e6b7f7..a8c6af6  master     -> master
 - [tag update]      patchew/20200214181547.21408-1-richard.henderson@linaro.org -> patchew/20200214181547.21408-1-richard.henderson@linaro.org
Switched to a new branch 'test'
e716b40 target/arm: Add missing checks for fpsp_v2
924bed9 target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
bcd9a95 target/arm: Perform fpdp_v2 check first
a08e2dc target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
ad3b265 target/arm: Rename isar_feature_aa32_fpdp_v2
2fc4bdd target/arm: Add isar_feature_aa32_simd_r16
fd6938b target/arm: Set MVFR0.FPSP for ARMv5 cpus
273e47a target/arm: Use isar_feature_aa32_simd_r32 more places
039819a target/arm: Rename isar_feature_aa32_simd_r32
823de8a sh4: Fix PCI ISA IO memory subregion
7544091 xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
dc4a7d1 target/arm: Convert PMULL.8 to gvec
c374ce3 target/arm: Convert PMULL.64 to gvec
2d2c396 target/arm: Convert PMUL.8 to gvec
d342964 target/arm: Vectorize USHL and SSHL
0063cd4 arm: allwinner: Wire up USB ports
b9e2884 hcd-ehci: Introduce "companion-enable" sysbus property
b574708 hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
ba6d43e target/arm: Correctly implement ACTLR2, HACTLR2
8e7a24e target/arm: Use FIELD_EX32 for testing 32-bit fields
85a3af5 target/arm: Use isar_feature function for testing AA32HPD feature
defa532 target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
66e3ef9 target/arm: Correct handling of PMCR_EL0.LC bit
862d8f4 target/arm: Correct definition of PMCRDP
3110f17 target/arm: Provide ARMv8.4-PMU in '-cpu max'
615c8f2 target/arm: Implement ARMv8.4-PMU extension
ed42118 target/arm: Implement ARMv8.1-PMU extension
48085b2 target/arm: Read debug-related ID registers from KVM
73d3d09 target/arm: Move DBGDIDR into ARMISARegisters
ea2b0e0 target/arm: Stop assuming DBGDIDR always exists
8864a36 target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
1aa7d60 target/arm: Define an aa32_pmu_8_1 isar feature test function
4a89e29 target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
1b01268 target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
fd7a65d target/arm: Factor out PMU register definitions
948e94f target/arm: Define and use any_predinv isar_feature test
d22e85e target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
863b6af target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
2bc50d3 target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
9eaceb5 target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
64aabef target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
4aae1d9 target/arm: Fix select for aa64_va_parameters_both
d9df3db target/arm: Use bit 55 explicitly for pauth
eb77dd7 target/arm: Flush high bits of sve register after AdvSIMD INS
15daed9 target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
627f05d target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
2552311 target/arm: Flush high bits of sve register after AdvSIMD EXT
2f9b229 z2: Make providing flash images non-mandatory
5597d60 mainstone: Make providing flash images non-mandatory
6e7770a hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
146f767 aspeed/scu: Implement chip ID register
17234bd aspeed/scu: Create separate write callbacks

=== OUTPUT BEGIN ===
1/52 Checking commit 17234bd36e95 (aspeed/scu: Create separate write callbacks)
2/52 Checking commit 146f7678f210 (aspeed/scu: Implement chip ID register)
3/52 Checking commit 6e7770a44c0d (hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register)
4/52 Checking commit 5597d60507da (mainstone: Make providing flash images non-mandatory)
5/52 Checking commit 2f9b229b8d1a (z2: Make providing flash images non-mandatory)
6/52 Checking commit 25523116e604 (target/arm: Flush high bits of sve register after AdvSIMD EXT)
7/52 Checking commit 627f05d53988 (target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX)
8/52 Checking commit 15daed9afadb (target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN)
9/52 Checking commit eb77dd70ad05 (target/arm: Flush high bits of sve register after AdvSIMD INS)
10/52 Checking commit d9df3db397d1 (target/arm: Use bit 55 explicitly for pauth)
11/52 Checking commit 4aae1d9d4919 (target/arm: Fix select for aa64_va_parameters_both)
12/52 Checking commit 64aabef54dd9 (target/arm: Remove ttbr1_valid check from get_phys_addr_lpae)
13/52 Checking commit 9eaceb539af1 (target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid)
14/52 Checking commit 2bc50d3a46d4 (target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers)
15/52 Checking commit 863b6af89ec2 (target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan)
16/52 Checking commit d22e85eb3758 (target/arm: Add isar_feature_any_fp16 and document naming/usage conventions)
17/52 Checking commit 948e94f753bf (target/arm: Define and use any_predinv isar_feature test)
18/52 Checking commit fd7a65dbfcae (target/arm: Factor out PMU register definitions)
19/52 Checking commit 1b01268db2b5 (target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1)
20/52 Checking commit 4a89e2989293 (target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field)
21/52 Checking commit 1aa7d60b6837 (target/arm: Define an aa32_pmu_8_1 isar feature test function)
22/52 Checking commit 8864a36c93a3 (target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks)
23/52 Checking commit ea2b0e008e90 (target/arm: Stop assuming DBGDIDR always exists)
24/52 Checking commit 73d3d09830da (target/arm: Move DBGDIDR into ARMISARegisters)
25/52 Checking commit 48085b2a44cb (target/arm: Read debug-related ID registers from KVM)
26/52 Checking commit ed421180995c (target/arm: Implement ARMv8.1-PMU extension)
27/52 Checking commit 615c8f2328f2 (target/arm: Implement ARMv8.4-PMU extension)
28/52 Checking commit 3110f175dfe2 (target/arm: Provide ARMv8.4-PMU in '-cpu max')
29/52 Checking commit 862d8f40b3e2 (target/arm: Correct definition of PMCRDP)
30/52 Checking commit 66e3ef905a8a (target/arm: Correct handling of PMCR_EL0.LC bit)
31/52 Checking commit defa532fa8a4 (target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks)
32/52 Checking commit 85a3af51a4f5 (target/arm: Use isar_feature function for testing AA32HPD feature)
33/52 Checking commit 8e7a24e8c248 (target/arm: Use FIELD_EX32 for testing 32-bit fields)
34/52 Checking commit ba6d43eeda80 (target/arm: Correctly implement ACTLR2, HACTLR2)
35/52 Checking commit b57470806773 (hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file)
36/52 Checking commit b9e28848bb19 (hcd-ehci: Introduce "companion-enable" sysbus property)
37/52 Checking commit 0063cd460d72 (arm: allwinner: Wire up USB ports)
38/52 Checking commit d342964f9893 (target/arm: Vectorize USHL and SSHL)
ERROR: trailing statements should be on next line
#163: FILE: target/arm/translate.c:3578:
+            case 2: gen_ushl_i32(var, var, shift); break;

ERROR: trailing statements should be on next line
#170: FILE: target/arm/translate.c:3584:
+            case 2: gen_sshl_i32(var, var, shift); break;

total: 2 errors, 0 warnings, 569 lines checked

Patch 38/52 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

39/52 Checking commit 2d2c396c7f84 (target/arm: Convert PMUL.8 to gvec)
40/52 Checking commit c374ce3197d8 (target/arm: Convert PMULL.64 to gvec)
41/52 Checking commit dc4a7d18ff35 (target/arm: Convert PMULL.8 to gvec)
42/52 Checking commit 7544091df58a (xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd)
43/52 Checking commit 823de8afd249 (sh4: Fix PCI ISA IO memory subregion)
44/52 Checking commit 039819a29015 (target/arm: Rename isar_feature_aa32_simd_r32)
45/52 Checking commit 273e47a45b06 (target/arm: Use isar_feature_aa32_simd_r32 more places)
46/52 Checking commit fd6938b475f0 (target/arm: Set MVFR0.FPSP for ARMv5 cpus)
47/52 Checking commit 2fc4bdd16fc7 (target/arm: Add isar_feature_aa32_simd_r16)
48/52 Checking commit ad3b265cccf5 (target/arm: Rename isar_feature_aa32_fpdp_v2)
49/52 Checking commit a08e2dc02fe3 (target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3})
50/52 Checking commit bcd9a95a316c (target/arm: Perform fpdp_v2 check first)
51/52 Checking commit 924bed926a5c (target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3)
52/52 Checking commit e716b403b38b (target/arm: Add missing checks for fpsp_v2)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200221130740.7583-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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