From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/52] aspeed/scu: Create separate write callbacks
Date: Fri, 21 Feb 2020 13:06:49 +0000 [thread overview]
Message-ID: <20200221130740.7583-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org>
From: Joel Stanley <joel@jms.id.au>
This splits the common write callback into separate ast2400 and ast2500
implementations. This makes it clearer when implementing differing
behaviour.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200121013302.43839-2-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/aspeed_scu.c | 80 +++++++++++++++++++++++++++++++-------------
1 file changed, 57 insertions(+), 23 deletions(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ce2f9562d4c..6cb388330a8 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -232,8 +232,47 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
return s->regs[reg];
}
-static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
- unsigned size)
+static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ASPEED_SCU_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
+ !s->regs[PROT_KEY]) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
+ }
+
+ trace_aspeed_scu_write(offset, size, data);
+
+ switch (reg) {
+ case PROT_KEY:
+ s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
+ return;
+ case SILICON_REV:
+ case FREQ_CNTR_EVAL:
+ case VGA_SCRATCH1 ... VGA_SCRATCH8:
+ case RNG_DATA:
+ case FREE_CNTR4:
+ case FREE_CNTR4_EXT:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ s->regs[reg] = data;
+}
+
+static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
+ uint64_t data, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
int reg = TO_REG(offset);
@@ -257,25 +296,11 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
case PROT_KEY:
s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
return;
- case CLK_SEL:
- s->regs[reg] = data;
- break;
case HW_STRAP1:
- if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
- s->regs[HW_STRAP1] |= data;
- return;
- }
- /* Jump to assignment below */
- break;
+ s->regs[HW_STRAP1] |= data;
+ return;
case SILICON_REV:
- if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
- s->regs[HW_STRAP1] &= ~data;
- } else {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
- __func__, offset);
- }
- /* Avoid assignment below, we've handled everything */
+ s->regs[HW_STRAP1] &= ~data;
return;
case FREQ_CNTR_EVAL:
case VGA_SCRATCH1 ... VGA_SCRATCH8:
@@ -291,9 +316,18 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
s->regs[reg] = data;
}
-static const MemoryRegionOps aspeed_scu_ops = {
+static const MemoryRegionOps aspeed_ast2400_scu_ops = {
.read = aspeed_scu_read,
- .write = aspeed_scu_write,
+ .write = aspeed_ast2400_scu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static const MemoryRegionOps aspeed_ast2500_scu_ops = {
+ .read = aspeed_scu_read,
+ .write = aspeed_ast2500_scu_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
@@ -469,7 +503,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
asc->calc_hpll = aspeed_2400_scu_calc_hpll;
asc->apb_divider = 2;
asc->nr_regs = ASPEED_SCU_NR_REGS;
- asc->ops = &aspeed_scu_ops;
+ asc->ops = &aspeed_ast2400_scu_ops;
}
static const TypeInfo aspeed_2400_scu_info = {
@@ -489,7 +523,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
asc->calc_hpll = aspeed_2500_scu_calc_hpll;
asc->apb_divider = 4;
asc->nr_regs = ASPEED_SCU_NR_REGS;
- asc->ops = &aspeed_scu_ops;
+ asc->ops = &aspeed_ast2500_scu_ops;
}
static const TypeInfo aspeed_2500_scu_info = {
--
2.20.1
next prev parent reply other threads:[~2020-02-21 13:08 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 13:06 [PULL 00/52] target-arm queue Peter Maydell
2020-02-21 13:06 ` Peter Maydell [this message]
2020-02-21 13:06 ` [PULL 02/52] aspeed/scu: Implement chip ID register Peter Maydell
2020-02-21 13:06 ` [PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register Peter Maydell
2020-02-21 13:06 ` [PULL 04/52] mainstone: Make providing flash images non-mandatory Peter Maydell
2020-02-21 13:06 ` [PULL 05/52] z2: " Peter Maydell
2020-02-21 13:06 ` [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT Peter Maydell
2020-02-21 13:06 ` [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Peter Maydell
2020-02-21 13:06 ` [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Peter Maydell
2020-02-21 13:06 ` [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS Peter Maydell
2020-02-21 13:06 ` [PULL 10/52] target/arm: Use bit 55 explicitly for pauth Peter Maydell
2020-02-21 13:06 ` [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both Peter Maydell
2020-02-21 13:07 ` [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae Peter Maydell
2020-02-21 13:07 ` [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid Peter Maydell
2020-02-21 13:07 ` [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
2020-02-21 13:07 ` [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Peter Maydell
2020-02-21 13:07 ` [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Peter Maydell
2020-02-21 13:07 ` [PULL 17/52] target/arm: Define and use any_predinv isar_feature test Peter Maydell
2020-02-21 13:07 ` [PULL 18/52] target/arm: Factor out PMU register definitions Peter Maydell
2020-02-21 13:07 ` [PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Peter Maydell
2020-02-21 13:07 ` [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Peter Maydell
2020-02-21 13:07 ` [PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function Peter Maydell
2020-02-21 13:07 ` [PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Peter Maydell
2020-02-21 13:07 ` [PULL 23/52] target/arm: Stop assuming DBGDIDR always exists Peter Maydell
2020-02-21 13:07 ` [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters Peter Maydell
2020-02-21 13:07 ` [PULL 25/52] target/arm: Read debug-related ID registers from KVM Peter Maydell
2020-02-21 13:07 ` [PULL 26/52] target/arm: Implement ARMv8.1-PMU extension Peter Maydell
2020-02-21 13:07 ` [PULL 27/52] target/arm: Implement ARMv8.4-PMU extension Peter Maydell
2020-02-21 13:07 ` [PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max' Peter Maydell
2020-02-21 13:07 ` [PULL 29/52] target/arm: Correct definition of PMCRDP Peter Maydell
2020-02-21 13:07 ` [PULL 30/52] target/arm: Correct handling of PMCR_EL0.LC bit Peter Maydell
2020-02-21 13:07 ` [PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Peter Maydell
2020-02-21 13:07 ` [PULL 32/52] target/arm: Use isar_feature function for testing AA32HPD feature Peter Maydell
2020-02-21 13:07 ` [PULL 33/52] target/arm: Use FIELD_EX32 for testing 32-bit fields Peter Maydell
2020-02-21 13:07 ` [PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2 Peter Maydell
2020-02-21 13:07 ` [PULL 35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file Peter Maydell
2020-02-21 13:07 ` [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property Peter Maydell
2020-02-21 13:07 ` [PULL 37/52] arm: allwinner: Wire up USB ports Peter Maydell
2020-02-21 13:07 ` [PULL 38/52] target/arm: Vectorize USHL and SSHL Peter Maydell
2020-02-21 13:07 ` [PULL 39/52] target/arm: Convert PMUL.8 to gvec Peter Maydell
2020-02-21 13:07 ` [PULL 40/52] target/arm: Convert PMULL.64 " Peter Maydell
2020-02-21 13:07 ` [PULL 41/52] target/arm: Convert PMULL.8 " Peter Maydell
2020-02-21 13:07 ` [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd Peter Maydell
2020-02-21 13:07 ` [PULL 43/52] sh4: Fix PCI ISA IO memory subregion Peter Maydell
2020-02-21 13:07 ` [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32 Peter Maydell
2020-02-21 13:07 ` [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places Peter Maydell
2020-02-21 13:07 ` [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus Peter Maydell
2020-02-21 13:07 ` [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16 Peter Maydell
2020-02-21 13:07 ` [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
2020-02-21 13:07 ` [PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
2020-02-21 13:07 ` [PULL 50/52] target/arm: Perform fpdp_v2 check first Peter Maydell
2020-02-21 13:07 ` [PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
2020-02-21 13:07 ` [PULL 52/52] target/arm: Add missing checks for fpsp_v2 Peter Maydell
2020-02-21 14:17 ` [PULL 00/52] target-arm queue no-reply
2020-02-21 16:06 ` no-reply
2020-02-21 16:10 ` no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200221130740.7583-2-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).