* [PATCH v3 0/3] Fix number of priority bits for arm boards
@ 2020-02-24 9:39 Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 1/3] arm_gic: Mask the un-supported priority bits Sai Pavan Boddu
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Sai Pavan Boddu @ 2020-02-24 9:39 UTC (permalink / raw)
To: Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Anthony Liguori, afaerber
Cc: qemu-arm, qemu-devel
This patch series implements the mask for unimplemented priority bits in
arm-gic. Which will return the expected number of priority bits on read.
Changes for V2:
Followed gicv3 code for defining mask for unimplemented bits
Hardcoded num priority bits for A9 and ARM11MPCore boards
Changes for V3:
Fixed the code as suggested in V1.
Implemented checks for max and min priority bits.
Sai Pavan Boddu (3):
arm_gic: Mask the un-supported priority bits
cpu/a9mpcore: Set number of GIC priority bits to 5
cpu/arm11mpcore: Set number of GIC priority bits to 4
hw/cpu/a9mpcore.c | 4 ++++
hw/cpu/arm11mpcore.c | 5 +++++
hw/intc/arm_gic.c | 33 +++++++++++++++++++++++++++++++--
hw/intc/arm_gic_common.c | 1 +
include/hw/intc/arm_gic.h | 2 ++
include/hw/intc/arm_gic_common.h | 1 +
6 files changed, 44 insertions(+), 2 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/3] arm_gic: Mask the un-supported priority bits
2020-02-24 9:39 [PATCH v3 0/3] Fix number of priority bits for arm boards Sai Pavan Boddu
@ 2020-02-24 9:39 ` Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5 Sai Pavan Boddu
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Sai Pavan Boddu @ 2020-02-24 9:39 UTC (permalink / raw)
To: Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Anthony Liguori, afaerber
Cc: qemu-arm, qemu-devel
Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits
are read as zeros(RAZ).
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 33 +++++++++++++++++++++++++++++++--
hw/intc/arm_gic_common.c | 1 +
include/hw/intc/arm_gic.h | 2 ++
include/hw/intc/arm_gic_common.h | 1 +
4 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1d7da7b..c60dc6b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return ret;
}
+static uint32_t gic_fullprio_mask(GICState *s, int cpu)
+{
+ /*
+ * Return a mask word which clears the unimplemented priority
+ * bits from a priority value for an interrupt. (Not to be
+ * confused with the group priority, whose mask depends on BPR.)
+ */
+ int priBits;
+
+ if (gic_is_vcpu(cpu)) {
+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;
+ } else {
+ priBits = s->n_prio_bits;
+ }
+ return ~0U << (8 - priBits);
+}
+
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs)
{
@@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
val = 0x80 | (val >> 1); /* Non-secure view */
}
+ val &= gic_fullprio_mask(s, cpu);
+
if (irq < GIC_INTERNAL) {
s->priority1[irq][cpu] = val;
} else {
@@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
}
prio = (prio << 1) & 0xff; /* Non-secure view */
}
- return prio;
+ return prio & gic_fullprio_mask(s, cpu);
}
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
@@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
return;
}
}
- s->priority_mask[cpu] = pmask;
+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);
}
static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
@@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||
+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {
+ error_setg(errp, "num-priority-bits cannot be greater than %d"
+ " or less than %d", GIC_MAX_PRIORITY_BITS,
+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ GIC_MIN_PRIORITY_BITS);
+ return;
+ }
+
/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
* enabled, virtualization extensions related interfaces (main virtual
* interface (s->vifaceiomem[0]) and virtual CPU interface).
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index e6c4fe7..7b44d56 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
/* True if the GIC should implement the virtualization extensions */
DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index ed703a1..303b974 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -68,6 +68,8 @@
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
+#define GIC_MAX_PRIORITY_BITS 8
+#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index b5585fe..6e0d6b8 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -96,6 +96,7 @@ typedef struct GICState {
uint16_t priority_mask[GIC_NCPU_VCPU];
uint16_t running_priority[GIC_NCPU_VCPU];
uint16_t current_pending[GIC_NCPU_VCPU];
+ uint32_t n_prio_bits;
/* If we present the GICv2 without security extensions to a guest,
* the guest can configure the GICC_CTLR to configure group 1 binary point
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5
2020-02-24 9:39 [PATCH v3 0/3] Fix number of priority bits for arm boards Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 1/3] arm_gic: Mask the un-supported priority bits Sai Pavan Boddu
@ 2020-02-24 9:39 ` Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Sai Pavan Boddu
2020-02-25 13:03 ` [PATCH v3 0/3] Fix number of priority bits for arm boards Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Sai Pavan Boddu @ 2020-02-24 9:39 UTC (permalink / raw)
To: Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Anthony Liguori, afaerber
Cc: qemu-arm, qemu-devel
All A9 CPUs have a GIC with 5 bits of priority.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a9mpcore.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 1f8bc8a..b4f6a7e 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -16,6 +16,8 @@
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#define A9_GIC_NUM_PRIORITY_BITS 5
+
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
A9MPPrivState *s = (A9MPPrivState *)opaque;
@@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
+ A9_GIC_NUM_PRIORITY_BITS);
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4
2020-02-24 9:39 [PATCH v3 0/3] Fix number of priority bits for arm boards Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 1/3] arm_gic: Mask the un-supported priority bits Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5 Sai Pavan Boddu
@ 2020-02-24 9:39 ` Sai Pavan Boddu
2020-02-25 13:03 ` [PATCH v3 0/3] Fix number of priority bits for arm boards Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Sai Pavan Boddu @ 2020-02-24 9:39 UTC (permalink / raw)
To: Edgar E . Iglesias, Alistair Francis, Peter Maydell,
Anthony Liguori, afaerber
Cc: qemu-arm, qemu-devel
ARM11MPCore GIC is implemented with 4 priority bits.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/arm11mpcore.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 2e3e87c..ab9fadb 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
@@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
+ ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
+
+
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] Fix number of priority bits for arm boards
2020-02-24 9:39 [PATCH v3 0/3] Fix number of priority bits for arm boards Sai Pavan Boddu
` (2 preceding siblings ...)
2020-02-24 9:39 ` [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Sai Pavan Boddu
@ 2020-02-25 13:03 ` Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2020-02-25 13:03 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Alistair Francis, QEMU Developers, qemu-arm, Anthony Liguori,
Edgar E . Iglesias, Andreas Färber
On Mon, 24 Feb 2020 at 09:44, Sai Pavan Boddu
<sai.pavan.boddu@xilinx.com> wrote:
>
> This patch series implements the mask for unimplemented priority bits in
> arm-gic. Which will return the expected number of priority bits on read.
>
> Changes for V2:
> Followed gicv3 code for defining mask for unimplemented bits
> Hardcoded num priority bits for A9 and ARM11MPCore boards
> Changes for V3:
> Fixed the code as suggested in V1.
> Implemented checks for max and min priority bits.
>
> Sai Pavan Boddu (3):
> arm_gic: Mask the un-supported priority bits
> cpu/a9mpcore: Set number of GIC priority bits to 5
> cpu/arm11mpcore: Set number of GIC priority bits to 4
Applied to target-arm.next, thanks. (I tweaked a few of
the commit messages to give a little more detail.)
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-02-24 9:39 [PATCH v3 0/3] Fix number of priority bits for arm boards Sai Pavan Boddu
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2020-02-24 9:39 ` [PATCH v3 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5 Sai Pavan Boddu
2020-02-24 9:39 ` [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Sai Pavan Boddu
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