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* [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors
@ 2020-08-13  9:41 Kaige Li
  2020-08-13  9:41 ` [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU Kaige Li
  2020-08-13 18:27 ` [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Aleksandar Markovic
  0 siblings, 2 replies; 7+ messages in thread
From: Kaige Li @ 2020-08-13  9:41 UTC (permalink / raw)
  To: Aleksandar Markovic, Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo
  Cc: qemu-devel

This will help ensure that style guidelines are being maintained during
subsequent changes.

Signed-off-by: Kaige Li <likaige@loongson.cn>
---
 target/mips/translate_init.inc.c | 61 ++++++++++++++++++++--------------------
 1 file changed, 31 insertions(+), 30 deletions(-)

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 637cacc..0740819 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -53,8 +53,7 @@
 
 /*****************************************************************************/
 /* MIPS CPU definitions */
-const mips_def_t mips_defs[] =
-{
+const mips_def_t mips_defs[] = {
     {
         .name = "4Kc",
         .CP0_PRid = 0x00018000,
@@ -766,8 +765,8 @@ const mips_def_t mips_defs[] =
         .name = "Loongson-2E",
         .CP0_PRid = 0x6302,
         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
-        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
-                       (0x1<<5) | (0x1<<4) | (0x1<<1),
+        .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 << 8) |
+                       (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
         /* Note: Config1 is only used internally,
            Loongson-2E has only Config0.  */
         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
@@ -786,8 +785,8 @@ const mips_def_t mips_defs[] =
         .name = "Loongson-2F",
         .CP0_PRid = 0x6303,
         /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
-        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
-                       (0x1<<5) | (0x1<<4) | (0x1<<1),
+        .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 << 8) |
+                       (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
         /* Note: Config1 is only used internally,
            Loongson-2F has only Config0.  */
         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
@@ -932,19 +931,19 @@ void mips_cpu_list(void)
 }
 
 #ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &no_mmu_map_address;
 }
 
-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1;
     env->tlb->map_address = &fixed_mmu_map_address;
 }
 
-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
     env->tlb->map_address = &r4k_map_address;
@@ -956,40 +955,41 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
     env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
 }
 
-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
 
     switch (def->mmu_type) {
-        case MMU_TYPE_NONE:
-            no_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R4000:
-            r4k_mmu_init(env, def);
-            break;
-        case MMU_TYPE_FMT:
-            fixed_mmu_init(env, def);
-            break;
-        case MMU_TYPE_R3000:
-        case MMU_TYPE_R6000:
-        case MMU_TYPE_R8000:
-        default:
-            cpu_abort(env_cpu(env), "MMU type not supported\n");
+    case MMU_TYPE_NONE:
+        no_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R4000:
+        r4k_mmu_init(env, def);
+        break;
+    case MMU_TYPE_FMT:
+        fixed_mmu_init(env, def);
+        break;
+    case MMU_TYPE_R3000:
+    case MMU_TYPE_R6000:
+    case MMU_TYPE_R8000:
+    default:
+        cpu_abort(env_cpu(env), "MMU type not supported\n");
     }
 }
 #endif /* CONFIG_USER_ONLY */
 
-static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fpu_init(CPUMIPSState *env, const mips_def_t *def)
 {
     int i;
 
-    for (i = 0; i < MIPS_FPU_MAX; i++)
+    for (i = 0; i < MIPS_FPU_MAX; i++) {
         env->fpus[i].fcr0 = def->CP1_fcr0;
+    }
 
     memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
 }
 
-static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
+static void mvp_init(CPUMIPSState *env, const mips_def_t *def)
 {
     env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
 
@@ -999,9 +999,10 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
        implemented, 5 TCs implemented. */
     env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
-// TODO: actually do 2 VPEs.
-//                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
-//                             (0x04 << CP0MVPC0_PTC);
+/* TODO: actually do 2 VPEs.
+ *                            (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
+ *                            (0x04 << CP0MVPC0_PTC);
+ */
                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
                              (0x00 << CP0MVPC0_PTC);
 #if !defined(CONFIG_USER_ONLY)
-- 
2.1.0



^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU
  2020-08-13  9:41 [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Kaige Li
@ 2020-08-13  9:41 ` Kaige Li
  2020-08-13 10:37   ` Jiaxun Yang
  2020-08-13 18:27 ` [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Aleksandar Markovic
  1 sibling, 1 reply; 7+ messages in thread
From: Kaige Li @ 2020-08-13  9:41 UTC (permalink / raw)
  To: Aleksandar Markovic, Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo
  Cc: qemu-devel

Add definition of the Loongson-3A3000 processor in QEMU.

Signed-off-by: Kaige Li <likaige@loongson.cn>
---
 target/mips/translate_init.inc.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 0740819..2e98aff 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -829,6 +829,30 @@ const mips_def_t mips_defs[] = {
         .PABITS = 48,
         .insn_flags = CPU_LOONGSON3A,
         .mmu_type = MMU_TYPE_R4000,
+   },
+   {
+        .name = "Loongson-3A3000",
+        .CP0_PRid = 0x14630d,
+        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
+                       (15 << CP0C2_SA),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .SYNCI_Step = 16,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x7DDBFFFF,
+        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64),
+        .CP1_fcr31 = 0,
+        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+        .SEGBITS = 48,
+        .PABITS = 48,
+        .insn_flags = CPU_LOONGSON3A,
+        .mmu_type = MMU_TYPE_R4000,
     },
     {
         .name = "Loongson-3A4000",
-- 
2.1.0



^ permalink raw reply related	[flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU
  2020-08-13  9:41 ` [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU Kaige Li
@ 2020-08-13 10:37   ` Jiaxun Yang
  2020-08-14  2:43     ` Kaige Li
  0 siblings, 1 reply; 7+ messages in thread
From: Jiaxun Yang @ 2020-08-13 10:37 UTC (permalink / raw)
  To: Kaige Li, Aleksandar Markovic, Aurelien Jarno, Aleksandar Rikalo
  Cc: qemu-devel



在 2020/8/13 下午5:41, Kaige Li 写道:
> Add definition of the Loongson-3A3000 processor in QEMU.

Hi Kaige,

We're not defining Loongson-3A3000 in QEMU because we have
some features like Loongson-EXT2, VTLB not available currently, I'd
prefer define it after we add these features to TCG.

Loongson-3A4000's define is a exception to support KVM.

Thanks.

- Jiaxun

>
> Signed-off-by: Kaige Li <likaige@loongson.cn>
> ---
>   target/mips/translate_init.inc.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
> index 0740819..2e98aff 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -829,6 +829,30 @@ const mips_def_t mips_defs[] = {
>           .PABITS = 48,
>           .insn_flags = CPU_LOONGSON3A,
>           .mmu_type = MMU_TYPE_R4000,
> +   },
> +   {
> +        .name = "Loongson-3A3000",
> +        .CP0_PRid = 0x14630d,
> +        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> +                       (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
> +                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
> +                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
> +                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> +        .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
> +                       (15 << CP0C2_SA),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> +        .SYNCI_Step = 16,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x7DDBFFFF,
> +        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64),
> +        .CP1_fcr31 = 0,
> +        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> +        .SEGBITS = 48,
> +        .PABITS = 48,
> +        .insn_flags = CPU_LOONGSON3A,
> +        .mmu_type = MMU_TYPE_R4000,
>       },
>       {
>           .name = "Loongson-3A4000",


^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors
  2020-08-13  9:41 [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Kaige Li
  2020-08-13  9:41 ` [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU Kaige Li
@ 2020-08-13 18:27 ` Aleksandar Markovic
  1 sibling, 0 replies; 7+ messages in thread
From: Aleksandar Markovic @ 2020-08-13 18:27 UTC (permalink / raw)
  To: Kaige Li; +Cc: Aleksandar Rikalo, Aurelien Jarno, qemu-devel

[-- Attachment #1: Type: text/plain, Size: 5720 bytes --]

On Thursday, August 13, 2020, Kaige Li <likaige@loongson.cn> wrote:

> This will help ensure that style guidelines are being maintained during
> subsequent changes.
>
> Signed-off-by: Kaige Li <likaige@loongson.cn>
> ---


Agreed.

Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>


>  target/mips/translate_init.inc.c | 61 ++++++++++++++++++++----------
> ----------
>  1 file changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/target/mips/translate_init.inc.c
> b/target/mips/translate_init.inc.c
> index 637cacc..0740819 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -53,8 +53,7 @@
>
>  /***********************************************************
> ******************/
>  /* MIPS CPU definitions */
> -const mips_def_t mips_defs[] =
> -{
> +const mips_def_t mips_defs[] = {
>      {
>          .name = "4Kc",
>          .CP0_PRid = 0x00018000,
> @@ -766,8 +765,8 @@ const mips_def_t mips_defs[] =
>          .name = "Loongson-2E",
>          .CP0_PRid = 0x6302,
>          /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.
> */
> -        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
> -                       (0x1<<5) | (0x1<<4) | (0x1<<1),
> +        .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 <<
> 8) |
> +                       (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
>          /* Note: Config1 is only used internally,
>             Loongson-2E has only Config0.  */
>          .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
> @@ -786,8 +785,8 @@ const mips_def_t mips_defs[] =
>          .name = "Loongson-2F",
>          .CP0_PRid = 0x6303,
>          /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.
> */
> -        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
> -                       (0x1<<5) | (0x1<<4) | (0x1<<1),
> +        .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 <<
> 8) |
> +                       (0x1 << 5) | (0x1 << 4) | (0x1 << 1),
>          /* Note: Config1 is only used internally,
>             Loongson-2F has only Config0.  */
>          .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
> @@ -932,19 +931,19 @@ void mips_cpu_list(void)
>  }
>
>  #ifndef CONFIG_USER_ONLY
> -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      env->tlb->nb_tlb = 1;
>      env->tlb->map_address = &no_mmu_map_address;
>  }
>
> -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      env->tlb->nb_tlb = 1;
>      env->tlb->map_address = &fixed_mmu_map_address;
>  }
>
> -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
>      env->tlb->map_address = &r4k_map_address;
> @@ -956,40 +955,41 @@ static void r4k_mmu_init (CPUMIPSState *env, const
> mips_def_t *def)
>      env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
>  }
>
> -static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
>
>      switch (def->mmu_type) {
> -        case MMU_TYPE_NONE:
> -            no_mmu_init(env, def);
> -            break;
> -        case MMU_TYPE_R4000:
> -            r4k_mmu_init(env, def);
> -            break;
> -        case MMU_TYPE_FMT:
> -            fixed_mmu_init(env, def);
> -            break;
> -        case MMU_TYPE_R3000:
> -        case MMU_TYPE_R6000:
> -        case MMU_TYPE_R8000:
> -        default:
> -            cpu_abort(env_cpu(env), "MMU type not supported\n");
> +    case MMU_TYPE_NONE:
> +        no_mmu_init(env, def);
> +        break;
> +    case MMU_TYPE_R4000:
> +        r4k_mmu_init(env, def);
> +        break;
> +    case MMU_TYPE_FMT:
> +        fixed_mmu_init(env, def);
> +        break;
> +    case MMU_TYPE_R3000:
> +    case MMU_TYPE_R6000:
> +    case MMU_TYPE_R8000:
> +    default:
> +        cpu_abort(env_cpu(env), "MMU type not supported\n");
>      }
>  }
>  #endif /* CONFIG_USER_ONLY */
>
> -static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
> +static void fpu_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      int i;
>
> -    for (i = 0; i < MIPS_FPU_MAX; i++)
> +    for (i = 0; i < MIPS_FPU_MAX; i++) {
>          env->fpus[i].fcr0 = def->CP1_fcr0;
> +    }
>
>      memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
>  }
>
> -static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
> +static void mvp_init(CPUMIPSState *env, const mips_def_t *def)
>  {
>      env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
>
> @@ -999,9 +999,10 @@ static void mvp_init (CPUMIPSState *env, const
> mips_def_t *def)
>         implemented, 5 TCs implemented. */
>      env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
>                               (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
> -// TODO: actually do 2 VPEs.
> -//                             (1 << CP0MVPC0_TCA) | (0x1 <<
> CP0MVPC0_PVPE) |
> -//                             (0x04 << CP0MVPC0_PTC);
> +/* TODO: actually do 2 VPEs.
> + *                            (1 << CP0MVPC0_TCA) | (0x1 <<
> CP0MVPC0_PVPE) |
> + *                            (0x04 << CP0MVPC0_PTC);
> + */
>                               (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE)
> |
>                               (0x00 << CP0MVPC0_PTC);
>  #if !defined(CONFIG_USER_ONLY)
> --
> 2.1.0
>
>

[-- Attachment #2: Type: text/html, Size: 7742 bytes --]

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU
  2020-08-13 10:37   ` Jiaxun Yang
@ 2020-08-14  2:43     ` Kaige Li
  2020-08-14  2:48       ` Jiaxun Yang
  0 siblings, 1 reply; 7+ messages in thread
From: Kaige Li @ 2020-08-14  2:43 UTC (permalink / raw)
  To: Jiaxun Yang, Aleksandar Markovic, Aurelien Jarno, Aleksandar Rikalo
  Cc: qemu-devel

On 08/13/2020 06:37 PM, Jiaxun Yang wrote:

>
>
> 在 2020/8/13 下午5:41, Kaige Li 写道:
>> Add definition of the Loongson-3A3000 processor in QEMU.
>
> Hi Kaige,
>
> We're not defining Loongson-3A3000 in QEMU because we have
> some features like Loongson-EXT2, VTLB not available currently, I'd
> prefer define it after we add these features to TCG.
>
> Loongson-3A4000's define is a exception to support KVM.
Ok, I see. This will be defined later, right?
Thanks.
Kaige.
>
> Thanks.
>
> - Jiaxun
>
>>
>> Signed-off-by: Kaige Li <likaige@loongson.cn>
>> ---
>>   target/mips/translate_init.inc.c | 24 ++++++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/target/mips/translate_init.inc.c 
>> b/target/mips/translate_init.inc.c
>> index 0740819..2e98aff 100644
>> --- a/target/mips/translate_init.inc.c
>> +++ b/target/mips/translate_init.inc.c
>> @@ -829,6 +829,30 @@ const mips_def_t mips_defs[] = {
>>           .PABITS = 48,
>>           .insn_flags = CPU_LOONGSON3A,
>>           .mmu_type = MMU_TYPE_R4000,
>> +   },
>> +   {
>> +        .name = "Loongson-3A3000",
>> +        .CP0_PRid = 0x14630d,
>> +        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line 
>> size.  */
>> +        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << 
>> CP0C0_AT) |
>> +                       (MMU_TYPE_R4000 << CP0C0_MT),
>> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << 
>> CP0C1_MMU) |
>> +                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << 
>> CP0C1_IA) |
>> +                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << 
>> CP0C1_DA) |
>> +                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << 
>> CP0C1_EP),
>> +        .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << 
>> CP0C2_SL) |
>> +                       (15 << CP0C2_SA),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>> +        .SYNCI_Step = 16,
>> +        .CCRes = 2,
>> +        .CP0_Status_rw_bitmask = 0x7DDBFFFF,
>> +        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << 
>> FCR0_F64),
>> +        .CP1_fcr31 = 0,
>> +        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
>> +        .SEGBITS = 48,
>> +        .PABITS = 48,
>> +        .insn_flags = CPU_LOONGSON3A,
>> +        .mmu_type = MMU_TYPE_R4000,
>>       },
>>       {
>>           .name = "Loongson-3A4000",



^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU
  2020-08-14  2:43     ` Kaige Li
@ 2020-08-14  2:48       ` Jiaxun Yang
  2020-08-20  7:44         ` Kaige Li
  0 siblings, 1 reply; 7+ messages in thread
From: Jiaxun Yang @ 2020-08-14  2:48 UTC (permalink / raw)
  To: Kaige Li, Aleksandar Markovic, Aurelien Jarno, Aleksandar Rikalo
  Cc: qemu-devel



在 2020/8/14 上午10:43, Kaige Li 写道:
> On 08/13/2020 06:37 PM, Jiaxun Yang wrote:
>
>>
>>
>> 在 2020/8/13 下午5:41, Kaige Li 写道:
>>> Add definition of the Loongson-3A3000 processor in QEMU.
>>
>> Hi Kaige,
>>
>> We're not defining Loongson-3A3000 in QEMU because we have
>> some features like Loongson-EXT2, VTLB not available currently, I'd
>> prefer define it after we add these features to TCG.
>>
>> Loongson-3A4000's define is a exception to support KVM.
> Ok, I see. This will be defined later, right?
Yes..

If you're willing to help I'd suggest you to take a look at how to implement
Loongson SPW (LDPTE LDDIR etc) in QEMU.


Thanks.

- Jiaxun

>
> Thanks.
> Kaige.
>>
>> Thanks.
>>
>> - Jiaxun


^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU
  2020-08-14  2:48       ` Jiaxun Yang
@ 2020-08-20  7:44         ` Kaige Li
  0 siblings, 0 replies; 7+ messages in thread
From: Kaige Li @ 2020-08-20  7:44 UTC (permalink / raw)
  To: Jiaxun Yang, Aleksandar Markovic, Aurelien Jarno, Aleksandar Rikalo
  Cc: qemu-devel



On 08/14/2020 10:48 AM, Jiaxun Yang wrote:
>
>
> 在 2020/8/14 上午10:43, Kaige Li 写道:
>> On 08/13/2020 06:37 PM, Jiaxun Yang wrote:
>>
>>>
>>>
>>> 在 2020/8/13 下午5:41, Kaige Li 写道:
>>>> Add definition of the Loongson-3A3000 processor in QEMU.
>>>
>>> Hi Kaige,
>>>
>>> We're not defining Loongson-3A3000 in QEMU because we have
>>> some features like Loongson-EXT2, VTLB not available currently, I'd
>>> prefer define it after we add these features to TCG.
>>>
>>> Loongson-3A4000's define is a exception to support KVM.
>> Ok, I see. This will be defined later, right?
> Yes..
>
> If you're willing to help I'd suggest you to take a look at how to 
> implement
> Loongson SPW (LDPTE LDDIR etc) in QEMU.
Ok, I'll analyze it carefully.

thanks.
-Kaige
>
>
> Thanks.
>
> - Jiaxun
>
>>
>> Thanks.
>> Kaige.
>>>
>>> Thanks.
>>>
>>> - Jiaxun



^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-08-20  7:45 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-13  9:41 [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Kaige Li
2020-08-13  9:41 ` [PATCH 2/2] target/mips: Add definition of Loongson-3A3000 CPU Kaige Li
2020-08-13 10:37   ` Jiaxun Yang
2020-08-14  2:43     ` Kaige Li
2020-08-14  2:48       ` Jiaxun Yang
2020-08-20  7:44         ` Kaige Li
2020-08-13 18:27 ` [PATCH 1/2] target/mips: Coding style update to fix checkpatch errors Aleksandar Markovic

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