From: Huacai Chen <zltjiangshi@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Huacai Chen <chenhuacai@gmail.com>,
qemu-devel@nongnu.org, Huacai Chen <chenhc@lemote.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
Date: Fri, 16 Oct 2020 14:51:54 +0800 [thread overview]
Message-ID: <1602831120-3377-3-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1602831120-3377-1-git-send-email-chenhc@lemote.com>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
gssqc1: store 16 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
target/mips/translate.c | 86 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf7289..20a7f36c7c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,17 @@ enum {
R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
};
+/* Loongson EXT load/store quad word opcodes */
+#define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020))
+enum {
+ OPC_GSLQ = 0x0020 | OPC_LWC2,
+ OPC_GSLQC1 = 0x8020 | OPC_LWC2,
+ OPC_GSSHFL = OPC_LWC2,
+ OPC_GSSQ = 0x0020 | OPC_SWC2,
+ OPC_GSSQC1 = 0x8020 | OPC_SWC2,
+ OPC_GSSHFS = OPC_SWC2,
+};
+
/* BSHFL opcodes */
#define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -5910,6 +5921,79 @@ no_rd:
tcg_temp_free_i64(t1);
}
+static void gen_loongson_lswc2(DisasContext *ctx, int rt,
+ int rs, int rd)
+{
+ TCGv t0, t1, t2;
+ TCGv_i32 fp0;
+#if defined(TARGET_MIPS64)
+ int lsq_rt1 = ctx->opcode & 0x1f;
+ int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
+#endif
+
+ t0 = tcg_temp_new();
+
+ switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
+#if defined(TARGET_MIPS64)
+ case OPC_GSLQ:
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t1, rt);
+ gen_store_gpr(t0, lsq_rt1);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSLQC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_store_fpr64(ctx, t1, rt);
+ gen_store_fpr64(ctx, t0, lsq_rt1);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSQ:
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ gen_load_gpr(t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ gen_load_gpr(t1, lsq_rt1);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+ case OPC_GSSQC1:
+ check_cp1_enabled(ctx);
+ t1 = tcg_temp_new();
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset);
+ gen_load_fpr64(ctx, t1, rt);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
+ gen_load_fpr64(ctx, t1, lsq_rt1);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+ ctx->default_tcg_memop_mask);
+ tcg_temp_free(t1);
+ break;
+#endif
+ default:
+ MIPS_INVAL("loongson_gslsq");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ tcg_temp_free(t0);
+}
+
/* Traps */
static void gen_trap(DisasContext *ctx, uint32_t opc,
int rs, int rt, int16_t imm)
@@ -30774,6 +30858,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_BC, OPC_BALC */
gen_compute_compact_branch(ctx, op, 0, 0,
sextract32(ctx->opcode << 2, 0, 28));
+ } else if (ctx->insn_flags & ASE_LEXT) {
+ gen_loongson_lswc2(ctx, rt, rs, rd);
} else {
/* OPC_LWC2, OPC_SWC2 */
/* COP2: Not implemented. */
--
2.17.2
next prev parent reply other threads:[~2020-10-16 6:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 6:51 [PATCH V14 0/8] mips: Add Loongson-3 machine support Huacai Chen
2020-10-16 6:51 ` [PATCH V14 1/8] target/mips: Fix PageMask with variable page size Huacai Chen
2020-10-16 15:15 ` Philippe Mathieu-Daudé
2020-10-20 1:38 ` Huacai Chen
2020-10-16 6:51 ` Huacai Chen [this message]
2020-10-16 15:12 ` [PATCH V14 2/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 3/8] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) Huacai Chen
2020-10-16 6:51 ` [PATCH V14 4/8] target/mips: Add loongson-ext lsdc2 group of instructions Huacai Chen
2020-10-16 14:12 ` Philippe Mathieu-Daudé
2020-10-16 6:51 ` [PATCH V14 5/8] hw/mips: Implement fw_cfg_arch_key_name() Huacai Chen
2020-10-16 6:51 ` [PATCH V14 6/8] hw/mips: Add Loongson-3 boot parameter helpers Huacai Chen
2020-10-16 14:24 ` Philippe Mathieu-Daudé
2020-10-20 2:22 ` Huacai Chen
2020-10-16 6:51 ` [PATCH V14 7/8] hw/mips: Add Loongson-3 machine support Huacai Chen
2020-10-17 15:58 ` Philippe Mathieu-Daudé
2020-10-20 8:05 ` Huacai Chen
2020-10-16 6:52 ` [PATCH V14 8/8] docs/system: Update MIPS machine documentation Huacai Chen
2020-10-16 14:25 ` Philippe Mathieu-Daudé
2020-10-16 7:06 ` [PATCH V14 0/8] mips: Add Loongson-3 machine support no-reply
2020-10-16 16:47 ` Philippe Mathieu-Daudé
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