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* [PATCH] i386: Add the support for AMD EPYC 3rd generation processors
@ 2021-01-22 16:36 Babu Moger
  2021-02-01 22:16 ` Eduardo Habkost
  0 siblings, 1 reply; 4+ messages in thread
From: Babu Moger @ 2021-01-22 16:36 UTC (permalink / raw)
  To: pbonzini, richard.henderson, ehabkost; +Cc: babu.moger, qemu-devel

Adds the support for AMD 3rd generation processors. The model
display for the new processor will be EPYC-Milan.

Adds the following new feature bits on top of the feature bits from
the first and second generation EPYC models.

pcid    : Process context identifiers support
ibrs    : Indirect Branch Restricted Speculation
ssbd    : Speculative Store Bypass Disable
erms    : Enhanced REP MOVSB/STOSB support
fsrm    : Fast Short REP MOVSB support
invpcid : Invalidate processor context ID
pku     : Protection keys support

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c |  105 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 target/i386/cpu.h |    4 ++
 2 files changed, 109 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 35459a38bb..666995bb42 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1798,6 +1798,56 @@ static CPUCaches epyc_rome_cache_info = {
     },
 };
 
+static CPUCaches epyc_milan_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 32 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 32768,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = true,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
@@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "AMD EPYC-Rome Processor",
         .cache_info = &epyc_rome_cache_info,
     },
+    {
+        .name = "EPYC-Milan",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_AMD,
+        .family = 25,
+        .model = 1,
+        .stepping = 1,
+        .features[FEAT_1_EDX] =
+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+            CPUID_VME | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
+            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+            CPUID_EXT_PCID,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+            CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+            CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
+        .features[FEAT_8000_0008_EBX] =
+            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
+            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
+            CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
+            CPUID_8000_0008_EBX_AMD_SSBD,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
+            CPUID_7_0_EBX_INVPCID,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_FSRM,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
+        .xlevel = 0x8000001E,
+        .model_id = "AMD EPYC-Milan Processor",
+        .cache_info = &epyc_milan_cache_info,
+    },
 };
 
 /* KVM-specific features that are automatically added/removed
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d23a5b340a..3bc210863a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -808,8 +808,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
 /* Indirect Branch Prediction Barrier */
 #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
+/* Indirect Branch Restricted Speculation */
+#define CPUID_8000_0008_EBX_IBRS        (1U << 14)
 /* Single Thread Indirect Branch Predictors */
 #define CPUID_8000_0008_EBX_STIBP       (1U << 15)
+/* Speculative Store Bypass Disable */
+#define CPUID_8000_0008_EBX_AMD_SSBD    (1U << 24)
 
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] i386: Add the support for AMD EPYC 3rd generation processors
  2021-01-22 16:36 [PATCH] i386: Add the support for AMD EPYC 3rd generation processors Babu Moger
@ 2021-02-01 22:16 ` Eduardo Habkost
  2021-02-01 22:29   ` Babu Moger
  0 siblings, 1 reply; 4+ messages in thread
From: Eduardo Habkost @ 2021-02-01 22:16 UTC (permalink / raw)
  To: Babu Moger; +Cc: pbonzini, richard.henderson, qemu-devel

On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote:
> Adds the support for AMD 3rd generation processors. The model
> display for the new processor will be EPYC-Milan.
> 
> Adds the following new feature bits on top of the feature bits from
> the first and second generation EPYC models.
> 
> pcid    : Process context identifiers support
> ibrs    : Indirect Branch Restricted Speculation
> ssbd    : Speculative Store Bypass Disable
> erms    : Enhanced REP MOVSB/STOSB support
> fsrm    : Fast Short REP MOVSB support
> invpcid : Invalidate processor context ID
> pku     : Protection keys support
> 
> Signed-off-by: Babu Moger <babu.moger@amd.com>
[...]
> @@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .model_id = "AMD EPYC-Rome Processor",
>          .cache_info = &epyc_rome_cache_info,
>      },
> +    {
> +        .name = "EPYC-Milan",
[...]
> +        .features[FEAT_8000_0008_EBX] =
> +            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
> +            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
> +            CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
> +            CPUID_8000_0008_EBX_AMD_SSBD,

This breaks query-cpu-model-expansion, see:
https://gitlab.com/ehabkost/qemu/-/jobs/1000347471#L350

20:11:28 ERROR| Reproduced traceback from: /builds/ehabkost/qemu/build/tests/venv/lib64/python3.6/site-packages/avocado/core/test.py:767
20:11:28 ERROR| Traceback (most recent call last):
20:11:28 ERROR|   File "/builds/ehabkost/qemu/build/tests/acceptance/cpu_queries.py", line 31, in test
20:11:28 ERROR|     self.assertNotIn('', c['unavailable-features'], c['name'])
20:11:28 ERROR|   File "/usr/lib64/python3.6/unittest/case.py", line 1096, in assertNotIn
20:11:28 ERROR|     self.fail(self._formatMessage(msg, standardMsg))
20:11:28 ERROR|   File "/builds/ehabkost/qemu/build/tests/venv/lib64/python3.6/site-packages/avocado/core/test.py", line 953, in fail
20:11:28 ERROR|     raise exceptions.TestFail(message)
20:11:28 ERROR| avocado.core.exceptions.TestFail: '' unexpectedly found in ['fma', 'pcid', 'avx', 'f16c', 'avx2', 'invpcid', 'rdseed', 'sha-ni', 'umip', 'rdpid', 'fsrm', 'fxsr-opt', 'misalignsse', '3dnowprefetch', 'osvw', 'topoext', 'perfctr-core', 'clzero', 'xsaveerptr', 'wbnoinvd', 'ibpb', '', 'amd-stibp', 'amd-ssbd', 'nrip-save', 'xsavec', 'xsaves'] : EPYC-Milan-v1

The root cause is the lack of name for CPUID_8000_0008_EBX_IBRS at
feature_word_info[CPUID_8000_0008_EBX_IBRS].feat_names[14].

I'm applying the following fixup.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 06c92650a17..8d4baf72e5b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "clzero", NULL, "xsaveerptr", NULL,
             NULL, NULL, NULL, NULL,
             NULL, "wbnoinvd", NULL, NULL,
-            "ibpb", NULL, NULL, "amd-stibp",
+            "ibpb", NULL, "ibrs", "amd-stibp",
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,

-- 
Eduardo



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] i386: Add the support for AMD EPYC 3rd generation processors
  2021-02-01 22:16 ` Eduardo Habkost
@ 2021-02-01 22:29   ` Babu Moger
  2021-02-01 22:38     ` Eduardo Habkost
  0 siblings, 1 reply; 4+ messages in thread
From: Babu Moger @ 2021-02-01 22:29 UTC (permalink / raw)
  To: Eduardo Habkost; +Cc: pbonzini, richard.henderson, qemu-devel

Eduardo,
Please hold off on this patch. I need to update this patch.
Actually We need to add one more bit to SVM
feature(CPUID_SVM_SVME_ADDR_CHK). I was planning to do that this week.
Got busy with some other priority. Will send it this week, Sorry about it.
thanks
Babu


On 2/1/21 4:16 PM, Eduardo Habkost wrote:
> On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote:
>> Adds the support for AMD 3rd generation processors. The model
>> display for the new processor will be EPYC-Milan.
>>
>> Adds the following new feature bits on top of the feature bits from
>> the first and second generation EPYC models.
>>
>> pcid    : Process context identifiers support
>> ibrs    : Indirect Branch Restricted Speculation
>> ssbd    : Speculative Store Bypass Disable
>> erms    : Enhanced REP MOVSB/STOSB support
>> fsrm    : Fast Short REP MOVSB support
>> invpcid : Invalidate processor context ID
>> pku     : Protection keys support
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
> [...]
>> @@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = {
>>          .model_id = "AMD EPYC-Rome Processor",
>>          .cache_info = &epyc_rome_cache_info,
>>      },
>> +    {
>> +        .name = "EPYC-Milan",
> [...]
>> +        .features[FEAT_8000_0008_EBX] =
>> +            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
>> +            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
>> +            CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
>> +            CPUID_8000_0008_EBX_AMD_SSBD,
> 
> This breaks query-cpu-model-expansion, see:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.com%2Fehabkost%2Fqemu%2F-%2Fjobs%2F1000347471%23L350&amp;data=04%7C01%7Cbabu.moger%40amd.com%7Cc472108231e74551a34a08d8c6ff0975%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637478145976001070%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=UggCEUXrcWCaRLgyClQ53lLnWDqu6%2F9bnxcyJqjy68s%3D&amp;reserved=0
> 
> 20:11:28 ERROR| Reproduced traceback from: /builds/ehabkost/qemu/build/tests/venv/lib64/python3.6/site-packages/avocado/core/test.py:767
> 20:11:28 ERROR| Traceback (most recent call last):
> 20:11:28 ERROR|   File "/builds/ehabkost/qemu/build/tests/acceptance/cpu_queries.py", line 31, in test
> 20:11:28 ERROR|     self.assertNotIn('', c['unavailable-features'], c['name'])
> 20:11:28 ERROR|   File "/usr/lib64/python3.6/unittest/case.py", line 1096, in assertNotIn
> 20:11:28 ERROR|     self.fail(self._formatMessage(msg, standardMsg))
> 20:11:28 ERROR|   File "/builds/ehabkost/qemu/build/tests/venv/lib64/python3.6/site-packages/avocado/core/test.py", line 953, in fail
> 20:11:28 ERROR|     raise exceptions.TestFail(message)
> 20:11:28 ERROR| avocado.core.exceptions.TestFail: '' unexpectedly found in ['fma', 'pcid', 'avx', 'f16c', 'avx2', 'invpcid', 'rdseed', 'sha-ni', 'umip', 'rdpid', 'fsrm', 'fxsr-opt', 'misalignsse', '3dnowprefetch', 'osvw', 'topoext', 'perfctr-core', 'clzero', 'xsaveerptr', 'wbnoinvd', 'ibpb', '', 'amd-stibp', 'amd-ssbd', 'nrip-save', 'xsavec', 'xsaves'] : EPYC-Milan-v1
> 
> The root cause is the lack of name for CPUID_8000_0008_EBX_IBRS at
> feature_word_info[CPUID_8000_0008_EBX_IBRS].feat_names[14].
> 
> I'm applying the following fixup.
> 
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 06c92650a17..8d4baf72e5b 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>              "clzero", NULL, "xsaveerptr", NULL,
>              NULL, NULL, NULL, NULL,
>              NULL, "wbnoinvd", NULL, NULL,
> -            "ibpb", NULL, NULL, "amd-stibp",
> +            "ibpb", NULL, "ibrs", "amd-stibp",
>              NULL, NULL, NULL, NULL,
>              NULL, NULL, NULL, NULL,
>              "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
> 


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] i386: Add the support for AMD EPYC 3rd generation processors
  2021-02-01 22:29   ` Babu Moger
@ 2021-02-01 22:38     ` Eduardo Habkost
  0 siblings, 0 replies; 4+ messages in thread
From: Eduardo Habkost @ 2021-02-01 22:38 UTC (permalink / raw)
  To: Babu Moger
  Cc: pbonzini, richard.henderson, qemu-devel, Dr. David Alan Gilbert

On Mon, Feb 01, 2021 at 04:29:50PM -0600, Babu Moger wrote:
> Eduardo,
> Please hold off on this patch. I need to update this patch.
> Actually We need to add one more bit to SVM
> feature(CPUID_SVM_SVME_ADDR_CHK). I was planning to do that this week.
> Got busy with some other priority. Will send it this week, Sorry about it.

No problem, thanks for the heads up!

-- 
Eduardo



^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-02-01 22:46 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-22 16:36 [PATCH] i386: Add the support for AMD EPYC 3rd generation processors Babu Moger
2021-02-01 22:16 ` Eduardo Habkost
2021-02-01 22:29   ` Babu Moger
2021-02-01 22:38     ` Eduardo Habkost

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