[Bug 1909823] [NEW] RDPMC check on PCE is backwards

[Bug 1909823] [NEW] RDPMC check on PCE is backwards

[Bruce Merry]

Public bug reported:

At [this
line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225)
the check on CR4_PCE_MASK is backwards: it's raising an exception if the
flag is set (and CPL != 0) rather than if the flag is clear.

It's low priority at the moment because the instruction isn't
implemented, so you get an illegal opcode exception when expecting a
GPF, or vice versa, but it's a time bomb for if it is ever implemented.

The Intel docs also indicate that CR0.PE influences the protection; I
don't know if that's already reflected in env->hflags & HF_CPL_MASK.

** Affects: qemu
     Importance: Undecided
         Status: New

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Title:
  RDPMC check on PCE is backwards

Status in QEMU:
  New

Bug description:
  At [this
  line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225)
  the check on CR4_PCE_MASK is backwards: it's raising an exception if
  the flag is set (and CPL != 0) rather than if the flag is clear.

  It's low priority at the moment because the instruction isn't
  implemented, so you get an illegal opcode exception when expecting a
  GPF, or vice versa, but it's a time bomb for if it is ever
  implemented.

  The Intel docs also indicate that CR0.PE influences the protection; I
  don't know if that's already reflected in env->hflags & HF_CPL_MASK.

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[Bug 1909823] Re: RDPMC check on PCE is backwards

[Thomas Huth]

The QEMU project is currently moving its bug tracking to another system.
For this we need to know which bugs are still valid and which could be
closed already. Thus we are setting the bug state to "Incomplete" now.

If the bug has already been fixed in the latest upstream version of QEMU,
then please close this ticket as "Fix released".

If it is not fixed yet and you think that this bug report here is still
valid, then you have two options:

1) If you already have an account on gitlab.com, please open a new ticket
for this problem in our new tracker here:

    https://gitlab.com/qemu-project/qemu/-/issues

and then close this ticket here on Launchpad (or let it expire auto-
matically after 60 days). Please mention the URL of this bug ticket on
Launchpad in the new ticket on GitLab.

2) If you don't have an account on gitlab.com and don't intend to get
one, but still would like to keep this ticket opened, then please switch
the state back to "New" or "Confirmed" within the next 60 days (other-
wise it will get closed as "Expired"). We will then eventually migrate
the ticket automatically to the new system (but you won't be the reporter
of the bug in the new system and thus you won't get notified on changes
anymore).

Thank you and sorry for the inconvenience.


** Tags added: i386 tcg

** Changed in: qemu
       Status: New => Incomplete

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https://bugs.launchpad.net/bugs/1909823

Title:
  RDPMC check on PCE is backwards

Status in QEMU:
  Incomplete

Bug description:
  At [this
  line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225)
  the check on CR4_PCE_MASK is backwards: it's raising an exception if
  the flag is set (and CPL != 0) rather than if the flag is clear.

  It's low priority at the moment because the instruction isn't
  implemented, so you get an illegal opcode exception when expecting a
  GPF, or vice versa, but it's a time bomb for if it is ever
  implemented.

  The Intel docs also indicate that CR0.PE influences the protection; I
  don't know if that's already reflected in env->hflags & HF_CPL_MASK.

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[Bug 1909823] Re: RDPMC check on PCE is backwards

[Bruce Merry]

It looks like this was fixed in c45b426.

** Changed in: qemu
       Status: Incomplete => Fix Released

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1909823

Title:
  RDPMC check on PCE is backwards

Status in QEMU:
  Fix Released

Bug description:
  At [this
  line](https://github.com/qemu/qemu/blob/75ee62ac606bfc9eb59310b9446df3434bf6e8c2/target/i386/tcg/misc_helper.c#L225)
  the check on CR4_PCE_MASK is backwards: it's raising an exception if
  the flag is set (and CPL != 0) rather than if the flag is clear.

  It's low priority at the moment because the instruction isn't
  implemented, so you get an illegal opcode exception when expecting a
  GPF, or vice versa, but it's a time bomb for if it is ever
  implemented.

  The Intel docs also indicate that CR0.PE influences the protection; I
  don't know if that's already reflected in env->hflags & HF_CPL_MASK.

To manage notifications about this bug go to:
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