From: Richard Henderson <richard.henderson@linaro.org>
To: Stefan Brankovic <stefan.brankovic@rt-rk.com>, qemu-devel@nongnu.org
Cc: david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH 6/8] target/ppc: Optimize emulation of vclzw instruction
Date: Thu, 6 Jun 2019 13:34:17 -0500 [thread overview]
Message-ID: <18871125-cb2c-57e7-864d-c5c7a8846093@linaro.org> (raw)
In-Reply-To: <1559816130-17113-7-git-send-email-stefan.brankovic@rt-rk.com>
On 6/6/19 5:15 AM, Stefan Brankovic wrote:
> + for (i = 0; i < 2; i++) {
> + if (i == 0) {
> + /* Get high doubleword element of vB in avr. */
> + get_avr64(avr, VB, true);
> + } else {
> + /* Get low doubleword element of vB in avr. */
> + get_avr64(avr, VB, false);
> + }
Better as simply get_avr64(avr, VB, i);
> + /*
> + * Perform count for every word element using tcg_gen_clzi_i64.
> + * Since it counts leading zeros on 64 bit lenght, we have to move
> + * ith word element to highest 32 bits of tmp, or it with mask(so we get
> + * all ones in lowest 32 bits), then perform tcg_gen_clzi_i64 and move
> + * it's result in appropriate word element of result.
> + */
> + tcg_gen_shli_i64(tmp, avr, 32);
> + tcg_gen_or_i64(tmp, tmp, mask);
> + tcg_gen_clzi_i64(result, tmp, 64);
> +
> + tcg_gen_or_i64(tmp, avr, mask);
> + tcg_gen_clzi_i64(tmp, tmp, 64);
s/64/32.
> + tcg_gen_deposit_i64(result, result, tmp, 32, 32);
That said, it's probably better to treat this as 4 words, not 2 doublewords.
for (i = 0; i < 4; i++) {
tcg_gen_ld_i32(tmp, cpu_env, avr_full_offset(VB) + i * 4);
tcg_gen_clzi_i32(tmp, tmp, 32);
tcg_gen_st_i32(tmp, cpu_env, avr_full_offset(VT) + i * 4);
}
r~
next prev parent reply other threads:[~2019-06-06 18:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-06 10:15 [Qemu-devel] [PATCH 0/8] Optimize emulation of ten Altivec instructions: lvsl, Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 1/8] target/ppc: Optimize emulation of lvsl and lvsr instructions Stefan Brankovic
2019-06-06 16:46 ` Richard Henderson
2019-06-17 11:31 ` Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions Stefan Brankovic
2019-06-06 17:03 ` Richard Henderson
2019-06-17 11:36 ` Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 3/8] target/ppc: Optimize emulation of vpkpx instruction Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 4/8] target/ppc: Optimize emulation of vgbbd instruction Stefan Brankovic
2019-06-06 18:19 ` Richard Henderson
2019-06-17 11:58 ` Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 5/8] target/ppc: Optimize emulation of vclzd instruction Stefan Brankovic
2019-06-06 18:26 ` Richard Henderson
2019-06-06 10:15 ` [Qemu-devel] [PATCH 6/8] target/ppc: Optimize emulation of vclzw instruction Stefan Brankovic
2019-06-06 18:34 ` Richard Henderson [this message]
2019-06-17 11:50 ` Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 7/8] target/ppc: Optimize emulation of vclzh and vclzb instructions Stefan Brankovic
2019-06-06 20:38 ` Richard Henderson
2019-06-17 11:42 ` Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 8/8] target/ppc: Refactor emulation of vmrgew and vmrgow instructions Stefan Brankovic
2019-06-06 20:43 ` Richard Henderson
2019-06-17 11:43 ` Stefan Brankovic
2019-06-06 17:13 ` [Qemu-devel] [PATCH 0/8] Optimize emulation of ten Altivec instructions: lvsl, Richard Henderson
2019-06-12 7:31 ` [Qemu-devel] ?==?utf-8?q? ?==?utf-8?q? [PATCH 0/8] Optimize emulation of ten Altivec instructions:?==?utf-8?q? lvsl, Stefan Brankovic
2019-06-17 11:32 ` [Qemu-devel] [PATCH 0/8] Optimize emulation of ten Altivec instructions: lvsl, Stefan Brankovic
2019-06-07 3:51 ` Howard Spoelstra
2019-06-19 11:03 [Qemu-devel] [PATCH 0/8] target/ppc: Optimize emulation of some Altivec instructions Stefan Brankovic
2019-06-19 11:03 ` [Qemu-devel] [PATCH 6/8] target/ppc: Optimize emulation of vclzw instruction Stefan Brankovic
2019-06-26 15:38 ` Richard Henderson
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