* [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend)
@ 2019-08-21 12:23 Bastian Koppelmann
2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann
` (7 more replies)
0 siblings, 8 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson
(sorry about the noise, git-sendmail just quit with "Temporary local problem -
please try later" after sending two of the mails)
Hi,
I finally came around to port TriCore to the "new" translate_loop
infrastructure. This is necessary such that TriCore can be used in the upcoming
plugin API [1].
Cheers,
Bastian
[1] (https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg03165.html)
v1 -> v2:
[03/05] Now also save hflags in tricore_tr_init_disas_context()
[04/05] New patch that raises EXCP_DEBUG for breakpoints, TriCore debug insns
[05/05] New patch that properly fetches 16 bit insns and does the page
boundary check.
Bastian Koppelmann (5):
target/tricore: Use DisasContextBase API
target-tricore: Make env a member of DisasContext
target/tricore: Use translate_loop
target/tricore: Implement a qemu excptions helper
target/tricore: Fix tricore_tr_translate_insn
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 7 +
target/tricore/translate.c | 581 ++++++++++++++++++++-----------------
3 files changed, 326 insertions(+), 263 deletions(-)
--
2.23.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann @ 2019-08-21 12:23 ` Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 2/5] target-tricore: Make env a member of DisasContext Bastian Koppelmann ` (6 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson this gets rid of the copied fields of TriCore's DisasContext and now uses the shared DisasContextBase, which is necessary for the conversion to translate_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 98 +++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index dc2a65f3f9..ca67b6cd4c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -30,6 +30,7 @@ #include "exec/helper-gen.h" #include "tricore-opcodes.h" +#include "exec/translator.h" #include "exec/log.h" /* @@ -64,24 +65,14 @@ static const char *regnames_d[] = { }; typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc, next_pc; + DisasContextBase base; + target_ulong pc_succ_insn; uint32_t opcode; - int singlestep_enabled; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; - int bstate; } DisasContext; -enum { - - BS_NONE = 0, - BS_STOP = 1, - BS_BRANCH = 2, - BS_EXCP = 3, -}; - enum { MODE_LL = 0, MODE_LU = 1, @@ -3230,12 +3221,12 @@ static inline void gen_save_pc(target_ulong pc) static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; #endif @@ -3246,10 +3237,10 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); gen_save_pc(dest); - tcg_gen_exit_tb(ctx->tb, n); + tcg_gen_exit_tb(ctx->base.tb, n); } else { gen_save_pc(dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { /* raise exception debug */ } tcg_gen_exit_tb(NULL, 0); @@ -3261,9 +3252,9 @@ static void generate_trap(DisasContext *ctx, int class, int tin) TCGv_i32 classtemp = tcg_const_i32(class); TCGv_i32 tintemp = tcg_const_i32(tin); - gen_save_pc(ctx->pc); + gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); - ctx->bstate = BS_EXCP; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(classtemp); tcg_temp_free(tintemp); @@ -3275,10 +3266,10 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, TCGLabel *jumpLabel = gen_new_label(); tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); - gen_goto_tb(ctx, 1, ctx->next_pc); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); gen_set_label(jumpLabel); - gen_goto_tb(ctx, 0, ctx->pc + address * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); } static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, @@ -3295,9 +3286,9 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset) tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); - gen_goto_tb(ctx, 1, ctx->pc + offset); + gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); gen_set_label(l1); - gen_goto_tb(ctx, 0, ctx->next_pc); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); } static void gen_fcall_save_ctx(DisasContext *ctx) @@ -3306,7 +3297,7 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); tcg_temp_free(temp); @@ -3321,7 +3312,7 @@ static void gen_fret(DisasContext *ctx) tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(temp); } @@ -3336,12 +3327,12 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, /* SB-format jumps */ case OPC1_16_SB_J: case OPC1_32_B_J: - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_CALL: case OPC1_16_SB_CALL: - gen_helper_1arg(call, ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_helper_1arg(call, ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_16_SB_JZ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); @@ -3433,26 +3424,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; /* B-format */ case OPC1_32_B_CALLA: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_FCALL: gen_fcall_save_ctx(ctx); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_FCALLA: gen_fcall_save_ctx(ctx); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JLA: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JL: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; /* BOL format */ case OPCM_32_BRC_EQ_NEQ: @@ -3551,7 +3542,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_loop(ctx, r2, offset * 2); } else { /* OPC2_32_BRR_LOOPU */ - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); } break; case OPCM_32_BRR_JNE: @@ -3585,7 +3576,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; } @@ -3933,7 +3924,7 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) case OPC2_16_SR_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ @@ -6557,11 +6548,11 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_JLI: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_CALLI: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_FCALLI: @@ -6572,7 +6563,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; } static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) @@ -8391,7 +8382,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_32_SYS_RFM: if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { @@ -8404,7 +8395,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) gen_helper_rfm(cpu_env); gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(tmp); } else { /* generate privilege trap */ @@ -8790,11 +8781,11 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) == 0) { - ctx->next_pc = ctx->pc + 2; + ctx->pc_succ_insn = ctx->base.pc_next + 2; decode_16Bit_opc(env, ctx); /* 32-Bit Instruction */ } else { - ctx->next_pc = ctx->pc + 4; + ctx->pc_succ_insn = ctx->base.pc_next + 4; decode_32Bit_opc(env, ctx); } } @@ -8807,33 +8798,32 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) int num_insns = 0; pc_start = tb->pc; - ctx.pc = pc_start; - ctx.saved_pc = -1; - ctx.tb = tb; - ctx.singlestep_enabled = cs->singlestep_enabled; - ctx.bstate = BS_NONE; + ctx.base.pc_next = pc_start; + ctx.base.tb = tb; + ctx.base.singlestep_enabled = cs->singlestep_enabled; + ctx.base.is_jmp = DISAS_NEXT; ctx.mem_idx = cpu_mmu_index(env, false); ctx.hflags = (uint32_t)tb->flags; tcg_clear_temp_count(); gen_tb_start(tb); - while (ctx.bstate == BS_NONE) { - tcg_gen_insn_start(ctx.pc); + while (ctx.base.is_jmp == DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; - ctx.opcode = cpu_ldl_code(env, ctx.pc); + ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next); decode_opc(env, &ctx, 0); if (num_insns >= max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.next_pc); + gen_save_pc(ctx.pc_succ_insn); tcg_gen_exit_tb(NULL, 0); break; } - ctx.pc = ctx.next_pc; + ctx.base.pc_next = ctx.pc_succ_insn; } gen_tb_end(tb, num_insns); - tb->size = ctx.pc - pc_start; + tb->size = ctx.base.pc_next - pc_start; tb->icount = num_insns; if (tcg_check_temp_count()) { @@ -8845,7 +8835,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); qemu_log("\n"); qemu_log_unlock(); } -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 2/5] target-tricore: Make env a member of DisasContext 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann @ 2019-08-21 12:23 ` Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop Bastian Koppelmann ` (5 subsequent siblings) 7 siblings, 0 replies; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson otherwise we have to pass env down through all functions which blocks the usage of translator_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 340 ++++++++++++++++++------------------- 1 file changed, 168 insertions(+), 172 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ca67b6cd4c..6b10ae5c47 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -66,6 +66,7 @@ static const char *regnames_d[] = { typedef struct DisasContext { DisasContextBase base; + CPUTriCoreState *env; target_ulong pc_succ_insn; uint32_t opcode; /* Routine used to access memory */ @@ -369,13 +370,13 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) These makros also specify in which ISA version the csfr was introduced. */ #define R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ - if (tricore_feature(env, FEATURE)) { \ + if (tricore_feature(ctx->env, FEATURE)) { \ tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ } \ break; #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) -static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) +static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset) { /* since we're caching PSW make this a special case */ if (offset == 0xfe04) { @@ -394,7 +395,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) since no execption occurs */ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ - if (tricore_feature(env, FEATURE)) { \ + if (tricore_feature(ctx->env, FEATURE)) { \ tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ } \ break; @@ -403,7 +404,7 @@ static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) watchdog device, we handle endinit protected registers like all-access registers for now. */ #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) -static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, +static inline void gen_mtcr(DisasContext *ctx, TCGv r1, int32_t offset) { if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { @@ -1093,7 +1094,7 @@ gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) static inline void gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, - uint32_t up_shift, CPUTriCoreState *env) + uint32_t up_shift) { TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); @@ -1254,7 +1255,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, static inline void gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, - TCGv arg3, uint32_t n, CPUTriCoreState *env) + TCGv arg3, uint32_t n) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -1952,7 +1953,7 @@ gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) static inline void gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, - uint32_t up_shift, CPUTriCoreState *env) + uint32_t up_shift) { TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); @@ -2107,7 +2108,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, static inline void gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, - TCGv arg3, uint32_t n, CPUTriCoreState *env) + TCGv arg3, uint32_t n) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -3153,11 +3154,11 @@ static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) } static inline void -gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) +gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) { TCGv_i64 ret = tcg_temp_new_i64(); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); } else { gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); @@ -3168,11 +3169,11 @@ gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) } static inline void -gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) +gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2) { TCGv_i64 ret = tcg_temp_new_i64(); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); } else { gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); @@ -3584,7 +3585,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, * Functions for decoding instructions */ -static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) +static void decode_src_opc(DisasContext *ctx, int op1) { int r1; int32_t const4; @@ -3646,7 +3647,7 @@ static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) tcg_gen_movi_tl(cpu_gpr_a[r1], const4); break; case OPC1_16_SRC_MOV_E: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { tcg_gen_movi_tl(cpu_gpr_d[r1], const4); tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); } else { @@ -3910,7 +3911,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1) } } -static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sr_system(DisasContext *ctx) { uint32_t op2; op2 = MASK_OP_SR_OP2(ctx->opcode); @@ -3937,7 +3938,7 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sr_accu(DisasContext *ctx) { uint32_t op2; uint32_t r1; @@ -3981,7 +3982,7 @@ static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_16Bit_opc(DisasContext *ctx) { int op1; int r1, r2; @@ -4012,7 +4013,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_16_SRC_MOV_E: case OPC1_16_SRC_SH: case OPC1_16_SRC_SHA: - decode_src_opc(env, ctx, op1); + decode_src_opc(ctx, op1); break; /* SRR-format */ case OPC1_16_SRR_ADD: @@ -4097,7 +4098,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; case OPC1_16_SBC_JEQ2: case OPC1_16_SBC_JNE2: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { address = MASK_OP_SBC_DISP4(ctx->opcode); const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, const16, address); @@ -4115,7 +4116,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) /* SBR-format */ case OPC1_16_SBR_JEQ2: case OPC1_16_SBR_JNE2: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { r1 = MASK_OP_SBR_S2(ctx->opcode); address = MASK_OP_SBR_DISP4(ctx->opcode); gen_compute_branch(ctx, op1, r1, 0, 0, address); @@ -4195,10 +4196,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* SR-format */ case OPCM_16_SR_SYSTEM: - decode_sr_system(env, ctx); + decode_sr_system(ctx); break; case OPCM_16_SR_ACCU: - decode_sr_accu(env, ctx); + decode_sr_accu(ctx); break; case OPC1_16_SR_JI: r1 = MASK_OP_SR_S1D(ctx->opcode); @@ -4218,7 +4219,7 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) */ /* ABS-format */ -static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldw(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4253,7 +4254,7 @@ static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldb(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4286,7 +4287,7 @@ static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldst_swap(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4313,7 +4314,7 @@ static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_ldst_context(DisasContext *ctx) { uint32_t op2; int32_t off18; @@ -4339,7 +4340,7 @@ static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_store(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4373,7 +4374,7 @@ static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_abs_storeb_h(DisasContext *ctx) { int32_t op2; int32_t r1; @@ -4401,7 +4402,7 @@ static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) /* Bit-format */ -static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_andacc(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4442,7 +4443,7 @@ static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_logical_t(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4476,7 +4477,7 @@ static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4499,7 +4500,7 @@ static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_logical_t2(DisasContext *ctx) { uint32_t op2; @@ -4535,7 +4536,7 @@ static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_orand(DisasContext *ctx) { uint32_t op2; @@ -4576,7 +4577,7 @@ static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_sh_logic1(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4617,7 +4618,7 @@ static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) +static void decode_bit_sh_logic2(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -4661,8 +4662,7 @@ static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) /* BO-format */ -static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -4696,13 +4696,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, break; case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF: - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC: - if (tricore_feature(env, TRICORE_FEATURE_131)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4710,7 +4710,7 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, break; case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC: - if (tricore_feature(env, TRICORE_FEATURE_131)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_131)) { tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4821,8 +4821,7 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, } } -static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -4932,8 +4931,7 @@ static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, tcg_temp_free(temp3); } -static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5067,8 +5065,7 @@ static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, } } -static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5186,8 +5183,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, tcg_temp_free(temp3); } -static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5279,8 +5275,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, tcg_temp_free(temp2); } -static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, - DisasContext *ctx) +static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) { uint32_t op2; uint32_t off10; @@ -5342,7 +5337,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, tcg_temp_free(temp3); } -static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) +static void decode_bol_opc(DisasContext *ctx, int32_t op1) { int r1, r2; int32_t address; @@ -5369,7 +5364,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); break; case OPC1_32_BOL_ST_A_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -5379,42 +5374,42 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); break; case OPC1_32_BOL_LD_B_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_BU_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_H_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_LD_HU_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_ST_B_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC1_32_BOL_ST_H_LONGOFF: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -5426,7 +5421,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) } /* RC format */ -static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_logical_shift(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5493,7 +5488,7 @@ static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_accumulator(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5693,7 +5688,7 @@ static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_serviceroutine(DisasContext *ctx) { uint32_t op2; uint32_t const9; @@ -5713,7 +5708,7 @@ static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rc_mul(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5751,7 +5746,7 @@ static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) } /* RCPW format */ -static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcpw_insert(DisasContext *ctx) { uint32_t op2; int r1, r2; @@ -5790,7 +5785,7 @@ static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) /* RCRW format */ -static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcrw_insert(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5835,7 +5830,7 @@ static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) /* RCR format */ -static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_cond_select(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5879,7 +5874,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_madd(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5934,7 +5929,7 @@ static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rcr_msub(DisasContext *ctx) { uint32_t op2; int r1, r3, r4; @@ -5991,7 +5986,7 @@ static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) /* RLC format */ -static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, +static void decode_rlc_opc(DisasContext *ctx, uint32_t op1) { int32_t const16; @@ -6013,13 +6008,13 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, break; case OPC1_32_RLC_MFCR: const16 = MASK_OP_RLC_CONST16(ctx->opcode); - gen_mfcr(env, cpu_gpr_d[r2], const16); + gen_mfcr(ctx, cpu_gpr_d[r2], const16); break; case OPC1_32_RLC_MOV: tcg_gen_movi_tl(cpu_gpr_d[r2], const16); break; case OPC1_32_RLC_MOV_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { CHECK_REG_PAIR(r2); tcg_gen_movi_tl(cpu_gpr_d[r2], const16); tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); @@ -6039,7 +6034,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, break; case OPC1_32_RLC_MTCR: const16 = MASK_OP_RLC_CONST16(ctx->opcode); - gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); + gen_mtcr(ctx, cpu_gpr_d[r1], const16); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -6047,7 +6042,7 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, } /* RR format */ -static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_accumulator(DisasContext *ctx) { uint32_t op2; int r3, r2, r1; @@ -6245,7 +6240,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RR_MOV_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { temp = tcg_temp_new(); CHECK_REG_PAIR(r3); @@ -6259,7 +6254,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) } break; case OPC2_32_RR_MOVS_64: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { CHECK_REG_PAIR(r3); tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); @@ -6389,7 +6384,7 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_logical_shift(DisasContext *ctx) { uint32_t op2; int r3, r2, r1; @@ -6467,7 +6462,7 @@ static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp); } -static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_address(DisasContext *ctx) { uint32_t op2, n; int r1, r2, r3; @@ -6535,7 +6530,7 @@ static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_idirect(DisasContext *ctx) { uint32_t op2; int r1; @@ -6566,7 +6561,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) ctx->base.is_jmp = DISAS_NORETURN; } -static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr_divide(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6588,7 +6583,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) break; case OPC2_32_RR_DVINIT_B: CHECK_REG_PAIR(r3); - gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_DVINIT_BU: @@ -6599,7 +6594,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); /* reset av */ tcg_gen_movi_tl(cpu_PSW_AV, 0); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ tcg_gen_abs_tl(temp, temp3); tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); @@ -6621,7 +6616,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) break; case OPC2_32_RR_DVINIT_H: CHECK_REG_PAIR(r3); - gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], + gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_DVINIT_HU: @@ -6632,7 +6627,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); /* reset av */ tcg_gen_movi_tl(cpu_PSW_AV, 0); - if (!tricore_feature(env, TRICORE_FEATURE_131)) { + if (!tricore_feature(ctx->env, TRICORE_FEATURE_131)) { /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ tcg_gen_abs_tl(temp, temp3); tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]); @@ -6695,14 +6690,14 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; case OPC2_32_RR_CRC32: - if (tricore_feature(env, TRICORE_FEATURE_161)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_161)) { gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; case OPC2_32_RR_DIV: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); } else { @@ -6710,7 +6705,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) } break; case OPC2_32_RR_DIV_U: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2]); } else { @@ -6753,7 +6748,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) } /* RR1 Format */ -static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr1_mul(DisasContext *ctx) { uint32_t op2; @@ -6867,7 +6862,7 @@ static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(n); } -static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr1_mulq(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6939,7 +6934,7 @@ static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) } /* RR2 format */ -static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rr2_mul(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -6976,7 +6971,7 @@ static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) } /* RRPW format */ -static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrpw_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3; @@ -7030,7 +7025,7 @@ static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) } /* RRR format */ -static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr_cond_select(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -7076,7 +7071,7 @@ static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr_divide(DisasContext *ctx) { uint32_t op2; @@ -7156,7 +7151,7 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) } /* RRR2 format */ -static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr2_madd(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4; @@ -7208,7 +7203,7 @@ static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr2_msub(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4; @@ -7260,7 +7255,7 @@ static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) } /* RRR1 format */ -static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_madd(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7406,7 +7401,7 @@ static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_maddq_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7425,19 +7420,19 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) switch (op2) { case OPC2_32_RRR1_MADD_Q_32: gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - cpu_gpr_d[r2], n, 32, env); + cpu_gpr_d[r2], n, 32); break; case OPC2_32_RRR1_MADD_Q_64: CHECK_REG_PAIR(r4); CHECK_REG_PAIR(r3); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_L: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MADD_Q_64_L: CHECK_REG_PAIR(r4); @@ -7445,12 +7440,12 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_U: tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MADD_Q_64_U: CHECK_REG_PAIR(r4); @@ -7458,7 +7453,7 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MADD_Q_32_LL: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); @@ -7586,7 +7581,7 @@ static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp2); } -static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_maddsu_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7744,7 +7739,7 @@ static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msub(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7890,7 +7885,7 @@ static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msubq_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -7909,19 +7904,19 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) switch (op2) { case OPC2_32_RRR1_MSUB_Q_32: gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - cpu_gpr_d[r2], n, 32, env); + cpu_gpr_d[r2], n, 32); break; case OPC2_32_RRR1_MSUB_Q_64: CHECK_REG_PAIR(r4); CHECK_REG_PAIR(r3); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_L: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MSUB_Q_64_L: CHECK_REG_PAIR(r4); @@ -7929,12 +7924,12 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_U: tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], - temp, n, 16, env); + temp, n, 16); break; case OPC2_32_RRR1_MSUB_Q_64_U: CHECK_REG_PAIR(r4); @@ -7942,7 +7937,7 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, - n, env); + n); break; case OPC2_32_RRR1_MSUB_Q_32_LL: tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); @@ -8070,7 +8065,7 @@ static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) tcg_temp_free(temp2); } -static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrr1_msubad_h(DisasContext *ctx) { uint32_t op2; uint32_t r1, r2, r3, r4, n; @@ -8229,7 +8224,7 @@ static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) } /* RRRR format */ -static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrrr_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -8286,7 +8281,7 @@ static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx) } /* RRRW format */ -static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) +static void decode_rrrw_extract_insert(DisasContext *ctx) { uint32_t op2; int r1, r2, r3, r4; @@ -8347,7 +8342,7 @@ static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) } /* SYS Format*/ -static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) +static void decode_sys_interrupts(DisasContext *ctx) { uint32_t op2; uint32_t r1; @@ -8408,7 +8403,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) gen_helper_svlcx(cpu_env); break; case OPC2_32_SYS_RESTORE: - if (tricore_feature(env, TRICORE_FEATURE_16)) { + if (tricore_feature(ctx->env, TRICORE_FEATURE_16)) { if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); @@ -8434,7 +8429,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) +static void decode_32Bit_opc(DisasContext *ctx) { int op1; int32_t r1, r2, r3; @@ -8453,22 +8448,22 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) switch (op1) { /* ABS-format */ case OPCM_32_ABS_LDW: - decode_abs_ldw(env, ctx); + decode_abs_ldw(ctx); break; case OPCM_32_ABS_LDB: - decode_abs_ldb(env, ctx); + decode_abs_ldb(ctx); break; case OPCM_32_ABS_LDMST_SWAP: - decode_abs_ldst_swap(env, ctx); + decode_abs_ldst_swap(ctx); break; case OPCM_32_ABS_LDST_CONTEXT: - decode_abs_ldst_context(env, ctx); + decode_abs_ldst_context(ctx); break; case OPCM_32_ABS_STORE: - decode_abs_store(env, ctx); + decode_abs_store(ctx); break; case OPCM_32_ABS_STOREB_H: - decode_abs_storeb_h(env, ctx); + decode_abs_storeb_h(ctx); break; case OPC1_32_ABS_STOREQ: address = MASK_OP_ABS_OFF18(ctx->opcode); @@ -8528,44 +8523,44 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* Bit-format */ case OPCM_32_BIT_ANDACC: - decode_bit_andacc(env, ctx); + decode_bit_andacc(ctx); break; case OPCM_32_BIT_LOGICAL_T1: - decode_bit_logical_t(env, ctx); + decode_bit_logical_t(ctx); break; case OPCM_32_BIT_INSERT: - decode_bit_insert(env, ctx); + decode_bit_insert(ctx); break; case OPCM_32_BIT_LOGICAL_T2: - decode_bit_logical_t2(env, ctx); + decode_bit_logical_t2(ctx); break; case OPCM_32_BIT_ORAND: - decode_bit_orand(env, ctx); + decode_bit_orand(ctx); break; case OPCM_32_BIT_SH_LOGIC1: - decode_bit_sh_logic1(env, ctx); + decode_bit_sh_logic1(ctx); break; case OPCM_32_BIT_SH_LOGIC2: - decode_bit_sh_logic2(env, ctx); + decode_bit_sh_logic2(ctx); break; /* BO Format */ case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: - decode_bo_addrmode_post_pre_base(env, ctx); + decode_bo_addrmode_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: - decode_bo_addrmode_bitreverse_circular(env, ctx); + decode_bo_addrmode_bitreverse_circular(ctx); break; case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: - decode_bo_addrmode_ld_post_pre_base(env, ctx); + decode_bo_addrmode_ld_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: - decode_bo_addrmode_ld_bitreverse_circular(env, ctx); + decode_bo_addrmode_ld_bitreverse_circular(ctx); break; case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: - decode_bo_addrmode_stctx_post_pre_base(env, ctx); + decode_bo_addrmode_stctx_post_pre_base(ctx); break; case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: - decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); + decode_bo_addrmode_ldmst_bitreverse_circular(ctx); break; /* BOL-format */ case OPC1_32_BOL_LD_A_LONGOFF: @@ -8579,7 +8574,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_BOL_LD_HU_LONGOFF: case OPC1_32_BOL_ST_B_LONGOFF: case OPC1_32_BOL_ST_H_LONGOFF: - decode_bol_opc(env, ctx, op1); + decode_bol_opc(ctx, op1); break; /* BRC Format */ case OPCM_32_BRC_EQ_NEQ: @@ -8612,20 +8607,20 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* RC Format */ case OPCM_32_RC_LOGICAL_SHIFT: - decode_rc_logical_shift(env, ctx); + decode_rc_logical_shift(ctx); break; case OPCM_32_RC_ACCUMULATOR: - decode_rc_accumulator(env, ctx); + decode_rc_accumulator(ctx); break; case OPCM_32_RC_SERVICEROUTINE: - decode_rc_serviceroutine(env, ctx); + decode_rc_serviceroutine(ctx); break; case OPCM_32_RC_MUL: - decode_rc_mul(env, ctx); + decode_rc_mul(ctx); break; /* RCPW Format */ case OPCM_32_RCPW_MASK_INSERT: - decode_rcpw_insert(env, ctx); + decode_rcpw_insert(ctx); break; /* RCRR Format */ case OPC1_32_RCRR_INSERT: @@ -8650,17 +8645,17 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* RCRW Format */ case OPCM_32_RCRW_MASK_INSERT: - decode_rcrw_insert(env, ctx); + decode_rcrw_insert(ctx); break; /* RCR Format */ case OPCM_32_RCR_COND_SELECT: - decode_rcr_cond_select(env, ctx); + decode_rcr_cond_select(ctx); break; case OPCM_32_RCR_MADD: - decode_rcr_madd(env, ctx); + decode_rcr_madd(ctx); break; case OPCM_32_RCR_MSUB: - decode_rcr_msub(env, ctx); + decode_rcr_msub(ctx); break; /* RLC Format */ case OPC1_32_RLC_ADDI: @@ -8673,38 +8668,38 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_RLC_MOV_H: case OPC1_32_RLC_MOVH_A: case OPC1_32_RLC_MTCR: - decode_rlc_opc(env, ctx, op1); + decode_rlc_opc(ctx, op1); break; /* RR Format */ case OPCM_32_RR_ACCUMULATOR: - decode_rr_accumulator(env, ctx); + decode_rr_accumulator(ctx); break; case OPCM_32_RR_LOGICAL_SHIFT: - decode_rr_logical_shift(env, ctx); + decode_rr_logical_shift(ctx); break; case OPCM_32_RR_ADDRESS: - decode_rr_address(env, ctx); + decode_rr_address(ctx); break; case OPCM_32_RR_IDIRECT: - decode_rr_idirect(env, ctx); + decode_rr_idirect(ctx); break; case OPCM_32_RR_DIVIDE: - decode_rr_divide(env, ctx); + decode_rr_divide(ctx); break; /* RR1 Format */ case OPCM_32_RR1_MUL: - decode_rr1_mul(env, ctx); + decode_rr1_mul(ctx); break; case OPCM_32_RR1_MULQ: - decode_rr1_mulq(env, ctx); + decode_rr1_mulq(ctx); break; /* RR2 format */ case OPCM_32_RR2_MUL: - decode_rr2_mul(env, ctx); + decode_rr2_mul(ctx); break; /* RRPW format */ case OPCM_32_RRPW_EXTRACT_INSERT: - decode_rrpw_extract_insert(env, ctx); + decode_rrpw_extract_insert(ctx); break; case OPC1_32_RRPW_DEXTR: r1 = MASK_OP_RRPW_S1(ctx->opcode); @@ -8723,48 +8718,48 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* RRR Format */ case OPCM_32_RRR_COND_SELECT: - decode_rrr_cond_select(env, ctx); + decode_rrr_cond_select(ctx); break; case OPCM_32_RRR_DIVIDE: - decode_rrr_divide(env, ctx); + decode_rrr_divide(ctx); break; /* RRR2 Format */ case OPCM_32_RRR2_MADD: - decode_rrr2_madd(env, ctx); + decode_rrr2_madd(ctx); break; case OPCM_32_RRR2_MSUB: - decode_rrr2_msub(env, ctx); + decode_rrr2_msub(ctx); break; /* RRR1 format */ case OPCM_32_RRR1_MADD: - decode_rrr1_madd(env, ctx); + decode_rrr1_madd(ctx); break; case OPCM_32_RRR1_MADDQ_H: - decode_rrr1_maddq_h(env, ctx); + decode_rrr1_maddq_h(ctx); break; case OPCM_32_RRR1_MADDSU_H: - decode_rrr1_maddsu_h(env, ctx); + decode_rrr1_maddsu_h(ctx); break; case OPCM_32_RRR1_MSUB_H: - decode_rrr1_msub(env, ctx); + decode_rrr1_msub(ctx); break; case OPCM_32_RRR1_MSUB_Q: - decode_rrr1_msubq_h(env, ctx); + decode_rrr1_msubq_h(ctx); break; case OPCM_32_RRR1_MSUBAD_H: - decode_rrr1_msubad_h(env, ctx); + decode_rrr1_msubad_h(ctx); break; /* RRRR format */ case OPCM_32_RRRR_EXTRACT_INSERT: - decode_rrrr_extract_insert(env, ctx); + decode_rrrr_extract_insert(ctx); break; /* RRRW format */ case OPCM_32_RRRW_EXTRACT_INSERT: - decode_rrrw_extract_insert(env, ctx); + decode_rrrw_extract_insert(ctx); break; /* SYS format */ case OPCM_32_SYS_INTERRUPTS: - decode_sys_interrupts(env, ctx); + decode_sys_interrupts(ctx); break; case OPC1_32_SYS_RSTV: tcg_gen_movi_tl(cpu_PSW_V, 0); @@ -8777,16 +8772,16 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) } } -static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) +static void decode_opc(DisasContext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) == 0) { ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_16Bit_opc(env, ctx); + decode_16Bit_opc(ctx); /* 32-Bit Instruction */ } else { ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_32Bit_opc(env, ctx); + decode_32Bit_opc(ctx); } } @@ -8804,6 +8799,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) ctx.base.is_jmp = DISAS_NEXT; ctx.mem_idx = cpu_mmu_index(env, false); ctx.hflags = (uint32_t)tb->flags; + ctx.env = env; tcg_clear_temp_count(); gen_tb_start(tb); @@ -8812,7 +8808,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) num_insns++; ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(env, &ctx, 0); + decode_opc(&ctx, 0); if (num_insns >= max_insns || tcg_op_buf_full()) { gen_save_pc(ctx.pc_succ_insn); -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 2/5] target-tricore: Make env a member of DisasContext Bastian Koppelmann @ 2019-08-21 12:23 ` Bastian Koppelmann 2019-08-21 23:06 ` Richard Henderson 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper Bastian Koppelmann ` (4 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- v1 -> v2: - save hflags in tricore_tr_init_disas_context() target/tricore/translate.c | 118 +++++++++++++++++++++++-------------- 1 file changed, 74 insertions(+), 44 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6b10ae5c47..5fb42abe35 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8772,7 +8772,7 @@ static void decode_32Bit_opc(DisasContext *ctx) } } -static void decode_opc(DisasContext *ctx, int *is_branch) +static void decode_opc(DisasContext *ctx) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) == 0) { @@ -8785,57 +8785,87 @@ static void decode_opc(DisasContext *ctx, int *is_branch) } } -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +static void tricore_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) { + DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUTriCoreState *env = cs->env_ptr; - DisasContext ctx; - target_ulong pc_start; - int num_insns = 0; - - pc_start = tb->pc; - ctx.base.pc_next = pc_start; - ctx.base.tb = tb; - ctx.base.singlestep_enabled = cs->singlestep_enabled; - ctx.base.is_jmp = DISAS_NEXT; - ctx.mem_idx = cpu_mmu_index(env, false); - ctx.hflags = (uint32_t)tb->flags; - ctx.env = env; - - tcg_clear_temp_count(); - gen_tb_start(tb); - while (ctx.base.is_jmp == DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; - - ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(&ctx, 0); - - if (num_insns >= max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.pc_succ_insn); - tcg_gen_exit_tb(NULL, 0); - break; + ctx->mem_idx = cpu_mmu_index(env, false); + ctx->hflags = (uint32_t)ctx->base.tb->flags; +} + +static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + return false; +} + +static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUTriCoreState *env = cpu->env_ptr; + + ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(ctx); + ctx->base.pc_next = ctx->pc_succ_insn; + + if (ctx->base.is_jmp == DISAS_NEXT) { + target_ulong page_start; + + page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + ctx->base.is_jmp = DISAS_TOO_MANY; } - ctx.base.pc_next = ctx.pc_succ_insn; } +} - gen_tb_end(tb, num_insns); - tb->size = ctx.base.pc_next - pc_start; - tb->icount = num_insns; +static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - if (tcg_check_temp_count()) { - printf("LEAK at %08x\n", env->PC); + switch (ctx->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(ctx, 0, ctx->base.pc_next); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); } +} -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +static void tricore_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps tricore_tr_ops = { + .init_disas_context = tricore_tr_init_disas_context, + .tb_start = tricore_tr_tb_start, + .insn_start = tricore_tr_insn_start, + .breakpoint_check = tricore_tr_breakpoint_check, + .translate_insn = tricore_tr_translate_insn, + .tb_stop = tricore_tr_tb_stop, + .disas_log = tricore_tr_disas_log, +}; + + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) +{ + DisasContext ctx; + translator_loop(&tricore_tr_ops, &ctx.base, cs, tb, max_insns); } void -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop Bastian Koppelmann @ 2019-08-21 23:06 ` Richard Henderson 0 siblings, 0 replies; 14+ messages in thread From: Richard Henderson @ 2019-08-21 23:06 UTC (permalink / raw) To: Bastian Koppelmann, qemu-devel; +Cc: david.brenken On 8/21/19 5:23 AM, Bastian Koppelmann wrote: > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > --- > v1 -> v2: > - save hflags in tricore_tr_init_disas_context() > > target/tricore/translate.c | 118 +++++++++++++++++++++++-------------- > 1 file changed, 74 insertions(+), 44 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann ` (2 preceding siblings ...) 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop Bastian Koppelmann @ 2019-08-21 12:23 ` Bastian Koppelmann 2019-08-21 23:05 ` Richard Henderson 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn Bastian Koppelmann ` (3 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson this helper is only used to raise qemu specific exceptions. We use this helper to raise it on breakpoints as well as the TriCore debug insn. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/tricore/helper.h | 1 + target/tricore/op_helper.c | 7 +++++++ target/tricore/translate.c | 24 +++++++++++++++++++++--- 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/target/tricore/helper.h b/target/tricore/helper.h index b64780c37d..78176aa17a 100644 --- a/target/tricore/helper.h +++ b/target/tricore/helper.h @@ -153,3 +153,4 @@ DEF_HELPER_2(psw_write, void, env, i32) DEF_HELPER_1(psw_read, i32, env) /* Exceptions */ DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32) +DEF_HELPER_2(qemu_excp, noreturn, env, i32) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 9476d10d00..32c2bc1699 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -107,6 +107,13 @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class, raise_exception_sync_internal(env, class, tin, pc, 0); } +void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp) +{ + CPUState *cs = env_cpu(env); + cs->exception_index = excp; + cpu_loop_exit(cs); +} + /* Addressing mode helper */ static uint16_t reverse16(uint16_t val) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5fb42abe35..19a0e4554c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3261,6 +3261,15 @@ static void generate_trap(DisasContext *ctx, int class, int tin) tcg_temp_free(tintemp); } +static void generate_qemu_excp(DisasContext *ctx, int excp) +{ + TCGv_i32 tmp = tcg_const_i32(excp); + gen_save_pc(ctx->base.pc_next); + gen_helper_qemu_excp(cpu_env, tmp); + ctx->base.is_jmp = DISAS_NORETURN; + tcg_temp_free(tmp); +} + static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, TCGv r2, int16_t address) { @@ -3928,7 +3937,7 @@ static void decode_sr_system(DisasContext *ctx) ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_16_SR_DEBUG: - /* raise EXCP_DEBUG */ + generate_qemu_excp(ctx, EXCP_DEBUG); break; case OPC2_16_SR_FRET: gen_fret(ctx); @@ -8354,7 +8363,7 @@ static void decode_sys_interrupts(DisasContext *ctx) switch (op2) { case OPC2_32_SYS_DEBUG: - /* raise EXCP_DEBUG */ + generate_qemu_excp(ctx, EXCP_DEBUG); break; case OPC2_32_SYS_DISABLE: tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); @@ -8808,7 +8817,16 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp) { - return false; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + generate_qemu_excp(ctx, EXCP_DEBUG); + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + ctx->base.pc_next += 4; + return true; } static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper Bastian Koppelmann @ 2019-08-21 23:05 ` Richard Henderson 2019-08-21 23:06 ` Richard Henderson 0 siblings, 1 reply; 14+ messages in thread From: Richard Henderson @ 2019-08-21 23:05 UTC (permalink / raw) To: Bastian Koppelmann, qemu-devel; +Cc: david.brenken On 8/21/19 5:23 AM, Bastian Koppelmann wrote: > @@ -3928,7 +3937,7 @@ static void decode_sr_system(DisasContext *ctx) > ctx->base.is_jmp = DISAS_NORETURN; > break; > case OPC2_16_SR_DEBUG: > - /* raise EXCP_DEBUG */ > + generate_qemu_excp(ctx, EXCP_DEBUG); > break; > case OPC2_16_SR_FRET: > gen_fret(ctx); > @@ -8354,7 +8363,7 @@ static void decode_sys_interrupts(DisasContext *ctx) > > switch (op2) { > case OPC2_32_SYS_DEBUG: > - /* raise EXCP_DEBUG */ > + generate_qemu_excp(ctx, EXCP_DEBUG); > break; > case OPC2_32_SYS_DISABLE: > tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); This is not correct -- EXCP_DEBUG is an internal qemu exception. The manual I have only describes the ISA and does not describe what a "Debug Event" would be. I note that you're missing the DBGSR.DE check. I also note that whatever a "Debug Event" is, RFM appears to be the return from it. So one can deduce some things about what it should be. r~ ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper 2019-08-21 23:05 ` Richard Henderson @ 2019-08-21 23:06 ` Richard Henderson 0 siblings, 0 replies; 14+ messages in thread From: Richard Henderson @ 2019-08-21 23:06 UTC (permalink / raw) To: Bastian Koppelmann, qemu-devel; +Cc: david.brenken On 8/21/19 4:05 PM, Richard Henderson wrote: > On 8/21/19 5:23 AM, Bastian Koppelmann wrote: >> @@ -3928,7 +3937,7 @@ static void decode_sr_system(DisasContext *ctx) >> ctx->base.is_jmp = DISAS_NORETURN; >> break; >> case OPC2_16_SR_DEBUG: >> - /* raise EXCP_DEBUG */ >> + generate_qemu_excp(ctx, EXCP_DEBUG); >> break; >> case OPC2_16_SR_FRET: >> gen_fret(ctx); >> @@ -8354,7 +8363,7 @@ static void decode_sys_interrupts(DisasContext *ctx) >> >> switch (op2) { >> case OPC2_32_SYS_DEBUG: >> - /* raise EXCP_DEBUG */ >> + generate_qemu_excp(ctx, EXCP_DEBUG); >> break; >> case OPC2_32_SYS_DISABLE: >> tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); > > This is not correct -- EXCP_DEBUG is an internal qemu exception. > > The manual I have only describes the ISA and does not describe what a "Debug > Event" would be. I note that you're missing the DBGSR.DE check. I also note > that whatever a "Debug Event" is, RFM appears to be the return from it. So one > can deduce some things about what it should be. Anyway, remove these hunks and the rest of the patch is ok. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann ` (3 preceding siblings ...) 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper Bastian Koppelmann @ 2019-08-21 12:23 ` Bastian Koppelmann 2019-08-21 22:54 ` Richard Henderson 2019-08-21 12:43 ` [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) no-reply ` (2 subsequent siblings) 7 siblings, 1 reply; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:23 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson we now fetch 2 bytes first, check whether we have a 32 bit insn, and only then fetch another 2 bytes. We also make sure that a 16 bit insn that still fits into the current page does not end up in the next page. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 47 +++++++++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 19a0e4554c..3ffcf0440e 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8781,17 +8781,9 @@ static void decode_32Bit_opc(DisasContext *ctx) } } -static void decode_opc(DisasContext *ctx) +static bool tricore_insn_is_16bit(uint32_t insn) { - /* 16-Bit Instruction */ - if ((ctx->opcode & 0x1) == 0) { - ctx->pc_succ_insn = ctx->base.pc_next + 2; - decode_16Bit_opc(ctx); - /* 32-Bit Instruction */ - } else { - ctx->pc_succ_insn = ctx->base.pc_next + 4; - decode_32Bit_opc(ctx); - } + return (insn & 0x1) == 0; } static void tricore_tr_init_disas_context(DisasContextBase *dcbase, @@ -8829,20 +8821,49 @@ static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } +static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) +{ + /* + * Return true if the insn at ctx->base.pc_next might cross a page boundary. + * (False positives are OK, false negatives are not.) + * Our caller ensures we are only called if dc->base.pc_next is less than + * 4 bytes from the page boundary, so we cross the page if the first + * 16 bits indicate that this is a 32 bit insn. + */ + uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next); + + return !tricore_insn_is_16bit(insn); +} + + static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUTriCoreState *env = cpu->env_ptr; + uint16_t insn_lo; + bool is_16bit; - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(ctx); + insn_lo = cpu_lduw_code(env, ctx->base.pc_next); + is_16bit = tricore_insn_is_16bit(insn_lo); + if (is_16bit) { + ctx->opcode = insn_lo; + ctx->pc_succ_insn = ctx->base.pc_next + 2; + decode_16Bit_opc(ctx); + } else { + uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2); + ctx->opcode = insn_hi << 16 | insn_lo; + ctx->pc_succ_insn = ctx->base.pc_next + 4; + decode_32Bit_opc(ctx); + } ctx->base.pc_next = ctx->pc_succ_insn; if (ctx->base.is_jmp == DISAS_NEXT) { target_ulong page_start; page_start = ctx->base.pc_first & TARGET_PAGE_MASK; - if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE + || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3 + && insn_crosses_page(env, ctx))) { ctx->base.is_jmp = DISAS_TOO_MANY; } } -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn Bastian Koppelmann @ 2019-08-21 22:54 ` Richard Henderson 0 siblings, 0 replies; 14+ messages in thread From: Richard Henderson @ 2019-08-21 22:54 UTC (permalink / raw) To: Bastian Koppelmann, qemu-devel; +Cc: david.brenken On 8/21/19 5:23 AM, Bastian Koppelmann wrote: > we now fetch 2 bytes first, check whether we have a 32 bit insn, and only then > fetch another 2 bytes. We also make sure that a 16 bit insn that still fits > into the current page does not end up in the next page. > > Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > --- > target/tricore/translate.c | 47 +++++++++++++++++++++++++++----------- > 1 file changed, 34 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann ` (4 preceding siblings ...) 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn Bastian Koppelmann @ 2019-08-21 12:43 ` no-reply 2019-08-21 23:08 ` no-reply 2019-08-21 23:19 ` no-reply 7 siblings, 0 replies; 14+ messages in thread From: no-reply @ 2019-08-21 12:43 UTC (permalink / raw) To: kbastian; +Cc: kbastian, david.brenken, richard.henderson, qemu-devel Patchew URL: https://patchew.org/QEMU/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Message-id: 20190821122315.18015-1-kbastian@mail.uni-paderborn.de === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de -> patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone' Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc' Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers' Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF' Submodule 'roms/edk2' (https://git.qemu.org/git/edk2.git) registered for path 'roms/edk2' Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe' Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios' Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware' Submodule 'roms/opensbi' (https://git.qemu.org/git/opensbi.git) registered for path 'roms/opensbi' Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode' Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios' Submodule 'roms/seabios-hppa' (https://git.qemu.org/git/seabios-hppa.git) registered for path 'roms/seabios-hppa' Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios' Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot' Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot' Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex' Submodule 'slirp' (https://git.qemu.org/git/libslirp.git) registered for path 'slirp' Submodule 'tests/fp/berkeley-softfloat-3' (https://git.qemu.org/git/berkeley-softfloat-3.git) registered for path 'tests/fp/berkeley-softfloat-3' Submodule 'tests/fp/berkeley-testfloat-3' (https://git.qemu.org/git/berkeley-testfloat-3.git) registered for path 'tests/fp/berkeley-testfloat-3' Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into 'capstone'... Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf' Cloning into 'dtc'... Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536' Cloning into 'roms/QemuMacDrivers'... Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266' Cloning into 'roms/SLOF'... Submodule path 'roms/SLOF': checked out 'ba1ab360eebe6338bb8d7d83a9220ccf7e213af3' Cloning into 'roms/edk2'... Submodule path 'roms/edk2': checked out '20d2e5a125e34fc8501026613a71549b2a1a3e54' Submodule 'SoftFloat' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3' Submodule 'CryptoPkg/Library/OpensslLib/openssl' (https://github.com/openssl/openssl) registered for path 'CryptoPkg/Library/OpensslLib/openssl' Cloning into 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'... Submodule path 'roms/edk2/ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'CryptoPkg/Library/OpensslLib/openssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl': checked out '50eaac9f3337667259de725451f201e784599687' Submodule 'boringssl' (https://boringssl.googlesource.com/boringssl) registered for path 'boringssl' Submodule 'krb5' (https://github.com/krb5/krb5) registered for path 'krb5' Submodule 'pyca.cryptography' (https://github.com/pyca/cryptography.git) registered for path 'pyca-cryptography' Cloning into 'boringssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/boringssl': checked out '2070f8ad9151dc8f3a73bffaa146b5e6937a583f' Cloning into 'krb5'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/krb5': checked out 'b9ad6c49505c96a088326b62a52568e3484f2168' Cloning into 'pyca-cryptography'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/pyca-cryptography': checked out '09403100de2f6f1cdd0d484dcb8e620f1c335c8f' Cloning into 'roms/ipxe'... Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17' Cloning into 'roms/openbios'... Submodule path 'roms/openbios': checked out 'c79e0ecb84f4f1ee3f73f521622e264edd1bf174' Cloning into 'roms/openhackware'... Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5' Cloning into 'roms/opensbi'... Submodule path 'roms/opensbi': checked out 'ce228ee0919deb9957192d723eecc8aaae2697c6' Cloning into 'roms/qemu-palcode'... Submodule path 'roms/qemu-palcode': checked out 'bf0e13698872450164fa7040da36a95d2d4b326f' Cloning into 'roms/seabios'... Submodule path 'roms/seabios': checked out 'a5cab58e9a3fb6e168aba919c5669bea406573b4' Cloning into 'roms/seabios-hppa'... Submodule path 'roms/seabios-hppa': checked out '0f4fe84658165e96ce35870fd19fc634e182e77b' Cloning into 'roms/sgabios'... Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a' Cloning into 'roms/skiboot'... Submodule path 'roms/skiboot': checked out '261ca8e779e5138869a45f174caa49be6a274501' Cloning into 'roms/u-boot'... Submodule path 'roms/u-boot': checked out 'd3689267f92c5956e09cc7d1baa4700141662bff' Cloning into 'roms/u-boot-sam460ex'... Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588' Cloning into 'slirp'... Submodule path 'slirp': checked out '126c04acbabd7ad32c2b018fe10dfac2a3bc1210' Cloning into 'tests/fp/berkeley-softfloat-3'... Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'tests/fp/berkeley-testfloat-3'... Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3' Cloning into 'ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' Switched to a new branch 'test' 1c56066 target/tricore: Fix tricore_tr_translate_insn b004f7c target/tricore: Implement a qemu excptions helper 4e13f68 target/tricore: Use translate_loop b76f7f0 target-tricore: Make env a member of DisasContext 72e431d target/tricore: Use DisasContextBase API === OUTPUT BEGIN === 1/5 Checking commit 72e431d244d3 (target/tricore: Use DisasContextBase API) 2/5 Checking commit b76f7f0cebe8 (target-tricore: Make env a member of DisasContext) ERROR: spaces required around that '+' (ctx:VxV) #661: FILE: target/tricore/translate.c:6586: + gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ ERROR: spaces required around that '+' (ctx:VxV) #679: FILE: target/tricore/translate.c:6619: + gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ total: 2 errors, 0 warnings, 1154 lines checked Patch 2/5 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/5 Checking commit 4e13f688cfcd (target/tricore: Use translate_loop) 4/5 Checking commit b004f7c5ace7 (target/tricore: Implement a qemu excptions helper) 5/5 Checking commit 1c5606667696 (target/tricore: Fix tricore_tr_translate_insn) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann ` (5 preceding siblings ...) 2019-08-21 12:43 ` [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) no-reply @ 2019-08-21 23:08 ` no-reply 2019-08-21 23:19 ` no-reply 7 siblings, 0 replies; 14+ messages in thread From: no-reply @ 2019-08-21 23:08 UTC (permalink / raw) To: kbastian; +Cc: kbastian, david.brenken, richard.henderson, qemu-devel Patchew URL: https://patchew.org/QEMU/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Message-id: 20190821122315.18015-1-kbastian@mail.uni-paderborn.de === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu - [tag update] patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de -> patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone' Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc' Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers' Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF' Submodule 'roms/edk2' (https://git.qemu.org/git/edk2.git) registered for path 'roms/edk2' Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe' Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios' Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware' Submodule 'roms/opensbi' (https://git.qemu.org/git/opensbi.git) registered for path 'roms/opensbi' Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode' Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios' Submodule 'roms/seabios-hppa' (https://git.qemu.org/git/seabios-hppa.git) registered for path 'roms/seabios-hppa' Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios' Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot' Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot' Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex' Submodule 'slirp' (https://git.qemu.org/git/libslirp.git) registered for path 'slirp' Submodule 'tests/fp/berkeley-softfloat-3' (https://git.qemu.org/git/berkeley-softfloat-3.git) registered for path 'tests/fp/berkeley-softfloat-3' Submodule 'tests/fp/berkeley-testfloat-3' (https://git.qemu.org/git/berkeley-testfloat-3.git) registered for path 'tests/fp/berkeley-testfloat-3' Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into 'capstone'... Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf' Cloning into 'dtc'... Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536' Cloning into 'roms/QemuMacDrivers'... Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266' Cloning into 'roms/SLOF'... Submodule path 'roms/SLOF': checked out '7bfe584e321946771692711ff83ad2b5850daca7' Cloning into 'roms/edk2'... Submodule path 'roms/edk2': checked out '20d2e5a125e34fc8501026613a71549b2a1a3e54' Submodule 'SoftFloat' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3' Submodule 'CryptoPkg/Library/OpensslLib/openssl' (https://github.com/openssl/openssl) registered for path 'CryptoPkg/Library/OpensslLib/openssl' Cloning into 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'... Submodule path 'roms/edk2/ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'CryptoPkg/Library/OpensslLib/openssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl': checked out '50eaac9f3337667259de725451f201e784599687' Submodule 'boringssl' (https://boringssl.googlesource.com/boringssl) registered for path 'boringssl' Submodule 'krb5' (https://github.com/krb5/krb5) registered for path 'krb5' Submodule 'pyca.cryptography' (https://github.com/pyca/cryptography.git) registered for path 'pyca-cryptography' Cloning into 'boringssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/boringssl': checked out '2070f8ad9151dc8f3a73bffaa146b5e6937a583f' Cloning into 'krb5'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/krb5': checked out 'b9ad6c49505c96a088326b62a52568e3484f2168' Cloning into 'pyca-cryptography'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/pyca-cryptography': checked out '09403100de2f6f1cdd0d484dcb8e620f1c335c8f' Cloning into 'roms/ipxe'... Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17' Cloning into 'roms/openbios'... Submodule path 'roms/openbios': checked out 'c79e0ecb84f4f1ee3f73f521622e264edd1bf174' Cloning into 'roms/openhackware'... Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5' Cloning into 'roms/opensbi'... Submodule path 'roms/opensbi': checked out 'ce228ee0919deb9957192d723eecc8aaae2697c6' Cloning into 'roms/qemu-palcode'... Submodule path 'roms/qemu-palcode': checked out 'bf0e13698872450164fa7040da36a95d2d4b326f' Cloning into 'roms/seabios'... Submodule path 'roms/seabios': checked out 'a5cab58e9a3fb6e168aba919c5669bea406573b4' Cloning into 'roms/seabios-hppa'... Submodule path 'roms/seabios-hppa': checked out '0f4fe84658165e96ce35870fd19fc634e182e77b' Cloning into 'roms/sgabios'... Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a' Cloning into 'roms/skiboot'... Submodule path 'roms/skiboot': checked out '261ca8e779e5138869a45f174caa49be6a274501' Cloning into 'roms/u-boot'... Submodule path 'roms/u-boot': checked out 'd3689267f92c5956e09cc7d1baa4700141662bff' Cloning into 'roms/u-boot-sam460ex'... Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588' Cloning into 'slirp'... Submodule path 'slirp': checked out '126c04acbabd7ad32c2b018fe10dfac2a3bc1210' Cloning into 'tests/fp/berkeley-softfloat-3'... Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'tests/fp/berkeley-testfloat-3'... Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3' Cloning into 'ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' Switched to a new branch 'test' ef20911 target/tricore: Fix tricore_tr_translate_insn e11b338 target/tricore: Implement a qemu excptions helper 229f53f target/tricore: Use translate_loop cd21ab5 target-tricore: Make env a member of DisasContext 914b4d7 target/tricore: Use DisasContextBase API === OUTPUT BEGIN === 1/5 Checking commit 914b4d76345c (target/tricore: Use DisasContextBase API) 2/5 Checking commit cd21ab55ca1e (target-tricore: Make env a member of DisasContext) ERROR: spaces required around that '+' (ctx:VxV) #661: FILE: target/tricore/translate.c:6586: + gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ ERROR: spaces required around that '+' (ctx:VxV) #679: FILE: target/tricore/translate.c:6619: + gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ total: 2 errors, 0 warnings, 1154 lines checked Patch 2/5 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/5 Checking commit 229f53fdd99c (target/tricore: Use translate_loop) 4/5 Checking commit e11b338cb79a (target/tricore: Implement a qemu excptions helper) 5/5 Checking commit ef2091146b25 (target/tricore: Fix tricore_tr_translate_insn) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann ` (6 preceding siblings ...) 2019-08-21 23:08 ` no-reply @ 2019-08-21 23:19 ` no-reply 7 siblings, 0 replies; 14+ messages in thread From: no-reply @ 2019-08-21 23:19 UTC (permalink / raw) To: kbastian; +Cc: kbastian, david.brenken, richard.henderson, qemu-devel Patchew URL: https://patchew.org/QEMU/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Subject: [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Message-id: 20190821122315.18015-1-kbastian@mail.uni-paderborn.de === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu - [tag update] patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de -> patchew/20190821122315.18015-1-kbastian@mail.uni-paderborn.de Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone' Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc' Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers' Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF' Submodule 'roms/edk2' (https://git.qemu.org/git/edk2.git) registered for path 'roms/edk2' Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe' Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios' Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware' Submodule 'roms/opensbi' (https://git.qemu.org/git/opensbi.git) registered for path 'roms/opensbi' Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode' Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios' Submodule 'roms/seabios-hppa' (https://git.qemu.org/git/seabios-hppa.git) registered for path 'roms/seabios-hppa' Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios' Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot' Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot' Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex' Submodule 'slirp' (https://git.qemu.org/git/libslirp.git) registered for path 'slirp' Submodule 'tests/fp/berkeley-softfloat-3' (https://git.qemu.org/git/berkeley-softfloat-3.git) registered for path 'tests/fp/berkeley-softfloat-3' Submodule 'tests/fp/berkeley-testfloat-3' (https://git.qemu.org/git/berkeley-testfloat-3.git) registered for path 'tests/fp/berkeley-testfloat-3' Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into 'capstone'... Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf' Cloning into 'dtc'... Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536' Cloning into 'roms/QemuMacDrivers'... Submodule path 'roms/QemuMacDrivers': checked out '90c488d5f4a407342247b9ea869df1c2d9c8e266' Cloning into 'roms/SLOF'... Submodule path 'roms/SLOF': checked out '7bfe584e321946771692711ff83ad2b5850daca7' Cloning into 'roms/edk2'... Submodule path 'roms/edk2': checked out '20d2e5a125e34fc8501026613a71549b2a1a3e54' Submodule 'SoftFloat' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3' Submodule 'CryptoPkg/Library/OpensslLib/openssl' (https://github.com/openssl/openssl) registered for path 'CryptoPkg/Library/OpensslLib/openssl' Cloning into 'ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3'... Submodule path 'roms/edk2/ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'CryptoPkg/Library/OpensslLib/openssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl': checked out '50eaac9f3337667259de725451f201e784599687' Submodule 'boringssl' (https://boringssl.googlesource.com/boringssl) registered for path 'boringssl' Submodule 'krb5' (https://github.com/krb5/krb5) registered for path 'krb5' Submodule 'pyca.cryptography' (https://github.com/pyca/cryptography.git) registered for path 'pyca-cryptography' Cloning into 'boringssl'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/boringssl': checked out '2070f8ad9151dc8f3a73bffaa146b5e6937a583f' Cloning into 'krb5'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/krb5': checked out 'b9ad6c49505c96a088326b62a52568e3484f2168' Cloning into 'pyca-cryptography'... Submodule path 'roms/edk2/CryptoPkg/Library/OpensslLib/openssl/pyca-cryptography': checked out '09403100de2f6f1cdd0d484dcb8e620f1c335c8f' Cloning into 'roms/ipxe'... Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17' Cloning into 'roms/openbios'... Submodule path 'roms/openbios': checked out 'c79e0ecb84f4f1ee3f73f521622e264edd1bf174' Cloning into 'roms/openhackware'... Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5' Cloning into 'roms/opensbi'... Submodule path 'roms/opensbi': checked out 'ce228ee0919deb9957192d723eecc8aaae2697c6' Cloning into 'roms/qemu-palcode'... Submodule path 'roms/qemu-palcode': checked out 'bf0e13698872450164fa7040da36a95d2d4b326f' Cloning into 'roms/seabios'... Submodule path 'roms/seabios': checked out 'a5cab58e9a3fb6e168aba919c5669bea406573b4' Cloning into 'roms/seabios-hppa'... Submodule path 'roms/seabios-hppa': checked out '0f4fe84658165e96ce35870fd19fc634e182e77b' Cloning into 'roms/sgabios'... Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a' Cloning into 'roms/skiboot'... Submodule path 'roms/skiboot': checked out '261ca8e779e5138869a45f174caa49be6a274501' Cloning into 'roms/u-boot'... Submodule path 'roms/u-boot': checked out 'd3689267f92c5956e09cc7d1baa4700141662bff' Cloning into 'roms/u-boot-sam460ex'... Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588' Cloning into 'slirp'... Submodule path 'slirp': checked out '126c04acbabd7ad32c2b018fe10dfac2a3bc1210' Cloning into 'tests/fp/berkeley-softfloat-3'... Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037' Cloning into 'tests/fp/berkeley-testfloat-3'... Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3' Cloning into 'ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' Switched to a new branch 'test' 5291b2d target/tricore: Fix tricore_tr_translate_insn 8fd6f1d target/tricore: Implement a qemu excptions helper 01b3158 target/tricore: Use translate_loop f1f4d25 target-tricore: Make env a member of DisasContext e2b0e1d target/tricore: Use DisasContextBase API === OUTPUT BEGIN === 1/5 Checking commit e2b0e1d07b2c (target/tricore: Use DisasContextBase API) 2/5 Checking commit f1f4d257e448 (target-tricore: Make env a member of DisasContext) ERROR: spaces required around that '+' (ctx:VxV) #661: FILE: target/tricore/translate.c:6586: + gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ ERROR: spaces required around that '+' (ctx:VxV) #679: FILE: target/tricore/translate.c:6619: + gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], ^ total: 2 errors, 0 warnings, 1154 lines checked Patch 2/5 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/5 Checking commit 01b3158621aa (target/tricore: Use translate_loop) 4/5 Checking commit 8fd6f1de4d18 (target/tricore: Implement a qemu excptions helper) 5/5 Checking commit 5291b2d179a4 (target/tricore: Fix tricore_tr_translate_insn) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190821122315.18015-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com ^ permalink raw reply [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop
@ 2019-08-21 12:20 Bastian Koppelmann
2019-08-21 12:20 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann
0 siblings, 1 reply; 14+ messages in thread
From: Bastian Koppelmann @ 2019-08-21 12:20 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson
Hi,
I finally came around to port TriCore to the "new" translate_loop
infrastructure. This is necessary such that TriCore can be used in the upcoming
plugin API [1].
Cheers,
Bastian
[1] (https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg03165.html)
v1 -> v2:
[03/05] Now also save hflags in tricore_tr_init_disas_context()
[04/05] New patch that raises EXCP_DEBUG for breakpoints, TriCore debug insns
[05/05] New patch that properly fetches 16 bit insns and does the page
boundary check.
Bastian Koppelmann (5):
target/tricore: Use DisasContextBase API
target-tricore: Make env a member of DisasContext
target/tricore: Use translate_loop
target/tricore: Implement a qemu excptions helper
target/tricore: Fix tricore_tr_translate_insn
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 7 +
target/tricore/translate.c | 581 ++++++++++++++++++++-----------------
3 files changed, 326 insertions(+), 263 deletions(-)
--
2.23.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API 2019-08-21 12:20 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop Bastian Koppelmann @ 2019-08-21 12:20 ` Bastian Koppelmann 0 siblings, 0 replies; 14+ messages in thread From: Bastian Koppelmann @ 2019-08-21 12:20 UTC (permalink / raw) To: qemu-devel; +Cc: kbastian, david.brenken, richard.henderson this gets rid of the copied fields of TriCore's DisasContext and now uses the shared DisasContextBase, which is necessary for the conversion to translate_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 98 +++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index dc2a65f3f9..ca67b6cd4c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -30,6 +30,7 @@ #include "exec/helper-gen.h" #include "tricore-opcodes.h" +#include "exec/translator.h" #include "exec/log.h" /* @@ -64,24 +65,14 @@ static const char *regnames_d[] = { }; typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc, saved_pc, next_pc; + DisasContextBase base; + target_ulong pc_succ_insn; uint32_t opcode; - int singlestep_enabled; /* Routine used to access memory */ int mem_idx; uint32_t hflags, saved_hflags; - int bstate; } DisasContext; -enum { - - BS_NONE = 0, - BS_STOP = 1, - BS_BRANCH = 2, - BS_EXCP = 3, -}; - enum { MODE_LL = 0, MODE_LU = 1, @@ -3230,12 +3221,12 @@ static inline void gen_save_pc(target_ulong pc) static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { - if (unlikely(ctx->singlestep_enabled)) { + if (unlikely(ctx->base.singlestep_enabled)) { return false; } #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; #endif @@ -3246,10 +3237,10 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); gen_save_pc(dest); - tcg_gen_exit_tb(ctx->tb, n); + tcg_gen_exit_tb(ctx->base.tb, n); } else { gen_save_pc(dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { /* raise exception debug */ } tcg_gen_exit_tb(NULL, 0); @@ -3261,9 +3252,9 @@ static void generate_trap(DisasContext *ctx, int class, int tin) TCGv_i32 classtemp = tcg_const_i32(class); TCGv_i32 tintemp = tcg_const_i32(tin); - gen_save_pc(ctx->pc); + gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); - ctx->bstate = BS_EXCP; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(classtemp); tcg_temp_free(tintemp); @@ -3275,10 +3266,10 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, TCGLabel *jumpLabel = gen_new_label(); tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); - gen_goto_tb(ctx, 1, ctx->next_pc); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); gen_set_label(jumpLabel); - gen_goto_tb(ctx, 0, ctx->pc + address * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2); } static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, @@ -3295,9 +3286,9 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset) tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); - gen_goto_tb(ctx, 1, ctx->pc + offset); + gen_goto_tb(ctx, 1, ctx->base.pc_next + offset); gen_set_label(l1); - gen_goto_tb(ctx, 0, ctx->next_pc); + gen_goto_tb(ctx, 0, ctx->pc_succ_insn); } static void gen_fcall_save_ctx(DisasContext *ctx) @@ -3306,7 +3297,7 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); tcg_temp_free(temp); @@ -3321,7 +3312,7 @@ static void gen_fret(DisasContext *ctx) tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(temp); } @@ -3336,12 +3327,12 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, /* SB-format jumps */ case OPC1_16_SB_J: case OPC1_32_B_J: - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_CALL: case OPC1_16_SB_CALL: - gen_helper_1arg(call, ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_helper_1arg(call, ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_16_SB_JZ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); @@ -3433,26 +3424,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; /* B-format */ case OPC1_32_B_CALLA: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_FCALL: gen_fcall_save_ctx(ctx); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; case OPC1_32_B_FCALLA: gen_fcall_save_ctx(ctx); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JLA: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); /* fall through */ case OPC1_32_B_JA: gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; case OPC1_32_B_JL: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); break; /* BOL format */ case OPCM_32_BRC_EQ_NEQ: @@ -3551,7 +3542,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_loop(ctx, r2, offset * 2); } else { /* OPC2_32_BRR_LOOPU */ - gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2); } break; case OPCM_32_BRR_JNE: @@ -3585,7 +3576,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; } @@ -3933,7 +3924,7 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) case OPC2_16_SR_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ @@ -6557,11 +6548,11 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_JLI: - tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_CALLI: - gen_helper_1arg(call, ctx->next_pc); + gen_helper_1arg(call, ctx->pc_succ_insn); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; case OPC2_32_RR_FCALLI: @@ -6572,7 +6563,7 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; } static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) @@ -8391,7 +8382,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; break; case OPC2_32_SYS_RFM: if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { @@ -8404,7 +8395,7 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) gen_helper_rfm(cpu_env); gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); - ctx->bstate = BS_BRANCH; + ctx->base.is_jmp = DISAS_NORETURN; tcg_temp_free(tmp); } else { /* generate privilege trap */ @@ -8790,11 +8781,11 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) { /* 16-Bit Instruction */ if ((ctx->opcode & 0x1) == 0) { - ctx->next_pc = ctx->pc + 2; + ctx->pc_succ_insn = ctx->base.pc_next + 2; decode_16Bit_opc(env, ctx); /* 32-Bit Instruction */ } else { - ctx->next_pc = ctx->pc + 4; + ctx->pc_succ_insn = ctx->base.pc_next + 4; decode_32Bit_opc(env, ctx); } } @@ -8807,33 +8798,32 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) int num_insns = 0; pc_start = tb->pc; - ctx.pc = pc_start; - ctx.saved_pc = -1; - ctx.tb = tb; - ctx.singlestep_enabled = cs->singlestep_enabled; - ctx.bstate = BS_NONE; + ctx.base.pc_next = pc_start; + ctx.base.tb = tb; + ctx.base.singlestep_enabled = cs->singlestep_enabled; + ctx.base.is_jmp = DISAS_NEXT; ctx.mem_idx = cpu_mmu_index(env, false); ctx.hflags = (uint32_t)tb->flags; tcg_clear_temp_count(); gen_tb_start(tb); - while (ctx.bstate == BS_NONE) { - tcg_gen_insn_start(ctx.pc); + while (ctx.base.is_jmp == DISAS_NEXT) { + tcg_gen_insn_start(ctx.base.pc_next); num_insns++; - ctx.opcode = cpu_ldl_code(env, ctx.pc); + ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next); decode_opc(env, &ctx, 0); if (num_insns >= max_insns || tcg_op_buf_full()) { - gen_save_pc(ctx.next_pc); + gen_save_pc(ctx.pc_succ_insn); tcg_gen_exit_tb(NULL, 0); break; } - ctx.pc = ctx.next_pc; + ctx.base.pc_next = ctx.pc_succ_insn; } gen_tb_end(tb, num_insns); - tb->size = ctx.pc - pc_start; + tb->size = ctx.base.pc_next - pc_start; tb->icount = num_insns; if (tcg_check_temp_count()) { @@ -8845,7 +8835,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start); qemu_log("\n"); qemu_log_unlock(); } -- 2.23.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-08-21 23:20 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-08-21 12:23 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 2/5] target-tricore: Make env a member of DisasContext Bastian Koppelmann 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 3/5] target/tricore: Use translate_loop Bastian Koppelmann 2019-08-21 23:06 ` Richard Henderson 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 4/5] target/tricore: Implement a qemu excptions helper Bastian Koppelmann 2019-08-21 23:05 ` Richard Henderson 2019-08-21 23:06 ` Richard Henderson 2019-08-21 12:23 ` [Qemu-devel] [PATCH v2 5/5] target/tricore: Fix tricore_tr_translate_insn Bastian Koppelmann 2019-08-21 22:54 ` Richard Henderson 2019-08-21 12:43 ` [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop (resend) no-reply 2019-08-21 23:08 ` no-reply 2019-08-21 23:19 ` no-reply -- strict thread matches above, loose matches on Subject: below -- 2019-08-21 12:20 [Qemu-devel] [PATCH v2 0/5] tricore: Convert to translate_loop Bastian Koppelmann 2019-08-21 12:20 ` [Qemu-devel] [PATCH v2 1/5] target/tricore: Use DisasContextBase API Bastian Koppelmann
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