From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
Date: Tue, 10 Sep 2019 12:04:42 -0700 [thread overview]
Message-ID: <20190910190513.21160-17-palmer@sifive.com> (raw)
In-Reply-To: <20190910190513.21160-1-palmer@sifive.com>
From: Bin Meng <bmeng.cn@gmail.com>
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/sifive_u.c | 18 +++++++++---------
hw/riscv/virt.c | 24 ++++++++++++------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0d9ff76a4f..762223c6fe 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -183,7 +183,7 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
- qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
g_free(nodename);
@@ -208,20 +208,20 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
0x0, memmap[SIFIVE_U_GEM].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
ethclk_phandle, ethclk_phandle, ethclk_phandle);
qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
sizeof(ethclk_names));
- qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
- qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
(long)memmap[SIFIVE_U_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
uartclk_phandle = phandle++;
@@ -241,9 +241,9 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
- qemu_fdt_setprop_cells(fdt, nodename, "clocks", uartclk_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
+ qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 78091707dc..6852178bc2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -233,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
(long)memmap[VIRT_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
- FDT_PLIC_ADDR_CELLS);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
+ FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
FDT_PLIC_INT_CELLS);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -247,7 +247,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
- qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
g_free(nodename);
@@ -260,19 +260,19 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
0x0, memmap[VIRT_VIRTIO].size);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
g_free(nodename);
}
nodename = g_strdup_printf("/soc/pci@%lx",
(long) memmap[VIRT_PCIE_ECAM].base);
qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
- FDT_PCI_ADDR_CELLS);
- qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
- FDT_PCI_INT_CELLS);
- qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
+ FDT_PCI_ADDR_CELLS);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
+ FDT_PCI_INT_CELLS);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"pci-host-ecam-generic");
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
@@ -309,8 +309,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
0x0, memmap[VIRT_UART0].base,
0x0, memmap[VIRT_UART0].size);
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
--
2.21.0
next prev parent reply other threads:[~2019-09-11 8:44 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-10 19:04 [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 01/47] riscv: sifive_u: Add support for loading initrd Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 03/47] riscv: sifive_u: Fix clock-names property for ethernet node Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 06/47] riscv: plic: Remove unused interrupt functions Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 07/47] target/riscv: Create function to test if FP is enabled Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 08/47] target/riscv: Update the Hypervisor CSRs to v0.4 Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 09/47] riscv: rv32: Root page table address can be larger than 32-bit Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 10/47] riscv: Add a helper routine for finding firmware Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 11/47] riscv: Resolve full path of the given bios image Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 12/47] riscv: hmp: Add a command to show virtual memory mappings Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property Palmer Dabbelt
2019-09-10 19:04 ` Palmer Dabbelt [this message]
2019-09-10 19:04 ` [Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 18/47] riscv: hw: Change create_fdt() to return void Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate() Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2 Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string Palmer Dabbelt
2019-09-10 19:04 ` [Qemu-devel] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540 Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 42/47] riscv: sifive_u: Fix broken GEM support Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 45/47] target/riscv: Use both register name and ABI name Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 46/47] target/riscv: Fix mstatus dirty mask Palmer Dabbelt
2019-09-10 19:05 ` [Qemu-devel] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Palmer Dabbelt
2019-09-13 9:17 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 Peter Maydell
2019-09-13 14:17 ` Palmer Dabbelt
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