From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com,
hsp.cat7@gmail.com
Subject: [PATCH v7 01/22] tcg/ppc: Introduce Altivec registers
Date: Mon, 30 Sep 2019 13:21:04 -0700 [thread overview]
Message-ID: <20190930202125.21064-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org>
Altivec supports 32 128-bit vector registers, whose names are
by convention v0 through v31.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 11 ++++-
tcg/ppc/tcg-target.inc.c | 88 +++++++++++++++++++++++++---------------
2 files changed, 65 insertions(+), 34 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 7627fb62d3..690fa744e1 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -31,7 +31,7 @@
# define TCG_TARGET_REG_BITS 32
#endif
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -45,6 +45,15 @@ typedef enum {
TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
TCG_REG_CALL_STACK = TCG_REG_R1,
TCG_AREG0 = TCG_REG_R27
} TCGReg;
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 815edac077..9d678c3bf1 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -42,6 +42,9 @@
# define TCG_REG_TMP1 TCG_REG_R12
#endif
+#define TCG_VEC_TMP1 TCG_REG_V0
+#define TCG_VEC_TMP2 TCG_REG_V1
+
#define TCG_REG_TB TCG_REG_R31
#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
@@ -72,39 +75,15 @@ bool have_isa_3_00;
#endif
#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "r0",
- "r1",
- "r2",
- "r3",
- "r4",
- "r5",
- "r6",
- "r7",
- "r8",
- "r9",
- "r10",
- "r11",
- "r12",
- "r13",
- "r14",
- "r15",
- "r16",
- "r17",
- "r18",
- "r19",
- "r20",
- "r21",
- "r22",
- "r23",
- "r24",
- "r25",
- "r26",
- "r27",
- "r28",
- "r29",
- "r30",
- "r31"
+static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
};
#endif
@@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
+
+ /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
+ TCG_REG_V2, /* call clobbered, vectors */
+ TCG_REG_V3,
+ TCG_REG_V4,
+ TCG_REG_V5,
+ TCG_REG_V6,
+ TCG_REG_V7,
+ TCG_REG_V8,
+ TCG_REG_V9,
+ TCG_REG_V10,
+ TCG_REG_V11,
+ TCG_REG_V12,
+ TCG_REG_V13,
+ TCG_REG_V14,
+ TCG_REG_V15,
+ TCG_REG_V16,
+ TCG_REG_V17,
+ TCG_REG_V18,
+ TCG_REG_V19,
};
static const int tcg_target_call_iarg_regs[] = {
@@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
+
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
@@ -2818,6 +2838,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
#endif
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
if (USE_REG_TB) {
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
}
--
2.17.1
next prev parent reply other threads:[~2019-09-30 20:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-30 20:21 [PATCH v7 00/22] tcg/ppc: Add vector opcodes Richard Henderson
2019-09-30 20:21 ` Richard Henderson [this message]
2019-09-30 20:21 ` [PATCH v7 02/22] tcg/ppc: Introduce macro VX4() Richard Henderson
2019-09-30 20:21 ` [PATCH v7 03/22] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() Richard Henderson
2019-09-30 20:21 ` [PATCH v7 04/22] tcg/ppc: Create TCGPowerISA and have_isa Richard Henderson
2019-09-30 20:21 ` [PATCH v7 05/22] tcg/ppc: Replace HAVE_ISA_2_06 Richard Henderson
2019-09-30 20:21 ` [PATCH v7 06/22] tcg/ppc: Replace HAVE_ISEL macro with a variable Richard Henderson
2019-09-30 20:21 ` [PATCH v7 07/22] tcg/ppc: Enable tcg backend vector compilation Richard Henderson
2019-09-30 20:21 ` [PATCH v7 08/22] tcg/ppc: Add support for load/store/logic/comparison Richard Henderson
2019-09-30 20:21 ` [PATCH v7 09/22] tcg/ppc: Add support for vector maximum/minimum Richard Henderson
2019-09-30 20:21 ` [PATCH v7 10/22] tcg/ppc: Add support for vector add/subtract Richard Henderson
2019-09-30 20:21 ` [PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract Richard Henderson
2019-09-30 20:21 ` [PATCH v7 12/22] tcg/ppc: Support vector shift by immediate Richard Henderson
2019-09-30 20:21 ` [PATCH v7 13/22] tcg/ppc: Support vector multiply Richard Henderson
2019-09-30 20:21 ` [PATCH v7 14/22] tcg/ppc: Support vector dup2 Richard Henderson
2019-09-30 20:21 ` [PATCH v7 15/22] tcg/ppc: Enable Altivec detection Richard Henderson
2019-09-30 20:21 ` [PATCH v7 16/22] tcg/ppc: Update vector support for VSX Richard Henderson
2019-09-30 20:21 ` [PATCH v7 17/22] tcg/ppc: Update vector support for v2.07 Altivec Richard Henderson
2019-09-30 20:21 ` [PATCH v7 18/22] tcg/ppc: Update vector support for v2.07 VSX Richard Henderson
2019-09-30 20:21 ` [PATCH v7 19/22] tcg/ppc: Update vector support for v2.07 FP Richard Henderson
2019-09-30 20:21 ` [PATCH v7 20/22] tcg/ppc: Update vector support for v3.00 Altivec Richard Henderson
2019-09-30 20:21 ` [PATCH v7 21/22] tcg/ppc: Update vector support for v3.00 load/store Richard Henderson
2019-09-30 20:21 ` [PATCH v7 22/22] tcg/ppc: Update vector support for v3.00 dup/dupi Richard Henderson
2019-09-30 21:46 ` [PATCH v7 00/22] tcg/ppc: Add vector opcodes no-reply
2019-10-01 20:33 ` Mark Cave-Ayland
2019-10-02 9:34 ` Aleksandar Markovic
2019-10-14 0:25 ` David Gibson
2019-10-14 3:31 ` Richard Henderson
2019-10-14 3:54 ` David Gibson
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