From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, amarkovic@wavecomp.com,
hsp.cat7@gmail.com
Subject: [PATCH v7 22/22] tcg/ppc: Update vector support for v3.00 dup/dupi
Date: Mon, 30 Sep 2019 13:21:25 -0700 [thread overview]
Message-ID: <20190930202125.21064-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190930202125.21064-1-richard.henderson@linaro.org>
These new instructions are conditional on MSR.VEC for TX=1,
so we can consider these Altivec instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.inc.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 5b7d1bd2dc..d308d69aba 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -596,11 +596,14 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
+#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
+#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
+#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
@@ -931,6 +934,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
return;
}
}
+ if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
+ tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
+ return;
+ }
/*
* Otherwise we must load the value from the constant pool.
@@ -3021,7 +3028,22 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src)
{
tcg_debug_assert(dst >= TCG_REG_V0);
- tcg_debug_assert(src >= TCG_REG_V0);
+
+ /* Splat from integer reg allowed via constraints for v3.00. */
+ if (src < TCG_REG_V0) {
+ tcg_debug_assert(have_isa_3_00);
+ switch (vece) {
+ case MO_64:
+ tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
+ return true;
+ case MO_32:
+ tcg_out32(s, MTVSRWS | VRT(dst) | RA(src));
+ return true;
+ default:
+ /* Fail, so that we fall back on either dupm or mov+dup. */
+ return false;
+ }
+ }
/*
* Recall we use (or emulate) VSX integer loads, so the integer is
@@ -3482,6 +3504,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static const TCGTargetOpDef sub2
= { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
+ static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
static const TCGTargetOpDef v_v_v_v
@@ -3651,8 +3674,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
- case INDEX_op_dup_vec:
return &v_v;
+ case INDEX_op_dup_vec:
+ return have_isa_3_00 ? &v_vr : &v_v;
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
--
2.17.1
next prev parent reply other threads:[~2019-09-30 20:47 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-30 20:21 [PATCH v7 00/22] tcg/ppc: Add vector opcodes Richard Henderson
2019-09-30 20:21 ` [PATCH v7 01/22] tcg/ppc: Introduce Altivec registers Richard Henderson
2019-09-30 20:21 ` [PATCH v7 02/22] tcg/ppc: Introduce macro VX4() Richard Henderson
2019-09-30 20:21 ` [PATCH v7 03/22] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() Richard Henderson
2019-09-30 20:21 ` [PATCH v7 04/22] tcg/ppc: Create TCGPowerISA and have_isa Richard Henderson
2019-09-30 20:21 ` [PATCH v7 05/22] tcg/ppc: Replace HAVE_ISA_2_06 Richard Henderson
2019-09-30 20:21 ` [PATCH v7 06/22] tcg/ppc: Replace HAVE_ISEL macro with a variable Richard Henderson
2019-09-30 20:21 ` [PATCH v7 07/22] tcg/ppc: Enable tcg backend vector compilation Richard Henderson
2019-09-30 20:21 ` [PATCH v7 08/22] tcg/ppc: Add support for load/store/logic/comparison Richard Henderson
2019-09-30 20:21 ` [PATCH v7 09/22] tcg/ppc: Add support for vector maximum/minimum Richard Henderson
2019-09-30 20:21 ` [PATCH v7 10/22] tcg/ppc: Add support for vector add/subtract Richard Henderson
2019-09-30 20:21 ` [PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract Richard Henderson
2019-09-30 20:21 ` [PATCH v7 12/22] tcg/ppc: Support vector shift by immediate Richard Henderson
2019-09-30 20:21 ` [PATCH v7 13/22] tcg/ppc: Support vector multiply Richard Henderson
2019-09-30 20:21 ` [PATCH v7 14/22] tcg/ppc: Support vector dup2 Richard Henderson
2019-09-30 20:21 ` [PATCH v7 15/22] tcg/ppc: Enable Altivec detection Richard Henderson
2019-09-30 20:21 ` [PATCH v7 16/22] tcg/ppc: Update vector support for VSX Richard Henderson
2019-09-30 20:21 ` [PATCH v7 17/22] tcg/ppc: Update vector support for v2.07 Altivec Richard Henderson
2019-09-30 20:21 ` [PATCH v7 18/22] tcg/ppc: Update vector support for v2.07 VSX Richard Henderson
2019-09-30 20:21 ` [PATCH v7 19/22] tcg/ppc: Update vector support for v2.07 FP Richard Henderson
2019-09-30 20:21 ` [PATCH v7 20/22] tcg/ppc: Update vector support for v3.00 Altivec Richard Henderson
2019-09-30 20:21 ` [PATCH v7 21/22] tcg/ppc: Update vector support for v3.00 load/store Richard Henderson
2019-09-30 20:21 ` Richard Henderson [this message]
2019-09-30 21:46 ` [PATCH v7 00/22] tcg/ppc: Add vector opcodes no-reply
2019-10-01 20:33 ` Mark Cave-Ayland
2019-10-02 9:34 ` Aleksandar Markovic
2019-10-14 0:25 ` David Gibson
2019-10-14 3:31 ` Richard Henderson
2019-10-14 3:54 ` David Gibson
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