From: qi1.zhang@intel.com
To: qemu-devel@nongnu.org
Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com,
pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net
Subject: [PATCH v1 0/2] TM field check failed
Date: Tue, 8 Oct 2019 10:34:54 +0800 [thread overview]
Message-ID: <cover.1570498233.git.qi1.zhang@intel.com> (raw)
Message-ID: <20191008023454.f2gdKlmeFfl7Q8n4kKZt8D-xX7S05uk9ZqnbVFmnaM8@z> (raw)
From: "Zhang, Qi" <qi1.zhang@intel.com>
spilt the reserved fields arrays and remove TM field
from reserved bits
Changelog V1:
add descriptons
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 34 insertions(+), 18 deletions(-)
--
2.20.1
next reply other threads:[~2019-10-08 2:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 1:39 qi1.zhang [this message]
2019-10-08 1:39 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-10-08 2:34 ` [PATCH v1 " qi1.zhang
2019-10-08 1:39 ` [PATCH 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-10-08 2:34 ` [PATCH v2 " qi1.zhang
2019-10-08 2:34 ` [PATCH v1 0/2] TM field check failed qi1.zhang
2019-10-12 5:05 ` Zhang, Qi1
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