From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions
Date: Fri, 11 Oct 2019 09:47:35 -0400 [thread overview]
Message-ID: <20191011134744.2477-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Require pre-cleaned addresses.
---
target/arm/helper-a64.h | 3 ++
target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 42 +++++++++++++----
3 files changed, 132 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 88a0241915..405aa60016 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -115,3 +115,6 @@ DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
+DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64)
+DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64)
+DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index f1dd1cc0dd..f1315bae37 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -414,3 +414,99 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
{
do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel);
}
+
+uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
+{
+ const int size = 4 << GMID_EL1_BS;
+ int el;
+ uint64_t sctlr;
+ void *mem;
+
+ ptr = QEMU_ALIGN_DOWN(ptr, size);
+
+ /* Trap if accessing an invalid page(s). */
+ mem = allocation_tag_mem(env, ptr, false, GETPC());
+
+ /*
+ * The tag is squashed to zero if the page does not support tags,
+ * or if the OS is denying access to the tags.
+ */
+ el = arm_current_el(env);
+ sctlr = arm_sctlr(env, el);
+ if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) {
+ return 0;
+ }
+
+#if GMID_EL1_BS != 6
+# error "Fill in the blanks for other sizes"
+#endif
+ /*
+ * We are loading 64-bits worth of tags. The ordering of elements
+ * within the word corresponds to a 64-bit little-endian operation.
+ */
+ return ldq_le_p(mem);
+}
+
+static uint64_t do_stgm(CPUARMState *env, uint64_t ptr,
+ uint64_t val, uintptr_t ra)
+{
+ const int size = 4 << GMID_EL1_BS;
+ int el;
+ uint64_t sctlr;
+ void *mem;
+
+ ptr = QEMU_ALIGN_DOWN(ptr, size);
+
+ /* Trap if accessing an invalid page(s). */
+ mem = allocation_tag_mem(env, ptr, true, ra);
+
+ /*
+ * No action if the page does not support tags,
+ * or if the OS is denying access to the tags.
+ */
+ el = arm_current_el(env);
+ sctlr = arm_sctlr(env, el);
+ if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) {
+ return ptr;
+ }
+
+#if GMID_EL1_BS != 6
+# error "Fill in the blanks for other sizes"
+#endif
+ /*
+ * We are storing 64-bits worth of tags. The ordering of elements
+ * within the word corresponds to a 64-bit little-endian operation.
+ */
+ stq_le_p(mem, val);
+
+ return ptr;
+}
+
+void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
+{
+ do_stgm(env, ptr, val, GETPC());
+}
+
+void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
+{
+ int i, mmu_idx, size = 4 << GMID_EL1_BS;
+ uintptr_t ra = GETPC();
+ void *mem;
+
+ ptr = do_stgm(env, ptr, val, ra);
+
+ /*
+ * We will have just probed this virtual address in do_stgm.
+ * If the tlb_vaddr_to_host fails, then the memory is not ram,
+ * or is monitored in some other way. Fall back to stores.
+ */
+ mmu_idx = cpu_mmu_index(env, false);
+ mem = tlb_vaddr_to_host(env, ptr, MMU_DATA_STORE, mmu_idx);
+ if (mem) {
+ memset(mem, 0, size);
+ } else {
+ for (i = 0; i < size; i += 8) {
+ cpu_stq_data_ra(env, ptr + i, 0, ra);
+ }
+ }
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4ecb0a2fb7..4e049bb4aa 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3592,7 +3592,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE;
int op2 = extract32(insn, 10, 3);
int op1 = extract32(insn, 22, 2);
- bool is_load = false, is_pair = false, is_zero = false;
+ bool is_load = false, is_pair = false, is_zero = false, is_mult = false;
int index = 0;
TCGv_i64 dirty_addr, clean_addr, tcg_rt;
@@ -3602,13 +3602,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
}
switch (op1) {
- case 0: /* STG */
+ case 0:
if (op2 != 0) {
/* STG */
index = op2 - 2;
- break;
+ } else {
+ /* STZGM */
+ if (s->current_el == 0 || offset != 0) {
+ goto do_unallocated;
+ }
+ is_mult = is_zero = true;
}
- goto do_unallocated;
+ break;
case 1:
if (op2 != 0) {
/* STZG */
@@ -3624,17 +3629,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
/* ST2G */
is_pair = true;
index = op2 - 2;
- break;
+ } else {
+ /* STGM */
+ if (s->current_el == 0 || offset != 0) {
+ goto do_unallocated;
+ }
+ is_mult = true;
}
- goto do_unallocated;
+ break;
case 3:
if (op2 != 0) {
/* STZ2G */
is_pair = is_zero = true;
index = op2 - 2;
- break;
+ } else {
+ /* LDGM */
+ if (s->current_el == 0 || offset != 0) {
+ goto do_unallocated;
+ }
+ is_mult = is_load = true;
}
- goto do_unallocated;
+ break;
default:
do_unallocated:
@@ -3651,7 +3666,16 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn)
clean_addr = clean_data_tbi(s, dirty_addr, false);
tcg_rt = cpu_reg(s, rt);
- if (is_load) {
+ if (is_mult) {
+ if (is_load) {
+ gen_helper_ldgm(tcg_rt, cpu_env, clean_addr);
+ } else if (is_zero) {
+ gen_helper_stzgm(cpu_env, clean_addr, tcg_rt);
+ } else {
+ gen_helper_stgm(cpu_env, clean_addr, tcg_rt);
+ }
+ return;
+ } else if (is_load) {
gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt);
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
if (is_pair) {
--
2.17.1
next prev parent reply other threads:[~2019-10-11 14:00 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 13:47 [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2019-10-11 13:47 ` [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-10-11 13:47 ` [PATCH v5 02/22] target/arm: Add regime_has_2_ranges Richard Henderson
2019-12-03 11:01 ` Peter Maydell
2019-12-03 15:09 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 03/22] target/arm: Add MTE system registers Richard Henderson
2019-12-03 11:48 ` Peter Maydell
2019-12-06 14:47 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} Richard Henderson
2019-12-03 13:42 ` Peter Maydell
2019-12-03 16:06 ` Richard Henderson
2019-12-03 16:26 ` Peter Maydell
2019-12-03 16:14 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-12-03 14:07 ` Peter Maydell
2020-02-17 21:32 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 06/22] target/arm: Implement the IRG instruction Richard Henderson
2019-12-03 14:26 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-10-11 13:47 ` [PATCH v5 08/22] target/arm: Implement the GMI instruction Richard Henderson
2019-10-11 13:47 ` [PATCH v5 09/22] target/arm: Implement the SUBP instruction Richard Henderson
2019-10-11 13:47 ` [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-12-05 16:12 ` Peter Maydell
2020-02-17 22:56 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-12-05 17:07 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 12/22] target/arm: Implement the STGP instruction Richard Henderson
2019-12-05 17:15 ` Peter Maydell
2019-10-11 13:47 ` Richard Henderson [this message]
2019-12-05 17:42 ` [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions Peter Maydell
2019-10-11 13:47 ` [PATCH v5 14/22] target/arm: Implement the access tag cache flushes Richard Henderson
2019-12-05 17:49 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 15/22] target/arm: Clean address for DC ZVA Richard Henderson
2019-12-05 17:54 ` Peter Maydell
2019-12-05 18:58 ` Peter Maydell
2020-02-18 0:50 ` Richard Henderson
2020-02-18 11:10 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 16/22] target/arm: Implement data cache set allocation tags Richard Henderson
2019-12-05 18:17 ` Peter Maydell
2020-02-18 1:19 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-10-11 13:47 ` [PATCH v5 18/22] target/arm: Enable MTE Richard Henderson
2019-12-05 18:23 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-12-05 18:32 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-12-05 18:40 ` Peter Maydell
2019-12-05 19:24 ` Richard Henderson
2019-12-06 9:51 ` Peter Maydell
2019-10-11 13:47 ` [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory Richard Henderson
2019-12-06 11:46 ` Peter Maydell
2019-12-06 14:03 ` Richard Henderson
2019-10-11 13:47 ` [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-12-06 13:02 ` Peter Maydell
2019-12-06 14:14 ` Richard Henderson
2019-10-11 19:32 ` [PATCH v5 00/22] target/arm: Implement ARMv8.5-MemTag, " no-reply
2019-10-15 20:39 ` Evgenii Stepanov
2019-10-15 22:04 ` Richard Henderson
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