From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Jae Hyun Yoo" <jae.hyun.yoo@linux.intel.com>,
"Andrew Jeffery" <andrew@aj.id.au>,
"Eddie James" <eajames@linux.vnet.ibm.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Joel Stanley" <joel@jms.id.au>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH 0/5] aspeed/i2c: Add support for pool and DMA transfer modes
Date: Wed, 16 Oct 2019 10:50:30 +0200 [thread overview]
Message-ID: <20191016085035.12136-1-clg@kaod.org> (raw)
Hello,
The Aspeed I2C controller can operate in three different transfer
modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer multiple
bytes in the same command sequence.
- DMA mode, supporting transfers up to 4K to and from DRAM.
This series adds support for the pool and DMA transfer modes taking
into account the specificities of each SoC.
Last patch adds some traces which proved to be useful to debug the
I2C state machine.
Thanks,
C.
Cédric Le Goater (5):
aspeed/i2c: Add support for pool buffer transfers
aspeed/i2c: Check SRAM enablement on A2500
aspeed: Add a DRAM memory region at the SoC level
aspeed/i2c: Add support for DMA transfers
aspeed/i2c: Add trace events
include/hw/arm/aspeed_soc.h | 1 +
include/hw/i2c/aspeed_i2c.h | 16 ++
hw/arm/aspeed_ast2600.c | 12 +-
hw/arm/aspeed_soc.c | 14 +-
hw/i2c/aspeed_i2c.c | 439 +++++++++++++++++++++++++++++++++---
hw/i2c/trace-events | 9 +
6 files changed, 459 insertions(+), 32 deletions(-)
--
2.21.0
next reply other threads:[~2019-10-16 8:52 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 8:50 Cédric Le Goater [this message]
2019-10-16 8:50 ` [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:02 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 2/5] aspeed/i2c: Check SRAM enablement on A2500 Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 3/5] aspeed: Add a DRAM memory region at the SoC level Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-22 17:36 ` Philippe Mathieu-Daudé
2019-10-16 8:50 ` [PATCH 4/5] aspeed/i2c: Add support for DMA transfers Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 5/5] aspeed/i2c: Add trace events Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:05 ` Jae Hyun Yoo
2019-10-17 10:22 ` Philippe Mathieu-Daudé
2019-10-17 11:52 ` Cédric Le Goater
2019-10-22 18:10 ` Philippe Mathieu-Daudé
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