From: Joel Stanley <joel@jms.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>,
Andrew Jeffery <andrew@aj.id.au>,
Eddie James <eajames@linux.vnet.ibm.com>,
QEMU Developers <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>
Subject: Re: [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers
Date: Wed, 16 Oct 2019 11:24:16 +0000 [thread overview]
Message-ID: <CACPK8XdULytZOsapN=wmAqz5GDD-v89-eTi0byo1O9DtVm3y2Q@mail.gmail.com> (raw)
In-Reply-To: <20191016085035.12136-2-clg@kaod.org>
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater <clg@kaod.org> wrote:
>
> The Aspeed I2C controller can operate in different transfer modes :
>
> - Byte Buffer mode, using a dedicated register to transfer a
> byte. This is what the model supports today.
>
> - Pool Buffer mode, using an internal SRAM to transfer multiple
> bytes in the same command sequence.
>
> Each SoC has different SRAM characteristics. On the AST2400, 2048
> bytes of SRAM are available at offset 0x800 of the controller AHB
> window. The pool buffer can be configured from 1 to 256 bytes per bus.
>
> On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
> 16 bytes per bus.
>
> On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
> 32 bytes per bus. It can be splitted in two for TX and RX but the
> current model does not add support for it as it it unused by known
> drivers.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
next prev parent reply other threads:[~2019-10-16 11:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-16 8:50 [PATCH 0/5] aspeed/i2c: Add support for pool and DMA transfer modes Cédric Le Goater
2019-10-16 8:50 ` [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley [this message]
2019-10-16 19:02 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 2/5] aspeed/i2c: Check SRAM enablement on A2500 Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 3/5] aspeed: Add a DRAM memory region at the SoC level Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-22 17:36 ` Philippe Mathieu-Daudé
2019-10-16 8:50 ` [PATCH 4/5] aspeed/i2c: Add support for DMA transfers Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:03 ` Jae Hyun Yoo
2019-10-16 8:50 ` [PATCH 5/5] aspeed/i2c: Add trace events Cédric Le Goater
2019-10-16 11:24 ` Joel Stanley
2019-10-16 19:05 ` Jae Hyun Yoo
2019-10-17 10:22 ` Philippe Mathieu-Daudé
2019-10-17 11:52 ` Cédric Le Goater
2019-10-22 18:10 ` Philippe Mathieu-Daudé
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