QEMU-Devel Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v2 0/3] target/microblaze: Plug tcg temp leaks
@ 2019-11-08 12:42 Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Edgar E. Iglesias @ 2019-11-08 12:42 UTC (permalink / raw)
  To: qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
	frederic.konrad, philmd, luc.michel

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

On some workloads we've seen TCG run out of temps due to leakage
in the MicroBlaze translator. This series fixes the leaks.

Cheers,
Edgar

ChangeLog:

v1 -> v2:
* Use tcg_gen_xori_tl when endian reversing load/store addresses


Edgar E. Iglesias (3):
  target/microblaze: Plug temp leaks for loads/stores
  target/microblaze: Plug temp leaks with delay slot setup
  target/microblaze: Plug temp leak around eval_cond_jmp()

 target/microblaze/translate.c | 77 +++++++++++++++++------------------
 1 file changed, 38 insertions(+), 39 deletions(-)

-- 
2.20.1



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores
  2019-11-08 12:42 [PATCH v2 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
@ 2019-11-08 12:42 ` Edgar E. Iglesias
  2019-11-08 13:15   ` Richard Henderson
                     ` (2 more replies)
  2019-11-08 12:42 ` [PATCH v2 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
  2 siblings, 3 replies; 7+ messages in thread
From: Edgar E. Iglesias @ 2019-11-08 12:42 UTC (permalink / raw)
  To: qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
	frederic.konrad, philmd, luc.michel

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Simplify endian reversion of address also plugging TCG temp
leaks for loads/stores.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 46 +++++++++++++++--------------------
 1 file changed, 20 insertions(+), 26 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 761f535357..c8442b18e1 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -962,17 +962,7 @@ static void dec_load(DisasContext *dc)
         switch (size) {
             case 1:
             {
-                /* 00 -> 11
-                   01 -> 10
-                   10 -> 10
-                   11 -> 00 */
-                TCGv low = tcg_temp_new();
-
-                tcg_gen_andi_tl(low, addr, 3);
-                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
-                tcg_gen_andi_tl(addr, addr, ~3);
-                tcg_gen_or_tl(addr, addr, low);
-                tcg_temp_free(low);
+                tcg_gen_xori_tl(addr, addr, 3);
                 break;
             }
 
@@ -1006,9 +996,16 @@ static void dec_load(DisasContext *dc)
     tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
 
     if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+        TCGv_i32 t0 = tcg_const_i32(0);
+        TCGv_i32 treg = tcg_const_i32(dc->rd);
+        TCGv_i32 tsize = tcg_const_i32(size - 1);
+
         tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
-        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
-                            tcg_const_i32(0), tcg_const_i32(size - 1));
+        gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
+
+        tcg_temp_free_i32(t0);
+        tcg_temp_free_i32(treg);
+        tcg_temp_free_i32(tsize);
     }
 
     if (ex) {
@@ -1095,17 +1092,7 @@ static void dec_store(DisasContext *dc)
         switch (size) {
             case 1:
             {
-                /* 00 -> 11
-                   01 -> 10
-                   10 -> 10
-                   11 -> 00 */
-                TCGv low = tcg_temp_new();
-
-                tcg_gen_andi_tl(low, addr, 3);
-                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
-                tcg_gen_andi_tl(addr, addr, ~3);
-                tcg_gen_or_tl(addr, addr, low);
-                tcg_temp_free(low);
+                tcg_gen_xori_tl(addr, addr, 3);
                 break;
             }
 
@@ -1124,6 +1111,10 @@ static void dec_store(DisasContext *dc)
 
     /* Verify alignment if needed.  */
     if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+        TCGv_i32 t1 = tcg_const_i32(1);
+        TCGv_i32 treg = tcg_const_i32(dc->rd);
+        TCGv_i32 tsize = tcg_const_i32(size - 1);
+
         tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
         /* FIXME: if the alignment is wrong, we should restore the value
          *        in memory. One possible way to achieve this is to probe
@@ -1131,8 +1122,11 @@ static void dec_store(DisasContext *dc)
          *        the alignment checks in between the probe and the mem
          *        access.
          */
-        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
-                            tcg_const_i32(1), tcg_const_i32(size - 1));
+        gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
+
+        tcg_temp_free_i32(t1);
+        tcg_temp_free_i32(treg);
+        tcg_temp_free_i32(tsize);
     }
 
     if (ex) {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 2/3] target/microblaze: Plug temp leaks with delay slot setup
  2019-11-08 12:42 [PATCH v2 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
@ 2019-11-08 12:42 ` Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
  2 siblings, 0 replies; 7+ messages in thread
From: Edgar E. Iglesias @ 2019-11-08 12:42 UTC (permalink / raw)
  To: qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
	frederic.konrad, philmd, luc.michel

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Plug temp leaks with delay slot setup.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c8442b18e1..7b4b66a622 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1177,6 +1177,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
     tcg_temp_free_i64(tmp_zero);
 }
 
+static void dec_setup_dslot(DisasContext *dc)
+{
+        TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
+
+        dc->delayed_branch = 2;
+        dc->tb_flags |= D_FLAG;
+
+        tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
+        tcg_temp_free_i32(tmp);
+}
+
 static void dec_bcc(DisasContext *dc)
 {
     unsigned int cc;
@@ -1188,10 +1199,7 @@ static void dec_bcc(DisasContext *dc)
 
     dc->delayed_branch = 1;
     if (dslot) {
-        dc->delayed_branch = 2;
-        dc->tb_flags |= D_FLAG;
-        tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
-                      cpu_env, offsetof(CPUMBState, bimm));
+        dec_setup_dslot(dc);
     }
 
     if (dec_alu_op_b_is_small_imm(dc)) {
@@ -1250,10 +1258,7 @@ static void dec_br(DisasContext *dc)
 
     dc->delayed_branch = 1;
     if (dslot) {
-        dc->delayed_branch = 2;
-        dc->tb_flags |= D_FLAG;
-        tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
-                      cpu_env, offsetof(CPUMBState, bimm));
+        dec_setup_dslot(dc);
     }
     if (link && dc->rd)
         tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
@@ -1355,10 +1360,7 @@ static void dec_rts(DisasContext *dc)
         return;
     }
 
-    dc->delayed_branch = 2;
-    dc->tb_flags |= D_FLAG;
-    tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
-                  cpu_env, offsetof(CPUMBState, bimm));
+    dec_setup_dslot(dc);
 
     if (i_bit) {
         LOG_DIS("rtid ir=%x\n", dc->ir);
-- 
2.20.1



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
  2019-11-08 12:42 [PATCH v2 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
  2019-11-08 12:42 ` [PATCH v2 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
@ 2019-11-08 12:42 ` Edgar E. Iglesias
  2 siblings, 0 replies; 7+ messages in thread
From: Edgar E. Iglesias @ 2019-11-08 12:42 UTC (permalink / raw)
  To: qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
	frederic.konrad, philmd, luc.michel

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Plug temp leak around eval_cond_jmp().

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7b4b66a622..bdc7d5326a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1681,7 +1681,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
                 dc->tb_flags &= ~D_FLAG;
                 /* If it is a direct jump, try direct chaining.  */
                 if (dc->jmp == JMP_INDIRECT) {
-                    eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc));
+                    TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
+                    eval_cond_jmp(dc, env_btarget, tmp_pc);
+                    tcg_temp_free_i64(tmp_pc);
+
                     dc->is_jmp = DISAS_JUMP;
                 } else if (dc->jmp == JMP_DIRECT) {
                     t_sync_flags(dc);
-- 
2.20.1



^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
@ 2019-11-08 13:15   ` Richard Henderson
  2019-11-08 13:16   ` Luc Michel
  2019-11-08 16:30   ` Alistair Francis
  2 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2019-11-08 13:15 UTC (permalink / raw)
  To: Edgar E. Iglesias, qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, frederic.konrad,
	philmd, luc.michel

On 11/8/19 1:42 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Simplify endian reversion of address also plugging TCG temp
> leaks for loads/stores.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/microblaze/translate.c | 46 +++++++++++++++--------------------
>  1 file changed, 20 insertions(+), 26 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
  2019-11-08 13:15   ` Richard Henderson
@ 2019-11-08 13:16   ` Luc Michel
  2019-11-08 16:30   ` Alistair Francis
  2 siblings, 0 replies; 7+ messages in thread
From: Luc Michel @ 2019-11-08 13:16 UTC (permalink / raw)
  To: Edgar E. Iglesias, qemu-devel
  Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
	sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
	frederic.konrad, philmd

On 11/8/19 1:42 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Simplify endian reversion of address also plugging TCG temp
> leaks for loads/stores.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/microblaze/translate.c | 46 +++++++++++++++--------------------
>  1 file changed, 20 insertions(+), 26 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 761f535357..c8442b18e1 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -962,17 +962,7 @@ static void dec_load(DisasContext *dc)
>          switch (size) {
>              case 1:
>              {
> -                /* 00 -> 11
> -                   01 -> 10
> -                   10 -> 10
> -                   11 -> 00 */
> -                TCGv low = tcg_temp_new();
> -
> -                tcg_gen_andi_tl(low, addr, 3);
> -                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> -                tcg_gen_andi_tl(addr, addr, ~3);
> -                tcg_gen_or_tl(addr, addr, low);
> -                tcg_temp_free(low);
> +                tcg_gen_xori_tl(addr, addr, 3);
>                  break;
>              }
>  
> @@ -1006,9 +996,16 @@ static void dec_load(DisasContext *dc)
>      tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>  
>      if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +        TCGv_i32 t0 = tcg_const_i32(0);
> +        TCGv_i32 treg = tcg_const_i32(dc->rd);
> +        TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
>          tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> -        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> -                            tcg_const_i32(0), tcg_const_i32(size - 1));
> +        gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
> +
> +        tcg_temp_free_i32(t0);
> +        tcg_temp_free_i32(treg);
> +        tcg_temp_free_i32(tsize);
>      }
>  
>      if (ex) {
> @@ -1095,17 +1092,7 @@ static void dec_store(DisasContext *dc)
>          switch (size) {
>              case 1:
>              {
> -                /* 00 -> 11
> -                   01 -> 10
> -                   10 -> 10
> -                   11 -> 00 */
> -                TCGv low = tcg_temp_new();
> -
> -                tcg_gen_andi_tl(low, addr, 3);
> -                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> -                tcg_gen_andi_tl(addr, addr, ~3);
> -                tcg_gen_or_tl(addr, addr, low);
> -                tcg_temp_free(low);
> +                tcg_gen_xori_tl(addr, addr, 3);
>                  break;
>              }
>  
> @@ -1124,6 +1111,10 @@ static void dec_store(DisasContext *dc)
>  
>      /* Verify alignment if needed.  */
>      if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +        TCGv_i32 t1 = tcg_const_i32(1);
> +        TCGv_i32 treg = tcg_const_i32(dc->rd);
> +        TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
>          tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
>          /* FIXME: if the alignment is wrong, we should restore the value
>           *        in memory. One possible way to achieve this is to probe
> @@ -1131,8 +1122,11 @@ static void dec_store(DisasContext *dc)
>           *        the alignment checks in between the probe and the mem
>           *        access.
>           */
> -        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> -                            tcg_const_i32(1), tcg_const_i32(size - 1));
> +        gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
> +
> +        tcg_temp_free_i32(t1);
> +        tcg_temp_free_i32(treg);
> +        tcg_temp_free_i32(tsize);
>      }
>  
>      if (ex) {
> 

Reviewed-by: Luc Michel <luc.michel@greensocs.com>


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores
  2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
  2019-11-08 13:15   ` Richard Henderson
  2019-11-08 13:16   ` Luc Michel
@ 2019-11-08 16:30   ` Alistair Francis
  2 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2019-11-08 16:30 UTC (permalink / raw)
  To: Edgar E. Iglesias
  Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
	Francisco Iglesias, Alistair Francis, Richard Henderson,
	qemu-devel@nongnu.org Developers, KONRAD Frederic,
	Stefano Stabellini, Philippe Mathieu-Daudé,
	Luc Michel

On Fri, Nov 8, 2019 at 4:43 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Simplify endian reversion of address also plugging TCG temp
> leaks for loads/stores.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/translate.c | 46 +++++++++++++++--------------------
>  1 file changed, 20 insertions(+), 26 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 761f535357..c8442b18e1 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -962,17 +962,7 @@ static void dec_load(DisasContext *dc)
>          switch (size) {
>              case 1:
>              {
> -                /* 00 -> 11
> -                   01 -> 10
> -                   10 -> 10
> -                   11 -> 00 */
> -                TCGv low = tcg_temp_new();
> -
> -                tcg_gen_andi_tl(low, addr, 3);
> -                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> -                tcg_gen_andi_tl(addr, addr, ~3);
> -                tcg_gen_or_tl(addr, addr, low);
> -                tcg_temp_free(low);
> +                tcg_gen_xori_tl(addr, addr, 3);
>                  break;
>              }
>
> @@ -1006,9 +996,16 @@ static void dec_load(DisasContext *dc)
>      tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
>      if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +        TCGv_i32 t0 = tcg_const_i32(0);
> +        TCGv_i32 treg = tcg_const_i32(dc->rd);
> +        TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
>          tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> -        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> -                            tcg_const_i32(0), tcg_const_i32(size - 1));
> +        gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
> +
> +        tcg_temp_free_i32(t0);
> +        tcg_temp_free_i32(treg);
> +        tcg_temp_free_i32(tsize);
>      }
>
>      if (ex) {
> @@ -1095,17 +1092,7 @@ static void dec_store(DisasContext *dc)
>          switch (size) {
>              case 1:
>              {
> -                /* 00 -> 11
> -                   01 -> 10
> -                   10 -> 10
> -                   11 -> 00 */
> -                TCGv low = tcg_temp_new();
> -
> -                tcg_gen_andi_tl(low, addr, 3);
> -                tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> -                tcg_gen_andi_tl(addr, addr, ~3);
> -                tcg_gen_or_tl(addr, addr, low);
> -                tcg_temp_free(low);
> +                tcg_gen_xori_tl(addr, addr, 3);
>                  break;
>              }
>
> @@ -1124,6 +1111,10 @@ static void dec_store(DisasContext *dc)
>
>      /* Verify alignment if needed.  */
>      if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +        TCGv_i32 t1 = tcg_const_i32(1);
> +        TCGv_i32 treg = tcg_const_i32(dc->rd);
> +        TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
>          tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
>          /* FIXME: if the alignment is wrong, we should restore the value
>           *        in memory. One possible way to achieve this is to probe
> @@ -1131,8 +1122,11 @@ static void dec_store(DisasContext *dc)
>           *        the alignment checks in between the probe and the mem
>           *        access.
>           */
> -        gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> -                            tcg_const_i32(1), tcg_const_i32(size - 1));
> +        gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
> +
> +        tcg_temp_free_i32(t1);
> +        tcg_temp_free_i32(treg);
> +        tcg_temp_free_i32(tsize);
>      }
>
>      if (ex) {
> --
> 2.20.1
>
>


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, back to index

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-08 12:42 [PATCH v2 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
2019-11-08 12:42 ` [PATCH v2 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
2019-11-08 13:15   ` Richard Henderson
2019-11-08 13:16   ` Luc Michel
2019-11-08 16:30   ` Alistair Francis
2019-11-08 12:42 ` [PATCH v2 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
2019-11-08 12:42 ` [PATCH v2 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git