* [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking
@ 2019-11-25 0:21 yadong.qi
0 siblings, 0 replies; 3+ messages in thread
From: yadong.qi @ 2019-11-25 0:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, peterx, pbonzini, yadong.qi, rth
From: "Qi, Yadong" <yadong.qi@intel.com>
The following patches are to refine/fix issues of reserved fields checking logic
of Second-Level Paging Entries of VT-d:
- split the resevred fields arrays into two ones,
- large page only effect for L2(2M) and L3(1G), so remove
checking of L1 and L4 for large page,
- when dt is supported, TM filed should not be Reserved(0).
Changes in v3:
- large page only effect for L2(2M) and L3(1G), so remove
checking of L1 and L4 for large page
Qi, Yadong (2):
intel_iommu: refine SL-PEs reserved fields checking
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 40 +++++++++++++++++++---------------
hw/i386/intel_iommu_internal.h | 18 +++++++++------
2 files changed, 34 insertions(+), 24 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking
2019-11-25 0:33 yadong.qi
@ 2019-11-25 3:08 ` Peter Xu
0 siblings, 0 replies; 3+ messages in thread
From: Peter Xu @ 2019-11-25 3:08 UTC (permalink / raw)
To: yadong.qi; +Cc: qi1.zhang, ehabkost, mst, qemu-devel, pbonzini, rth
On Mon, Nov 25, 2019 at 08:33:19AM +0800, yadong.qi@intel.com wrote:
> From: "Qi, Yadong" <yadong.qi@intel.com>
>
> The following patches are to refine/fix issues of reserved fields checking logic
> of Second-Level Paging Entries of VT-d:
> - split the resevred fields arrays into two ones,
> - large page only effect for L2(2M) and L3(1G), so remove
> checking of L1 and L4 for large page,
> - when dt is supported, TM filed should not be Reserved(0).
>
> Changes in v3:
> - large page only effect for L2(2M) and L3(1G), so remove
> checking of L1 and L4 for large page
Reviewed-by: Peter Xu <peterx@redhat.com>
Thanks,
--
Peter Xu
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking
@ 2019-11-25 0:33 yadong.qi
2019-11-25 3:08 ` Peter Xu
0 siblings, 1 reply; 3+ messages in thread
From: yadong.qi @ 2019-11-25 0:33 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, peterx, pbonzini, yadong.qi, rth
From: "Qi, Yadong" <yadong.qi@intel.com>
The following patches are to refine/fix issues of reserved fields checking logic
of Second-Level Paging Entries of VT-d:
- split the resevred fields arrays into two ones,
- large page only effect for L2(2M) and L3(1G), so remove
checking of L1 and L4 for large page,
- when dt is supported, TM filed should not be Reserved(0).
Changes in v3:
- large page only effect for L2(2M) and L3(1G), so remove
checking of L1 and L4 for large page
Qi, Yadong (2):
intel_iommu: refine SL-PEs reserved fields checking
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 40 +++++++++++++++++++---------------
hw/i386/intel_iommu_internal.h | 18 +++++++++------
2 files changed, 34 insertions(+), 24 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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