[PATCH RESEND 0/4] Add extra information to versioned CPU models

qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed

* [PATCH RESEND 0/4] Add extra information to versioned CPU models
@ 2019-12-02  6:32 Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-02  6:32 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel

This series of patches will remove MPX from Denverton, remove Remove
monitor from some CPU models. Add additional information for -cpu help
to indicate the changes in this version of CPU model.

The output is as follows:
x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
x86 Broadwell-v2          Intel Core Processor (Broadwell) [no TSX]                 
x86 Broadwell-v3          Intel Core Processor (Broadwell) [IBRS]                   
x86 Broadwell-v4          Intel Core Processor (Broadwell) [no TSX, IBRS]           
x86 Cascadelake-Server-v2  Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES]    
x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake) [no TSX]               
x86 Denverton-v2          Intel Atom Processor (Denverton) [no MPX, no MONITOR]     
x86 Dhyana-v2             Hygon Dhyana Processor [no MONITOR]                       
x86 EPYC-v2               AMD EPYC Processor [IBPB]                                 
x86 EPYC-v3               AMD EPYC Processor [IBPB, no MONITOR]                     
x86 Haswell-v2            Intel Core Processor (Haswell) [no TSX]                   
x86 Haswell-v3            Intel Core Processor (Haswell) [IBRS]                     
x86 Haswell-v4            Intel Core Processor (Haswell) [no TSX, IBRS]             
x86 Icelake-Client-v2     Intel Core Processor (Icelake) [no TSX]                   
x86 Icelake-Server-v2     Intel Xeon Processor (Icelake) [no TSX]                   
x86 IvyBridge-v2          Intel Xeon E3-12xx v2 (Ivy Bridge) [IBRS]                 
x86 Nehalem-v2            Intel Core i7 9xx (Nehalem Class Core i7) [IBRS]          
x86 Opteron_G3-v2         AMD Opteron 23xx (Gen 3 Class Opteron) [no MONITOR]       
x86 SandyBridge-v2        Intel Xeon E312xx (Sandy Bridge) [IBRS]                   
x86 Skylake-Client-v2     Intel Core Processor (Skylake) [IBRS]                     
x86 Skylake-Client-v3     Intel Core Processor (Skylake) [no TSX, IBRS]             
x86 Skylake-Server-v2     Intel Xeon Processor (Skylake) [IBRS]                     
x86 Skylake-Server-v3     Intel Xeon Processor (Skylake) [no TSX, IBRS]             
x86 Snowridge-v2          Intel Atom Processor (SnowRidge) [no MPX]                 
x86 Snowridge-v3          Intel Atom Processor (SnowRidge) [no MPX, no MONITOR]     
x86 Westmere-v2           Westmere E56xx/L56xx/X56xx (Nehalem-C) [IBRS]

Tao Xu (4):
  target/i386: Add Denverton-v2 (no MPX) CPU model
  target/i386: Remove monitor from some CPU models
  target/i386: Add new property note to versioned CPU models
  target/i386: Add notes for versioned CPU models

 target/i386/cpu.c | 112 +++++++++++++++++++++++++++++++++++-----------
 1 file changed, 85 insertions(+), 27 deletions(-)

-- 
2.20.1



^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH RESEND 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model
  2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
@ 2019-12-02  6:32 ` Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 2/4] target/i386: Remove monitor from some CPU models Tao Xu
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-02  6:32 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel

Because MPX is being removed from the linux kernel, remove MPX feature
from Denverton.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 69f518a21a..06a3077f95 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3482,6 +3482,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Intel Atom Processor (Denverton)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { "mpx", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
     {
         .name = "Snowridge",
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH RESEND 2/4] target/i386: Remove monitor from some CPU models
  2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
@ 2019-12-02  6:32 ` Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 3/4] target/i386: Add new property note to versioned " Tao Xu
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-02  6:32 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel

Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to remove MONITOR/MWAIT feature.

After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
(commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
feature in these CPU model is unused.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 06a3077f95..b09ac38409 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3621,6 +3621,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ },
                 },
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    /* mpx was already removed by -v2 above */
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
             { /* end of list */ },
         },
     },
@@ -3732,6 +3740,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
         .xlevel = 0x80000008,
         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
     {
         .name = "Opteron_G4",
@@ -3856,6 +3875,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    /* ibpb was already enabled by -v2 above */
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
             { /* end of list */ }
         }
     },
@@ -3908,6 +3935,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "Hygon Dhyana Processor",
         .cache_info = &epyc_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
 };
 
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH RESEND 3/4] target/i386: Add new property note to versioned CPU models
  2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 2/4] target/i386: Remove monitor from some CPU models Tao Xu
@ 2019-12-02  6:32 ` Tao Xu
  2019-12-02  6:32 ` [PATCH RESEND 4/4] target/i386: Add notes for " Tao Xu
  2019-12-05  8:55 ` [PATCH RESEND 0/4] Add extra information to " Xiaoyao Li
  4 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-02  6:32 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel

Add additional information for -cpu help to indicate the changes in this
version of CPU model.

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b09ac38409..7b3bd6d4db 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1693,6 +1693,7 @@ typedef struct PropValue {
 typedef struct X86CPUVersionDefinition {
     X86CPUVersion version;
     const char *alias;
+    const char *note;
     PropValue *props;
 } X86CPUVersionDefinition;
 
@@ -1723,6 +1724,7 @@ struct X86CPUModel {
     X86CPUDefinition *cpudef;
     /* CPU model version */
     X86CPUVersion version;
+    const char *note;
     /*
      * If true, this is an alias CPU model.
      * This matters only for "-cpu help" and query-cpu-definitions
@@ -4788,6 +4790,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
     char *name = x86_cpu_class_get_model_name(cc);
     char *desc = g_strdup(cc->model_description);
     char *alias_of = x86_cpu_class_get_alias_of(cc);
+    char *model_id = x86_cpu_class_get_model_id(cc);
 
     if (!desc && alias_of) {
         if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
@@ -4796,14 +4799,18 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
             desc = g_strdup_printf("(alias of %s)", alias_of);
         }
     }
+    if (!desc && cc->model && cc->model->note) {
+        desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
+    }
     if (!desc) {
-        desc = x86_cpu_class_get_model_id(cc);
+        desc = g_strdup_printf("%s", model_id);
     }
 
-    qemu_printf("x86 %-20s  %-48s\n", name, desc);
+    qemu_printf("x86 %-20s  %-58s\n", name, desc);
     g_free(name);
     g_free(desc);
     g_free(alias_of);
+    g_free(model_id);
 }
 
 /* list available CPU models and flags */
@@ -5280,6 +5287,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
         X86CPUModel *m = g_new0(X86CPUModel, 1);
         m->cpudef = def;
         m->version = vdef->version;
+        m->note = vdef->note;
         name = x86_cpu_versioned_model_name(def, vdef->version);
         x86_register_cpu_model_type(name, m);
         g_free(name);
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH RESEND 4/4] target/i386: Add notes for versioned CPU models
  2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
                   ` (2 preceding siblings ...)
  2019-12-02  6:32 ` [PATCH RESEND 3/4] target/i386: Add new property note to versioned " Tao Xu
@ 2019-12-02  6:32 ` Tao Xu
  2019-12-05  8:44   ` Xiaoyao Li
  2019-12-05  8:55 ` [PATCH RESEND 0/4] Add extra information to " Xiaoyao Li
  4 siblings, 1 reply; 9+ messages in thread
From: Tao Xu @ 2019-12-02  6:32 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel

Add which features are added or removed in this version. Remove the
changed model-id in versioned CPU models.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 50 +++++++++++++++++++++++------------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7b3bd6d4db..c82fbfd02e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2281,10 +2281,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Nehalem-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2362,10 +2361,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Westmere-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Westmere E56xx/L56xx/X56xx (IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2448,10 +2446,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "SandyBridge-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2540,10 +2537,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "IvyBridge-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2637,17 +2633,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Haswell-noTSX",
+                .note = "no TSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     { "stepping", "1" },
-                    { "model-id", "Intel Core Processor (Haswell, no TSX)", },
                     { /* end of list */ }
                 },
             },
             {
                 .version = 3,
                 .alias = "Haswell-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* Restore TSX features removed by -v2 above */
                     { "hle", "on" },
@@ -2658,21 +2655,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
                      */
                     { "stepping", "4" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Haswell, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 4,
                 .alias = "Haswell-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     /* spec-ctrl was already enabled by -v3 above */
                     { "stepping", "1" },
-                    { "model-id",
-                      "Intel Core Processor (Haswell, no TSX, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2768,35 +2762,33 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Broadwell-noTSX",
+                .note = "no TSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
-                    { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
                     { /* end of list */ }
                 },
             },
             {
                 .version = 3,
                 .alias = "Broadwell-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* Restore TSX features removed by -v2 above */
                     { "hle", "on" },
                     { "rtm", "on" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Broadwell, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 4,
                 .alias = "Broadwell-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     /* spec-ctrl was already enabled by -v3 above */
-                    { "model-id",
-                      "Intel Core Processor (Broadwell, no TSX, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2896,17 +2888,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "IBRS",
                 .alias = "Skylake-Client-IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Skylake, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
                 .alias = "Skylake-Client-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
@@ -3017,19 +3009,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Skylake-Server-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* clflushopt was not added to Skylake-Server-IBRS */
                     /* TODO: add -v3 including clflushopt */
                     { "clflushopt", "off" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon Processor (Skylake, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
                 .alias = "Skylake-Server-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
@@ -3141,6 +3133,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
             { .version = 2,
+              .note = "ARCH_CAPABILITIES",
               .props = (PropValue[]) {
                   { "arch-capabilities", "on" },
                   { "rdctl-no", "on" },
@@ -3152,6 +3145,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             },
             { .version = 3,
               .alias = "Cascadelake-Server-noTSX",
+              .note = "no TSX",
               .props = (PropValue[]) {
                   { "hle", "off" },
                   { "rtm", "off" },
@@ -3264,6 +3258,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no TSX",
                 .alias = "Icelake-Client-noTSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
@@ -3381,6 +3376,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no TSX",
                 .alias = "Icelake-Server-noTSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
@@ -3488,6 +3484,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MPX, no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { "mpx", "off" },
@@ -3617,14 +3614,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MPX",
                 .props = (PropValue[]) {
                     { "mpx", "off" },
-                    { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
                     { /* end of list */ },
                 },
             },
             {
                 .version = 3,
+                .note = "no MPX, no MONITOR",
                 .props = (PropValue[]) {
                     /* mpx was already removed by -v2 above */
                     { "monitor", "off" },
@@ -3746,6 +3744,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { /* end of list */ },
@@ -3870,15 +3869,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "EPYC-IBPB",
+                .note = "IBPB",
                 .props = (PropValue[]) {
                     { "ibpb", "on" },
-                    { "model-id",
-                      "AMD EPYC Processor (with IBPB)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
+                .note = "IBPB, no MONITOR",
                 .props = (PropValue[]) {
                     /* ibpb was already enabled by -v2 above */
                     { "monitor", "off" },
@@ -3941,6 +3940,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { /* end of list */ },
-- 
2.20.1



^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH RESEND 4/4] target/i386: Add notes for versioned CPU models
  2019-12-02  6:32 ` [PATCH RESEND 4/4] target/i386: Add notes for " Tao Xu
@ 2019-12-05  8:44   ` Xiaoyao Li
  2019-12-09  2:47     ` Tao Xu
  0 siblings, 1 reply; 9+ messages in thread
From: Xiaoyao Li @ 2019-12-05  8:44 UTC (permalink / raw)
  To: qemu-devel

On 12/2/2019 2:32 PM, Tao Xu wrote:
> Add which features are added or removed in this version. Remove the
> changed model-id in versioned CPU models.
> 
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
>   target/i386/cpu.c | 50 +++++++++++++++++++++++------------------------
>   1 file changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 7b3bd6d4db..c82fbfd02e 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c

[...]

> @@ -3141,6 +3133,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>           .versions = (X86CPUVersionDefinition[]) {
>               { .version = 1 },
>               { .version = 2,
> +              .note = "ARCH_CAPABILITIES",

Here ARCH_CAPABILITIES doesn't tell what bits in 
MSR_IA32_ARCH_CAPABILITIES this version has, which makes it meaningless.

Maybe
	.note = "ARCH_CAPABLITIES(rdctl-no, ibrs-all, skip-l1dfl-vmentry, mds-no)",

is better?

>                 .props = (PropValue[]) {
>                     { "arch-capabilities", "on" },
>                     { "rdctl-no", "on" },
> @@ -3152,6 +3145,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>               },
>               { .version = 3,
>                 .alias = "Cascadelake-Server-noTSX",
> +              .note = "no TSX",
>                 .props = (PropValue[]) {
>                     { "hle", "off" },
>                     { "rtm", "off" },




^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH RESEND 4/4] target/i386: Add notes for versioned CPU models
  2019-12-05  8:44   ` Xiaoyao Li
@ 2019-12-09  2:47     ` Tao Xu
  0 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-09  2:47 UTC (permalink / raw)
  To: Xiaoyao Li, qemu-devel

On 12/5/2019 4:44 PM, Xiaoyao Li wrote:
> On 12/2/2019 2:32 PM, Tao Xu wrote:
>> Add which features are added or removed in this version. Remove the
>> changed model-id in versioned CPU models.
>>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>> ---
>>    target/i386/cpu.c | 50 +++++++++++++++++++++++------------------------
>>    1 file changed, 25 insertions(+), 25 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 7b3bd6d4db..c82fbfd02e 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
> 
> [...]
> 
>> @@ -3141,6 +3133,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>>            .versions = (X86CPUVersionDefinition[]) {
>>                { .version = 1 },
>>                { .version = 2,
>> +              .note = "ARCH_CAPABILITIES",
> 
> Here ARCH_CAPABILITIES doesn't tell what bits in
> MSR_IA32_ARCH_CAPABILITIES this version has, which makes it meaningless.
> 
> Maybe
>          .note = "ARCH_CAPABLITIES(rdctl-no, ibrs-all, skip-l1dfl-vmentry, mds-no)",
> 
> is better?
> 

But it is too long for -cpu help, break the info into 2 lines.




^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH RESEND 0/4] Add extra information to versioned CPU models
  2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
                   ` (3 preceding siblings ...)
  2019-12-02  6:32 ` [PATCH RESEND 4/4] target/i386: Add notes for " Tao Xu
@ 2019-12-05  8:55 ` Xiaoyao Li
  2019-12-09  2:43   ` Tao Xu
  4 siblings, 1 reply; 9+ messages in thread
From: Xiaoyao Li @ 2019-12-05  8:55 UTC (permalink / raw)
  To: qemu-devel

On 12/2/2019 2:32 PM, Tao Xu wrote:
> This series of patches will remove MPX from Denverton, remove Remove
> monitor from some CPU models. Add additional information for -cpu help
> to indicate the changes in this version of CPU model.
> 
> The output is as follows:
> x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
> x86 Broadwell-v2          Intel Core Processor (Broadwell) [no TSX]
> x86 Broadwell-v3          Intel Core Processor (Broadwell) [IBRS]
> x86 Broadwell-v4          Intel Core Processor (Broadwell) [no TSX, IBRS]

Above the changes of each Broadwell-v{2,3,4} are based on Broadwell-v1.

> x86 Cascadelake-Server-v2  Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES]
> x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake) [no TSX]

But in the code, Cascadelake-Server-v3 inherits all the features in 
Cascadelake-Server-v2 and removes TSX related hle & rtm.

So if we keep the same rule based on v1, it should be

  x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake) 
[ARCH_CAPABILITIES, no TSX]

> x86 Denverton-v2          Intel Atom Processor (Denverton) [no MPX, no MONITOR]
> x86 Dhyana-v2             Hygon Dhyana Processor [no MONITOR]
> x86 EPYC-v2               AMD EPYC Processor [IBPB]
> x86 EPYC-v3               AMD EPYC Processor [IBPB, no MONITOR]
> x86 Haswell-v2            Intel Core Processor (Haswell) [no TSX]
> x86 Haswell-v3            Intel Core Processor (Haswell) [IBRS]
> x86 Haswell-v4            Intel Core Processor (Haswell) [no TSX, IBRS]
> x86 Icelake-Client-v2     Intel Core Processor (Icelake) [no TSX]
> x86 Icelake-Server-v2     Intel Xeon Processor (Icelake) [no TSX]
> x86 IvyBridge-v2          Intel Xeon E3-12xx v2 (Ivy Bridge) [IBRS]
> x86 Nehalem-v2            Intel Core i7 9xx (Nehalem Class Core i7) [IBRS]
> x86 Opteron_G3-v2         AMD Opteron 23xx (Gen 3 Class Opteron) [no MONITOR]
> x86 SandyBridge-v2        Intel Xeon E312xx (Sandy Bridge) [IBRS]
> x86 Skylake-Client-v2     Intel Core Processor (Skylake) [IBRS]
> x86 Skylake-Client-v3     Intel Core Processor (Skylake) [no TSX, IBRS]
> x86 Skylake-Server-v2     Intel Xeon Processor (Skylake) [IBRS]
> x86 Skylake-Server-v3     Intel Xeon Processor (Skylake) [no TSX, IBRS]
> x86 Snowridge-v2          Intel Atom Processor (SnowRidge) [no MPX]
> x86 Snowridge-v3          Intel Atom Processor (SnowRidge) [no MPX, no MONITOR]
> x86 Westmere-v2           Westmere E56xx/L56xx/X56xx (Nehalem-C) [IBRS]
> 
> Tao Xu (4):
>    target/i386: Add Denverton-v2 (no MPX) CPU model
>    target/i386: Remove monitor from some CPU models
>    target/i386: Add new property note to versioned CPU models
>    target/i386: Add notes for versioned CPU models
> 
>   target/i386/cpu.c | 112 +++++++++++++++++++++++++++++++++++-----------
>   1 file changed, 85 insertions(+), 27 deletions(-)
> 



^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH RESEND 0/4] Add extra information to versioned CPU models
  2019-12-05  8:55 ` [PATCH RESEND 0/4] Add extra information to " Xiaoyao Li
@ 2019-12-09  2:43   ` Tao Xu
  0 siblings, 0 replies; 9+ messages in thread
From: Tao Xu @ 2019-12-09  2:43 UTC (permalink / raw)
  To: Xiaoyao Li, qemu-devel

On 12/5/2019 4:55 PM, Xiaoyao Li wrote:
> On 12/2/2019 2:32 PM, Tao Xu wrote:
>> This series of patches will remove MPX from Denverton, remove Remove
>> monitor from some CPU models. Add additional information for -cpu help
>> to indicate the changes in this version of CPU model.
>>
>> The output is as follows:
>> x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
>> x86 Broadwell-v2          Intel Core Processor (Broadwell) [no TSX]
>> x86 Broadwell-v3          Intel Core Processor (Broadwell) [IBRS]
>> x86 Broadwell-v4          Intel Core Processor (Broadwell) [no TSX, IBRS]
> 
> Above the changes of each Broadwell-v{2,3,4} are based on Broadwell-v1.
> 
>> x86 Cascadelake-Server-v2  Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES]
>> x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake) [no TSX]
> 
> But in the code, Cascadelake-Server-v3 inherits all the features in
> Cascadelake-Server-v2 and removes TSX related hle & rtm.
> 
> So if we keep the same rule based on v1, it should be
> 
>    x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake)
> [ARCH_CAPABILITIES, no TSX]

Thank you for your suggestion. I will correct this.



^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2019-12-09  2:48 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-02  6:32 [PATCH RESEND 0/4] Add extra information to versioned CPU models Tao Xu
2019-12-02  6:32 ` [PATCH RESEND 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
2019-12-02  6:32 ` [PATCH RESEND 2/4] target/i386: Remove monitor from some CPU models Tao Xu
2019-12-02  6:32 ` [PATCH RESEND 3/4] target/i386: Add new property note to versioned " Tao Xu
2019-12-02  6:32 ` [PATCH RESEND 4/4] target/i386: Add notes for " Tao Xu
2019-12-05  8:44   ` Xiaoyao Li
2019-12-09  2:47     ` Tao Xu
2019-12-05  8:55 ` [PATCH RESEND 0/4] Add extra information to " Xiaoyao Li
2019-12-09  2:43   ` Tao Xu

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).