* [PULL 0/1] target/openrisc patch queue
@ 2020-01-17 0:54 Richard Henderson
2020-01-17 0:54 ` [PULL 1/1] target/openrisc: Fix FPCSR mask to allow setting DZF Richard Henderson
2020-01-17 14:55 ` [PULL 0/1] target/openrisc patch queue Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Richard Henderson @ 2020-01-17 0:54 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-or1k-20200116
for you to fetch changes up to 97a254b3f03a184136e381c6d9fd80475e1795ac:
target/openrisc: Fix FPCSR mask to allow setting DZF (2020-01-16 14:50:43 -1000)
----------------------------------------------------------------
Fix FPSCR masking
----------------------------------------------------------------
Stafford Horne (1):
target/openrisc: Fix FPCSR mask to allow setting DZF
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PULL 1/1] target/openrisc: Fix FPCSR mask to allow setting DZF
2020-01-17 0:54 [PULL 0/1] target/openrisc patch queue Richard Henderson
@ 2020-01-17 0:54 ` Richard Henderson
2020-01-17 14:55 ` [PULL 0/1] target/openrisc patch queue Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2020-01-17 0:54 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Stafford Horne
From: Stafford Horne <shorne@gmail.com>
The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.
This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 59e1413279..6f75ea0505 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
float_round_down
};
- env->fpcsr = val & 0x7ff;
+ env->fpcsr = val & 0xfff;
set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PULL 0/1] target/openrisc patch queue
2020-01-17 0:54 [PULL 0/1] target/openrisc patch queue Richard Henderson
2020-01-17 0:54 ` [PULL 1/1] target/openrisc: Fix FPCSR mask to allow setting DZF Richard Henderson
@ 2020-01-17 14:55 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2020-01-17 14:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 17 Jan 2020 at 00:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:
>
> ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)
>
> are available in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-or1k-20200116
>
> for you to fetch changes up to 97a254b3f03a184136e381c6d9fd80475e1795ac:
>
> target/openrisc: Fix FPCSR mask to allow setting DZF (2020-01-16 14:50:43 -1000)
>
> ----------------------------------------------------------------
> Fix FPSCR masking
>
> ----------------------------------------------------------------
> Stafford Horne (1):
> target/openrisc: Fix FPCSR mask to allow setting DZF
>
> target/openrisc/fpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-01-17 14:55 ` [PULL 0/1] target/openrisc patch queue Peter Maydell
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