From: Aurelien Jarno <aurelien@aurel32.net>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled
Date: Tue, 21 Jan 2020 21:37:10 +0100 [thread overview]
Message-ID: <20200121203710.GA3061510@aurel32.net> (raw)
In-Reply-To: <CAKmqyKNd8ihSXTcdS9da_pGkinFVnJKAAsg4fR4LzBEUH8NZ2A@mail.gmail.com>
Hi,
On 2020-01-20 10:31, Alistair Francis wrote:
> On Mon, Jan 6, 2020 at 2:59 AM Aurelien Jarno <aurelien@aurel32.net> wrote:
> >
> > On 2020-01-05 17:36, Aurelien Jarno wrote:
> > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > > index e0d4586760..2789215b5e 100644
> > > > --- a/target/riscv/csr.c
> > > > +++ b/target/riscv/csr.c
> > >
> > > [ snip ]
> > >
> > > > @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
> > > > {
> > > > target_ulong mstatus = env->mstatus;
> > > > target_ulong mask = 0;
> > > > + int dirty;
> > > >
> > > > /* flush tlb on mstatus fields that affect VM */
> > > > if (env->priv_ver <= PRIV_VERSION_1_09_1) {
> > > > @@ -340,8 +341,9 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
> > > >
> > > > mstatus = (mstatus & ~mask) | (val & mask);
> > > >
> > > > - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
> > > > - ((mstatus & MSTATUS_XS) == MSTATUS_XS);
> > > > + dirty = (riscv_cpu_fp_enabled(env) &&
> > > > + ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |
> > > > + ((mstatus & MSTATUS_XS) == MSTATUS_XS);
> > > > mstatus = set_field(mstatus, MSTATUS_SD, dirty);
> > > > env->mstatus = mstatus;
> > >
> > > This patch, and more precisely the above two hunks broke
> > > qemu-system-riscv64. More precisely, when running a Debian sid system
> > > inside QEMU, sshd hangs during key exchange.
> >
> > The problem is that at this stage, mstatus != env->status. Prior to that
> > patch, dirty was computed exclusively on the new mstatus status, after
> > the update by val. With this patch, riscv_cpu_fp_enabled() refers to the
> > old value of mstatus. Therefore when FS is changed from "Off" (FS = 00)
> > to "Dirty" (FS == 11), the SD bit is not set.
>
> Thanks for reporting this!
>
> Can you try this branch (it should be a PR to mainline QEMU soon) and
> let me know if that fixes the issue?
>
> https://github.com/palmer-dabbelt/qemu/commits/for-master
Thanks for the patchset. I confirm this fixes the issue.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2020-01-21 20:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 15:21 [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled Alistair Francis
2020-01-05 16:36 ` Aurelien Jarno
2020-01-05 16:59 ` Aurelien Jarno
2020-01-20 0:31 ` Alistair Francis
2020-01-21 20:37 ` Aurelien Jarno [this message]
2020-01-21 22:20 ` Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Alistair Francis
2019-08-23 15:44 ` Peter Maydell
2019-08-23 15:43 ` Alistair Francis
2019-09-10 13:16 ` Palmer Dabbelt
2019-09-10 13:16 ` [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Palmer Dabbelt
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