From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
bmeng.cn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
alistair23@gmail.com
Subject: Re: [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
Date: Tue, 10 Sep 2019 06:16:31 -0700 (PDT) [thread overview]
Message-ID: <mhng-a8e09e2d-e0a4-4de5-88f6-d47db22fb1e8@palmer-si-x1e> (raw)
In-Reply-To: <066a2c520c38b0c175c052d6a3385d5661764833.1566573576.git.alistair.francis@wdc.com>
On Fri, 23 Aug 2019 08:21:25 PDT (-0700), Alistair Francis wrote:
> Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
> flags.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index eb7b5b0af3..0347be453b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -301,7 +301,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> #else
> *flags = cpu_mmu_index(env, 0);
> if (riscv_cpu_fp_enabled(env)) {
> - *flags |= env->mstatus & MSTATUS_FS;
> + *flags |= TB_FLAGS_MSTATUS_FS;
I thought this was a functional change, but it's not: fp_enabled() checks
mstatus already.
> }
> #endif
> }
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
next prev parent reply other threads:[~2019-09-10 13:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 15:21 [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled Alistair Francis
2020-01-05 16:36 ` Aurelien Jarno
2020-01-05 16:59 ` Aurelien Jarno
2020-01-20 0:31 ` Alistair Francis
2020-01-21 20:37 ` Aurelien Jarno
2020-01-21 22:20 ` Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask Alistair Francis
2019-08-23 15:21 ` [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point Alistair Francis
2019-08-23 15:44 ` Peter Maydell
2019-08-23 15:43 ` Alistair Francis
2019-09-10 13:16 ` Palmer Dabbelt [this message]
2019-09-10 13:16 ` [Qemu-devel] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2 Palmer Dabbelt
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