* [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns
@ 2020-02-25 14:39 Peter Maydell
2020-02-25 20:32 ` Alex Bennée
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2020-02-25 14:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Alex Bennée, Richard Henderson
Add patterns for the new instructions in the v8.3-RCPC and
v8.4-RCPC extensions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
This is what I used for testing the RCPC QEMU patches I sent out
the other day. Did I get the @ section syntax here right?
aarch64.risu | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/aarch64.risu b/aarch64.risu
index c4eda7a..8f08cd0 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -3019,3 +3019,35 @@ SM3TT2B A64_V 1100 1110 010 rm:5 10 imm:2 11 rn:5 rd:5
XAR A64_V 1100 1110 100 rm:5 imm:6 rn:5 rd:5
@
+
+# v8.3-RCPC instructions
+@v8_3_rcpc
+
+# LDAPR, LDAPRH, LDAPRB
+# As usual, the $rn != $rt constraint is risu-imposed, not architectural
+LDAPR A64 sz:2 111000 101 11111 1100 00 rn:5 rt:5 \
+!constraints { $rn != 31 && $rn != $rt } \
+!memory { align(1 << $sz); reg_plus_imm($rn, 0); }
+
+@
+
+# v8.4-RCPC instructions
+# As usual, the $rn != $rt constraint is risu-imposed, not architectural
+@v8_4_rcpc
+STLUR A64 sz:2 011001 00 0 imm:9 00 rn:5 rt:5 \
+!constraints { $rn != 31 && $rn != $rt } \
+!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
+
+LDAPUR A64 sz:2 011001 01 0 imm:9 00 rn:5 rt:5 \
+!constraints { $rn != 31 && $rn != $rt } \
+!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
+
+LDAPURS64 A64 sz:2 011001 10 0 imm:9 00 rn:5 rt:5 \
+!constraints { $rn != 31 && $rn != $rt && $sz != 3 } \
+!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
+
+LDAPURS32 A64 sz:2 011001 11 0 imm:9 00 rn:5 rt:5 \
+!constraints { $rn != 31 && $rn != $rt && $sz < 2 } \
+!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
+
+@
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns
2020-02-25 14:39 [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns Peter Maydell
@ 2020-02-25 20:32 ` Alex Bennée
2020-02-27 17:27 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Alex Bennée @ 2020-02-25 20:32 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, Richard Henderson, qemu-devel
Peter Maydell <peter.maydell@linaro.org> writes:
> Add patterns for the new instructions in the v8.3-RCPC and
> v8.4-RCPC extensions.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> This is what I used for testing the RCPC QEMU patches I sent out
> the other day. Did I get the @ section syntax here right?
Yep ;-)
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
>
> aarch64.risu | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/aarch64.risu b/aarch64.risu
> index c4eda7a..8f08cd0 100644
> --- a/aarch64.risu
> +++ b/aarch64.risu
> @@ -3019,3 +3019,35 @@ SM3TT2B A64_V 1100 1110 010 rm:5 10 imm:2 11 rn:5 rd:5
> XAR A64_V 1100 1110 100 rm:5 imm:6 rn:5 rd:5
>
> @
> +
> +# v8.3-RCPC instructions
> +@v8_3_rcpc
> +
> +# LDAPR, LDAPRH, LDAPRB
> +# As usual, the $rn != $rt constraint is risu-imposed, not architectural
> +LDAPR A64 sz:2 111000 101 11111 1100 00 rn:5 rt:5 \
> +!constraints { $rn != 31 && $rn != $rt } \
> +!memory { align(1 << $sz); reg_plus_imm($rn, 0); }
> +
> +@
> +
> +# v8.4-RCPC instructions
> +# As usual, the $rn != $rt constraint is risu-imposed, not architectural
> +@v8_4_rcpc
> +STLUR A64 sz:2 011001 00 0 imm:9 00 rn:5 rt:5 \
> +!constraints { $rn != 31 && $rn != $rt } \
> +!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
> +
> +LDAPUR A64 sz:2 011001 01 0 imm:9 00 rn:5 rt:5 \
> +!constraints { $rn != 31 && $rn != $rt } \
> +!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
> +
> +LDAPURS64 A64 sz:2 011001 10 0 imm:9 00 rn:5 rt:5 \
> +!constraints { $rn != 31 && $rn != $rt && $sz != 3 } \
> +!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
> +
> +LDAPURS32 A64 sz:2 011001 11 0 imm:9 00 rn:5 rt:5 \
> +!constraints { $rn != 31 && $rn != $rt && $sz < 2 } \
> +!memory { align(1 << $sz); reg_plus_imm($rn, $imm); }
> +
> +@
--
Alex Bennée
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns
2020-02-25 20:32 ` Alex Bennée
@ 2020-02-27 17:27 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2020-02-27 17:27 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-arm, Richard Henderson, QEMU Developers
On Tue, 25 Feb 2020 at 20:32, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > Add patterns for the new instructions in the v8.3-RCPC and
> > v8.4-RCPC extensions.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > This is what I used for testing the RCPC QEMU patches I sent out
> > the other day. Did I get the @ section syntax here right?
>
> Yep ;-)
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Thanks; applied to risu master.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-02-25 14:39 [PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns Peter Maydell
2020-02-25 20:32 ` Alex Bennée
2020-02-27 17:27 ` Peter Maydell
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