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From: Peter Xu <peterx@redhat.com>
To: Liu Yi L <yi.l.liu@intel.com>
Cc: jean-philippe@linaro.org, kevin.tian@intel.com,
	Jacob Pan <jacob.jun.pan@linux.intel.com>,
	Yi Sun <yi.y.sun@linux.intel.com>,
	Eduardo Habkost <ehabkost@redhat.com>,
	kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com,
	qemu-devel@nongnu.org, eric.auger@redhat.com,
	alex.williamson@redhat.com, pbonzini@redhat.com,
	hao.wu@intel.com, yi.y.sun@intel.com,
	Richard Henderson <rth@twiddle.net>,
	david@gibson.dropbear.id.au
Subject: Re: [PATCH v1 20/22] intel_iommu: propagate PASID-based iotlb invalidation to host
Date: Tue, 24 Mar 2020 14:34:23 -0400
Message-ID: <20200324183423.GE127076@xz-x1> (raw)
In-Reply-To: <1584880579-12178-21-git-send-email-yi.l.liu@intel.com>

On Sun, Mar 22, 2020 at 05:36:17AM -0700, Liu Yi L wrote:
> This patch propagates PASID-based iotlb invalidation to host.
> 
> Intel VT-d 3.0 supports nested translation in PASID granular.
> Guest SVA support could be implemented by configuring nested
> translation on specific PASID. This is also known as dual stage
> DMA translation.
> 
> Under such configuration, guest owns the GVA->GPA translation
> which is configured as first level page table in host side for
> a specific pasid, and host owns GPA->HPA translation. As guest
> owns first level translation table, piotlb invalidation should
> be propagated to host since host IOMMU will cache first level
> page table related mappings during DMA address translation.
> 
> This patch traps the guest PASID-based iotlb flush and propagate
> it to host.
> 
> Cc: Kevin Tian <kevin.tian@intel.com>
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: Yi Sun <yi.y.sun@linux.intel.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
> ---
>  hw/i386/intel_iommu.c          | 139 +++++++++++++++++++++++++++++++++++++++++
>  hw/i386/intel_iommu_internal.h |   7 +++
>  2 files changed, 146 insertions(+)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index b9ac07d..10d314d 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3134,15 +3134,154 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s,
>      return (ret == 0) ? true : false;
>  }
>  
> +/**
> + * Caller of this function should hold iommu_lock.
> + */
> +static void vtd_invalidate_piotlb(IntelIOMMUState *s,
> +                                  VTDBus *vtd_bus,
> +                                  int devfn,
> +                                  DualIOMMUStage1Cache *stage1_cache)
> +{
> +    VTDHostIOMMUContext *vtd_dev_icx;
> +    HostIOMMUContext *host_icx;
> +
> +    vtd_dev_icx = vtd_bus->dev_icx[devfn];
> +    if (!vtd_dev_icx) {
> +        goto out;
> +    }
> +    host_icx = vtd_dev_icx->host_icx;
> +    if (!host_icx) {
> +        goto out;
> +    }
> +    if (host_iommu_ctx_flush_stage1_cache(host_icx, stage1_cache)) {
> +        error_report("Cache flush failed");

I think this should not easily be triggered by the guest, but just in
case... Let's use error_report_once() to be safe.

> +    }
> +out:
> +    return;
> +}
> +
> +static inline bool vtd_pasid_cache_valid(
> +                          VTDPASIDAddressSpace *vtd_pasid_as)
> +{
> +    return vtd_pasid_as->iommu_state &&

This check can be dropped because always true?

If you agree with both the changes, please add:

Reviewed-by: Peter Xu <peterx@redhat.com>

> +           (vtd_pasid_as->iommu_state->pasid_cache_gen
> +             == vtd_pasid_as->pasid_cache_entry.pasid_cache_gen);
> +}
> +
> +/**
> + * This function is a loop function for the s->vtd_pasid_as
> + * list with VTDPIOTLBInvInfo as execution filter. It propagates
> + * the piotlb invalidation to host. Caller of this function
> + * should hold iommu_lock.
> + */
> +static void vtd_flush_pasid_iotlb(gpointer key, gpointer value,
> +                                  gpointer user_data)
> +{
> +    VTDPIOTLBInvInfo *piotlb_info = user_data;
> +    VTDPASIDAddressSpace *vtd_pasid_as = value;
> +    uint16_t did;
> +
> +    /*
> +     * Needs to check whether the pasid entry cache stored in
> +     * vtd_pasid_as is valid or not. "invalid" means the pasid
> +     * cache has been flushed, thus host should have done piotlb
> +     * invalidation together with a pasid cache invalidation, so
> +     * no need to pass down piotlb invalidation to host for better
> +     * performance. Only when pasid entry cache is "valid", should
> +     * a piotlb invalidation be propagated to host since it means
> +     * guest just modified a mapping in its page table.
> +     */
> +    if (!vtd_pasid_cache_valid(vtd_pasid_as)) {
> +        return;
> +    }
> +
> +    did = vtd_pe_get_domain_id(
> +                &(vtd_pasid_as->pasid_cache_entry.pasid_entry));
> +
> +    if ((piotlb_info->domain_id == did) &&
> +        (piotlb_info->pasid == vtd_pasid_as->pasid)) {
> +        vtd_invalidate_piotlb(vtd_pasid_as->iommu_state,
> +                              vtd_pasid_as->vtd_bus,
> +                              vtd_pasid_as->devfn,
> +                              piotlb_info->stage1_cache);
> +    }
> +
> +    /*
> +     * TODO: needs to add QEMU piotlb flush when QEMU piotlb
> +     * infrastructure is ready. For now, it is enough for passthru
> +     * devices.
> +     */
> +}
> +
>  static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
>                                          uint16_t domain_id,
>                                          uint32_t pasid)
>  {
> +    VTDPIOTLBInvInfo piotlb_info;
> +    DualIOMMUStage1Cache *stage1_cache;
> +    struct iommu_cache_invalidate_info *cache_info;
> +
> +    stage1_cache = g_malloc0(sizeof(*stage1_cache));
> +    stage1_cache->pasid = pasid;
> +
> +    cache_info = &stage1_cache->cache_info;
> +    cache_info->version = IOMMU_UAPI_VERSION;
> +    cache_info->cache = IOMMU_CACHE_INV_TYPE_IOTLB;
> +    cache_info->granularity = IOMMU_INV_GRANU_PASID;
> +    cache_info->pasid_info.pasid = pasid;
> +    cache_info->pasid_info.flags = IOMMU_INV_PASID_FLAGS_PASID;
> +
> +    piotlb_info.domain_id = domain_id;
> +    piotlb_info.pasid = pasid;
> +    piotlb_info.stage1_cache = stage1_cache;
> +
> +    vtd_iommu_lock(s);
> +    /*
> +     * Here loops all the vtd_pasid_as instances in s->vtd_pasid_as
> +     * to find out the affected devices since piotlb invalidation
> +     * should check pasid cache per architecture point of view.
> +     */
> +    g_hash_table_foreach(s->vtd_pasid_as,
> +                         vtd_flush_pasid_iotlb, &piotlb_info);
> +    vtd_iommu_unlock(s);
> +    g_free(stage1_cache);
>  }
>  
>  static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
>                               uint32_t pasid, hwaddr addr, uint8_t am, bool ih)
>  {
> +    VTDPIOTLBInvInfo piotlb_info;
> +    DualIOMMUStage1Cache *stage1_cache;
> +    struct iommu_cache_invalidate_info *cache_info;
> +
> +    stage1_cache = g_malloc0(sizeof(*stage1_cache));
> +    stage1_cache->pasid = pasid;
> +
> +    cache_info = &stage1_cache->cache_info;
> +    cache_info->version = IOMMU_UAPI_VERSION;
> +    cache_info->cache = IOMMU_CACHE_INV_TYPE_IOTLB;
> +    cache_info->granularity = IOMMU_INV_GRANU_ADDR;
> +    cache_info->addr_info.flags = IOMMU_INV_ADDR_FLAGS_PASID;
> +    cache_info->addr_info.flags |= ih ? IOMMU_INV_ADDR_FLAGS_LEAF : 0;
> +    cache_info->addr_info.pasid = pasid;
> +    cache_info->addr_info.addr = addr;
> +    cache_info->addr_info.granule_size = 1 << (12 + am);
> +    cache_info->addr_info.nb_granules = 1;
> +
> +    piotlb_info.domain_id = domain_id;
> +    piotlb_info.pasid = pasid;
> +    piotlb_info.stage1_cache = stage1_cache;
> +
> +    vtd_iommu_lock(s);
> +    /*
> +     * Here loops all the vtd_pasid_as instances in s->vtd_pasid_as
> +     * to find out the affected devices since piotlb invalidation
> +     * should check pasid cache per architecture point of view.
> +     */
> +    g_hash_table_foreach(s->vtd_pasid_as,
> +                         vtd_flush_pasid_iotlb, &piotlb_info);
> +    vtd_iommu_unlock(s);
> +    g_free(stage1_cache);
>  }
>  
>  static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 314e2c4..967cc4f 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -560,6 +560,13 @@ struct VTDPASIDCacheInfo {
>                                        VTD_PASID_CACHE_DEVSI)
>  typedef struct VTDPASIDCacheInfo VTDPASIDCacheInfo;
>  
> +struct VTDPIOTLBInvInfo {
> +    uint16_t domain_id;
> +    uint32_t pasid;
> +    DualIOMMUStage1Cache *stage1_cache;
> +};
> +typedef struct VTDPIOTLBInvInfo VTDPIOTLBInvInfo;
> +
>  /* PASID Table Related Definitions */
>  #define VTD_PASID_DIR_BASE_ADDR_MASK  (~0xfffULL)
>  #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL)
> -- 
> 2.7.4
> 

-- 
Peter Xu



  reply index

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-22 12:35 [PATCH v1 00/22] intel_iommu: expose Shared Virtual Addressing to VMs Liu Yi L
2020-03-22 12:35 ` [PATCH v1 01/22] scripts/update-linux-headers: Import iommu.h Liu Yi L
2020-03-22 12:35 ` [PATCH v1 02/22] header file update VFIO/IOMMU vSVA APIs Liu Yi L
2020-03-29 16:32   ` Auger Eric
2020-03-30  7:06     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 03/22] vfio: check VFIO_TYPE1_NESTING_IOMMU support Liu Yi L
2020-03-22 12:36 ` [PATCH v1 04/22] hw/iommu: introduce HostIOMMUContext Liu Yi L
2020-03-23 20:58   ` Peter Xu
2020-03-24 10:00     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 05/22] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps Liu Yi L
2020-03-22 12:36 ` [PATCH v1 06/22] hw/pci: introduce pci_device_set/unset_iommu_context() Liu Yi L
2020-03-23 21:15   ` Peter Xu
2020-03-24 10:02     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 07/22] intel_iommu: add set/unset_iommu_context callback Liu Yi L
2020-03-23 21:29   ` Peter Xu
2020-03-24 11:15     ` Liu, Yi L
2020-03-24 15:24       ` Peter Xu
2020-03-25  9:37         ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 08/22] vfio: init HostIOMMUContext per-container Liu Yi L
     [not found]   ` <20200323213943.GR127076@xz-x1>
2020-03-24 13:03     ` Liu, Yi L
2020-03-24 14:45       ` Peter Xu
2020-03-25  9:30         ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 09/22] vfio/common: check PASID alloc/free availability Liu Yi L
2020-03-23 22:06   ` Peter Xu
2020-03-24 11:18     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 10/22] intel_iommu: add virtual command capability support Liu Yi L
2020-03-22 12:36 ` [PATCH v1 11/22] intel_iommu: process PASID cache invalidation Liu Yi L
2020-03-22 12:36 ` [PATCH v1 12/22] intel_iommu: add PASID cache management infrastructure Liu Yi L
2020-03-24 17:32   ` Peter Xu
2020-03-25 12:20     ` Liu, Yi L
2020-03-25 14:52       ` Peter Xu
2020-03-26  6:15         ` Liu, Yi L
2020-03-26 13:57           ` Liu, Yi L
2020-03-26 15:53             ` Peter Xu
2020-03-27  1:33               ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 13/22] vfio: add bind stage-1 page table support Liu Yi L
2020-03-24 17:41   ` Peter Xu
2020-03-25  9:49     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 14/22] intel_iommu: bind/unbind guest page table to host Liu Yi L
2020-03-24 17:46   ` Peter Xu
2020-03-25 12:42     ` Liu, Yi L
2020-03-25 14:56       ` Peter Xu
2020-03-26  3:04         ` Liu, Yi L
2020-03-25 12:47     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 15/22] intel_iommu: replay guest pasid bindings " Liu Yi L
2020-03-24 18:00   ` Peter Xu
2020-03-25 13:14     ` Liu, Yi L
2020-03-25 15:06       ` Peter Xu
2020-03-26  3:17         ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 16/22] intel_iommu: replay pasid binds after context cache invalidation Liu Yi L
2020-03-24 18:07   ` Peter Xu
2020-03-25 13:18     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 17/22] intel_iommu: do not pass down pasid bind for PASID #0 Liu Yi L
2020-03-24 18:13   ` Peter Xu
2020-03-25 10:42     ` Liu, Yi L
2020-03-25 15:12       ` Peter Xu
2020-03-26  2:42         ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 18/22] vfio: add support for flush iommu stage-1 cache Liu Yi L
2020-03-24 18:19   ` Peter Xu
2020-03-25 10:40     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 19/22] intel_iommu: process PASID-based iotlb invalidation Liu Yi L
2020-03-24 18:26   ` Peter Xu
2020-03-25 13:36     ` Liu, Yi L
2020-03-25 15:15       ` Peter Xu
2020-03-29 11:17         ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 20/22] intel_iommu: propagate PASID-based iotlb invalidation to host Liu Yi L
2020-03-24 18:34   ` Peter Xu [this message]
2020-03-25 13:21     ` Liu, Yi L
2020-03-26  5:41       ` Liu, Yi L
2020-03-26 13:02         ` Peter Xu
2020-03-26 13:22           ` Peter Xu
2020-03-26 13:33             ` Liu, Yi L
2020-03-26 13:23           ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 21/22] intel_iommu: process PASID-based Device-TLB invalidation Liu Yi L
2020-03-24 18:36   ` Peter Xu
2020-03-25  9:19     ` Liu, Yi L
2020-03-22 12:36 ` [PATCH v1 22/22] intel_iommu: modify x-scalable-mode to be string option Liu Yi L
2020-03-24 18:39   ` Peter Xu
2020-03-25 13:22     ` Liu, Yi L
2020-03-22 13:25 ` [PATCH v1 00/22] intel_iommu: expose Shared Virtual Addressing to VMs no-reply

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