* [PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions
@ 2020-04-27 15:29 Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Stephen Long @ 2020-04-27 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Used one macro to cover the helper functions for
SVE2 AESC, AESIMC, AESE, AESD.
No macro was used to implement the helper functions for
SM4E, SM4EKEY, RAX1.
Stephen Long (3):
target/arm: Implement SVE2 AESMC, AESIMC
target/arm: Implement SVE2 AESE, AESD, SM4E
target/arm: Implement SVE2 SM4EKEY, RAX1
target/arm/cpu.h | 5 +++
target/arm/helper-sve.h | 10 ++++++
target/arm/sve.decode | 20 ++++++++++++
target/arm/sve_helper.c | 46 +++++++++++++++++++++++++++
target/arm/translate-sve.c | 64 ++++++++++++++++++++++++++++++++++++++
5 files changed, 145 insertions(+)
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC
2020-04-27 15:29 [PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
@ 2020-04-27 15:29 ` Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
2 siblings, 0 replies; 4+ messages in thread
From: Stephen Long @ 2020-04-27 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 3 +++
target/arm/sve.decode | 10 ++++++++++
target/arm/sve_helper.c | 15 +++++++++++++++
target/arm/translate-sve.c | 18 ++++++++++++++++++
4 files changed, 46 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 51ad60e5c3..340fe07801 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2690,3 +2690,6 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index de3768c24a..f58eb04d11 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -92,6 +92,10 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
+# One operand with unused vector element size
+@rdn_e0 ........ .. ........... . ..... rd:5 \
+ &rr_esz rn=%reg_movprfx esz=0
+
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
@@ -1419,3 +1423,9 @@ STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
# SVE2 32-bit scatter non-temporal store (vector plus scalar)
STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=0 esz=2 scale=0
+
+#### SVE2 Crypto Extensions
+
+## SVE2 crypto unary operations
+AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
+AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index cd5c6f7fb0..5c3dee048d 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7516,3 +7516,18 @@ void HELPER(fmmla_d)(void *vd, void *va, void *vn, void *vm,
d[3] = float64_add(a[3], float64_add(p0, p1, status), status);
}
}
+
+#define DO_SVE2_AES_CRYPTO(NAME, FN) \
+void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ intptr_t decrypt = simd_data(desc); \
+ for (i = 0; i < opr_sz; i += 16) { \
+ HELPER(FN)(vd + i, vn + i, decrypt); \
+ } \
+}
+
+DO_SVE2_AES_CRYPTO(sve2_aesmc, crypto_aesmc);
+DO_SVE2_AES_CRYPTO(sve2_aesimc, crypto_aesmc);
+
+#undef DO_SVE2_AES_CRYPTO
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 86c3d0ed11..f70b7f44e3 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7956,3 +7956,21 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
};
return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
}
+
+#define DO_SVE2_AES_CRYPTO(NAME, name, DECRYPT) \
+static bool trans_##NAME(DisasContext *s, arg_rr_esz *a) \
+{ \
+ if (!dc_isar_feature(aa64_sve2_aes, s)) { \
+ return false; \
+ } \
+ if (sve_access_check(s)) { \
+ unsigned vsz = vec_full_reg_size(s); \
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), \
+ vec_full_reg_offset(s, a->rn), \
+ vsz, vsz, DECRYPT, gen_helper_sve2_##name); \
+ } \
+ return true; \
+}
+
+DO_SVE2_AES_CRYPTO(AESMC, aesmc, 0)
+DO_SVE2_AES_CRYPTO(AESIMC, aesimc, 1)
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH RFC v2 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E
2020-04-27 15:29 [PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
@ 2020-04-27 15:29 ` Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
2 siblings, 0 replies; 4+ messages in thread
From: Stephen Long @ 2020-04-27 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/cpu.h | 5 +++++
target/arm/helper-sve.h | 4 ++++
target/arm/sve.decode | 6 ++++++
target/arm/sve_helper.c | 11 +++++++++++
target/arm/translate-sve.c | 16 ++++++++++++++++
5 files changed, 42 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d41c4a08c0..8b1dc38b9c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3880,6 +3880,11 @@ static inline bool isar_feature_aa64_sve2_f64mm(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 340fe07801..6cd6fdfae1 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2693,3 +2693,7 @@ DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f58eb04d11..1cb5792bb1 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
+@pd5_pn5_e0 ........ ........ ...... rn:5 rd:5 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@@ -1429,3 +1430,8 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
## SVE2 crypto unary operations
AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
+
+## SVE2 crpyto destructive binary operations
+AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
+AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
+SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 5c3dee048d..4204659276 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7530,4 +7530,15 @@ void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
DO_SVE2_AES_CRYPTO(sve2_aesmc, crypto_aesmc);
DO_SVE2_AES_CRYPTO(sve2_aesimc, crypto_aesmc);
+DO_SVE2_AES_CRYPTO(sve2_aese, crypto_aese);
+DO_SVE2_AES_CRYPTO(sve2_aesd, crypto_aese);
+
#undef DO_SVE2_AES_CRYPTO
+
+void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4e)(vd + i, vn + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f70b7f44e3..6b26d8c512 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7974,3 +7974,19 @@ static bool trans_##NAME(DisasContext *s, arg_rr_esz *a) \
DO_SVE2_AES_CRYPTO(AESMC, aesmc, 0)
DO_SVE2_AES_CRYPTO(AESIMC, aesimc, 1)
+DO_SVE2_AES_CRYPTO(AESE, aese, 0)
+DO_SVE2_AES_CRYPTO(AESD, aesd, 1)
+
+static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vsz, vsz, 0, gen_helper_sve2_sm4e);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1
2020-04-27 15:29 [PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
@ 2020-04-27 15:29 ` Stephen Long
2 siblings, 0 replies; 4+ messages in thread
From: Stephen Long @ 2020-04-27 15:29 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 3 +++
target/arm/sve.decode | 4 ++++
target/arm/sve_helper.c | 20 ++++++++++++++++++++
target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++
4 files changed, 57 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 6cd6fdfae1..e509137e4a 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2697,3 +2697,6 @@ DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 1cb5792bb1..278530ca83 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1435,3 +1435,7 @@ AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
+
+## SVE2 crypto constructive binary operations
+SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
+RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 4204659276..8307abc401 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7542,3 +7542,23 @@ void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
HELPER(crypto_sm4e)(vd + i, vn + i);
}
}
+
+void HELPER(sve2_sm4ekey)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4ekey)(vd + i, vn + i, vm + i);
+ }
+}
+
+void HELPER(sve2_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+
+ for (i = 0; i < opr_sz; ++i) {
+ uint64_t nn = n[i];
+ uint64_t mm = m[i];
+ d[i] = nn ^ rol64(mm, 1);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6b26d8c512..2baa51b2b2 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7990,3 +7990,33 @@ static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
}
return true;
}
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_sm4ekey);
+ }
+ return true;
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_rax1);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-04-27 15:37 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-04-27 15:29 [PATCH RFC v2 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
2020-04-27 15:29 ` [PATCH RFC v2 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
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