From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions
Date: Wed, 22 Jul 2020 17:16:18 +0800 [thread overview]
Message-ID: <20200722091641.8834-56-frank.chang@sifive.com> (raw)
In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Remove clear function from helper function as the tail elements
are unchanged in RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 69 +++++++++++++++++-------------------
1 file changed, 33 insertions(+), 36 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8dccec4e04..39245b5ac8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4565,15 +4565,13 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
*** Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
-#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
- uint32_t vta = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
@@ -4584,56 +4582,55 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, vta, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb)
-GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh)
-GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl)
-GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq)
+GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD)
/* vd[0] = maxu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX)
/* vd[0] = max(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX)
/* vd[0] = minu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN)
/* vd[0] = min(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN)
/* vd[0] = and(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb)
-GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh)
-GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl)
-GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq)
+GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND)
+GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND)
+GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND)
+GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND)
/* vd[0] = or(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb)
-GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh)
-GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl)
-GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq)
+GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR)
+GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR)
+GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR)
+GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR)
/* vd[0] = xor(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb)
-GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
-GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
-GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
--
2.17.1
next prev parent reply other threads:[~2020-07-22 9:38 UTC|newest]
Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-22 9:15 [RFC v2 00/76] target/riscv: support vector extension v0.9 frank.chang
2020-07-22 9:15 ` [RFC v2 01/76] target/riscv: drop vector 0.7.1 support frank.chang
2020-07-22 16:37 ` Alistair Francis
2020-07-27 19:54 ` Palmer Dabbelt
2020-07-27 19:55 ` Alistair Francis
2020-07-30 8:07 ` Frank Chang
2020-07-30 12:27 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 frank.chang
2020-07-22 16:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-22 16:18 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-22 9:15 ` [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-22 9:15 ` [RFC v2 06/76] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-22 9:15 ` [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-07-22 16:19 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field frank.chang
2020-07-22 16:33 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus " frank.chang
2020-07-22 16:34 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status frank.chang
2020-07-22 16:53 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register frank.chang
2020-07-22 16:54 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-22 16:57 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-22 16:58 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-22 17:04 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL frank.chang
2020-07-22 17:30 ` Richard Henderson
2020-07-23 2:11 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA frank.chang
2020-07-22 18:00 ` Richard Henderson
2020-07-23 2:18 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 17/76] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-22 9:15 ` [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-07-22 18:08 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper frank.chang
2020-07-22 19:15 ` Richard Henderson
2020-07-23 7:13 ` Frank Chang
2020-07-23 16:14 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans frank.chang
2020-07-22 9:15 ` [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-22 20:00 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-22 9:15 ` [RFC v2 23/76] target/riscv: rvv-0.9: index " frank.chang
2020-07-22 9:15 ` [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-22 9:15 ` [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-22 9:15 ` [RFC v2 26/76] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-22 9:15 ` [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-29 20:30 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-30 12:44 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-30 12:52 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-30 13:05 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-30 13:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-30 13:26 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-30 13:29 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-30 13:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended frank.chang
2020-07-30 13:43 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-22 9:16 ` [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-30 14:50 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction frank.chang
2020-07-30 19:57 ` Richard Henderson
2020-07-30 20:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions frank.chang
2020-07-30 20:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 42/76] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-30 20:14 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-30 20:35 ` Richard Henderson
2020-07-31 10:17 ` Frank Chang
2020-07-31 17:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-30 20:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions frank.chang
2020-07-30 20:47 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-22 9:16 ` [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-30 21:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-30 21:04 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-30 21:19 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-30 21:24 ` Richard Henderson
2020-08-04 2:40 ` Frank Chang
2020-08-05 16:48 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-30 21:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 52/76] fpu: implement full set compare for fp16 frank.chang
2020-07-22 11:35 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-30 21:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-22 9:16 ` frank.chang [this message]
2020-07-22 9:16 ` [RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions frank.chang
2020-07-31 15:13 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-22 9:16 ` [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-31 15:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 59/76] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-31 16:05 ` Richard Henderson
2020-08-03 10:35 ` Frank Chang
2020-08-03 18:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-31 16:07 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-31 16:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-31 16:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-22 9:16 ` [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-31 16:59 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-31 17:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-31 17:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-31 17:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation frank.chang
2020-07-22 9:16 ` [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-22 9:16 ` [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-22 9:16 ` [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-31 17:10 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 72/76] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-31 17:18 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 73/76] fpu: fix float16 nan check frank.chang
2020-07-22 9:16 ` [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-07-22 9:16 ` [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-07-31 17:25 ` Richard Henderson
2020-08-03 11:31 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 frank.chang
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).