* [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions
@ 2020-07-24 4:58 Lijun Pan
2020-07-24 4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
this version. In v4 version, coding style issues are fixed, community
reviews/suggestions are taken into consideration. 1/11 - 5/11 of v4 were
accepted by David Gibson, and 9/11 of v4 was accepted by Lauren Vivier.
This v5 version updates PPC_FEATURE2_ARCH_3_10 definition in 6/11 of v4,
rebases 7/11 8/11 10/11 11/11 of v4, and integrates vmsumudm/vmsumcud
patch.
Lijun Pan (6):
Update PowerPC AT_HWCAP2 definition
target/ppc: add vmulld to INDEX_op_mul_vec case
target/ppc: add vmulh{su}w instructions
target/ppc: add vmulh{su}d instructions
target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
target/ppc: add vmsumudm vmsumcud instructions
disas/ppc.c | 2 +
include/elf.h | 1 +
target/ppc/helper.h | 16 +++-
target/ppc/int_helper.c | 111 +++++++++++++++++++++++++++-
target/ppc/translate.c | 4 +-
target/ppc/translate/vmx-impl.inc.c | 62 +++++++++++-----
target/ppc/translate/vmx-ops.inc.c | 25 ++++++-
tcg/ppc/tcg-target.h | 2 +
tcg/ppc/tcg-target.inc.c | 12 ++-
9 files changed, 208 insertions(+), 27 deletions(-)
--
2.23.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 17:54 ` Richard Henderson
2020-07-24 4:58 ` [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v5: match the definition with that in linux's
arch/powerpc/include/uapi/asm/cputable.h
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/elf.h b/include/elf.h
index 8fbfe60e09..4fc1276ab6 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -554,6 +554,7 @@ typedef struct {
#define PPC_FEATURE2_HTM_NOSC 0x01000000
#define PPC_FEATURE2_ARCH_3_00 0x00800000
#define PPC_FEATURE2_HAS_IEEE128 0x00400000
+#define PPC_FEATURE2_ARCH_3_10 0x00040000
/* Bits present in AT_HWCAP for Sparc. */
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-24 4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 17:56 ` Richard Henderson
2020-07-24 4:58 ` [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions Lijun Pan
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v5: no change
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
tcg/ppc/tcg-target.h | 2 ++
tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 4fa21f0e71..ff1249ef8e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@ typedef enum {
tcg_isa_2_06,
tcg_isa_2_07,
tcg_isa_3_00,
+ tcg_isa_3_10,
} TCGPowerISA;
extern TCGPowerISA have_isa;
@@ -72,6 +73,7 @@ extern bool have_vsx;
#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
+#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index ee1f9227c1..caa8985b46 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -564,6 +564,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VMULOUH VX4(72)
#define VMULOUW VX4(136) /* v2.07 */
#define VMULUWM VX4(137) /* v2.07 */
+#define VMULLD VX4(457) /* v3.10 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
@@ -3015,6 +3016,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return -1;
case MO_32:
return have_isa_2_07 ? 1 : -1;
+ case MO_64:
+ return have_isa_3_10;
}
return 0;
case INDEX_op_bitsel_vec:
@@ -3149,6 +3152,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+ mul_op[4] = { 0, 0, VMULUWM, VMULLD },
neg_op[4] = { 0, 0, VNEGW, VNEGD },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
@@ -3199,8 +3203,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a1 = 0;
break;
case INDEX_op_mul_vec:
- tcg_debug_assert(vece == MO_32 && have_isa_2_07);
- insn = VMULUWM;
+ insn = mul_op[vece];
break;
case INDEX_op_ssadd_vec:
insn = ssadd_op[vece];
@@ -3709,6 +3712,11 @@ static void tcg_target_init(TCGContext *s)
have_isa = tcg_isa_3_00;
}
#endif
+#ifdef PPC_FEATURE2_ARCH_3_10
+ if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
+ have_isa = tcg_isa_3_10;
+ }
+#endif
#ifdef PPC_FEATURE2_HAS_ISEL
/* Prefer explicit instruction from the kernel. */
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-24 4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-24 4:58 ` [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 17:57 ` Richard Henderson
2020-07-24 4:58 ` [PATCH v5 4/6] target/ppc: add vmulh{su}d instructions Lijun Pan
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4/v5: no change
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 19 +++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 6 ++++++
target/ppc/translate/vmx-ops.inc.c | 4 ++--
4 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 69416b6d7c..3b3013866a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -184,6 +184,8 @@ DEF_HELPER_3(vmulosw, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_3(vmulouw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index bd3e6d7cc7..a3a20821fc 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1086,6 +1086,25 @@ VMUL(uw, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
+void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ r->s32[i] = (int32_t)(((int64_t)a->s32[i] * (int64_t)b->s32[i]) >> 32);
+ }
+}
+
+void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ r->u32[i] = (uint32_t)(((uint64_t)a->u32[i] *
+ (uint64_t)b->u32[i]) >> 32);
+ }
+}
+
void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 8c89738552..50bac375fc 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -811,9 +811,15 @@ GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
+GEN_VXFORM(vmulhuw, 4, 10);
+GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
+ vmulhuw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
GEN_VXFORM(vmulesw, 4, 14);
+GEN_VXFORM(vmulhsw, 4, 14);
+GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
+ vmulhsw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index b49787ac97..29701ad778 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -110,10 +110,10 @@ GEN_VXFORM_207(vmulosw, 4, 6),
GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
-GEN_VXFORM_207(vmuleuw, 4, 10),
+GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
-GEN_VXFORM_207(vmulesw, 4, 14),
+GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 4/6] target/ppc: add vmulh{su}d instructions
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (2 preceding siblings ...)
2020-07-24 4:58 ` [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 4:58 ` [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4/v5: no change
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
v3: simplify helper_vmulh{su}d
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 16 ++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 2 ++
target/ppc/translate/vmx-ops.inc.c | 2 ++
4 files changed, 22 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3b3013866a..0036788919 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -186,6 +186,8 @@ DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_3(vmulouw, void, avr, avr, avr)
DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
+DEF_HELPER_3(vmulhud, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a3a20821fc..57d6767f60 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1105,6 +1105,22 @@ void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
+void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ uint64_t discard;
+
+ muls64(&discard, &r->u64[0], a->s64[0], b->s64[0]);
+ muls64(&discard, &r->u64[1], a->s64[1], b->s64[1]);
+}
+
+void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ uint64_t discard;
+
+ mulu64(&discard, &r->u64[0], a->u64[0], b->u64[0]);
+ mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]);
+}
+
void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 50bac375fc..0910807232 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -812,6 +812,7 @@ GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulhuw, 4, 10);
+GEN_VXFORM(vmulhud, 4, 11);
GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
vmulhuw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM(vmulesb, 4, 12);
@@ -820,6 +821,7 @@ GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vmulhsw, 4, 14);
GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
vmulhsw, PPC_NONE, PPC2_ISA310);
+GEN_VXFORM(vmulhsd, 4, 15);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 29701ad778..f3f4855111 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -111,9 +111,11 @@ GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_310(vmulhud, 4, 11),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_310(vmulhsd, 4, 15),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (3 preceding siblings ...)
2020-07-24 4:58 ` [PATCH v5 4/6] target/ppc: add vmulh{su}d instructions Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 4:58 ` [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions Lijun Pan
2020-07-27 6:33 ` [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
6 siblings, 0 replies; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
vdivsw: Vector Divide Signed Word
vdivuw: Vector Divide Unsigned Word
vdivsd: Vector Divide Signed Doubleword
vdivud: Vector Divide Unsigned Doubleword
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v5: no change
v4: add a comment on undefined result of divide operation.
fix if(){} coding style issue, remove blank line.
v3: add missing divided-by-zero, divided-by-(-1) handling
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 8 ++++++++
target/ppc/int_helper.c | 27 +++++++++++++++++++++++++++
target/ppc/translate.c | 3 +++
target/ppc/translate/vmx-impl.inc.c | 15 +++++++++++++++
target/ppc/translate/vmx-ops.inc.c | 17 +++++++++++++++--
5 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0036788919..70a14029ca 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -188,6 +188,14 @@ DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
DEF_HELPER_3(vmulhud, void, avr, avr, avr)
+DEF_HELPER_3(vdivsw, void, avr, avr, avr)
+DEF_HELPER_3(vdivuw, void, avr, avr, avr)
+DEF_HELPER_3(vdivsd, void, avr, avr, avr)
+DEF_HELPER_3(vdivud, void, avr, avr, avr)
+DEF_HELPER_3(vmodsw, void, avr, avr, avr)
+DEF_HELPER_3(vmoduw, void, avr, avr, avr)
+DEF_HELPER_3(vmodsd, void, avr, avr, avr)
+DEF_HELPER_3(vmodud, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 57d6767f60..62b93b4568 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1121,6 +1121,33 @@ void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]);
}
+#define VDIV_MOD_DO(name, op, element, sign, bit) \
+ void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ if (unlikely((b->element[i] == 0) || \
+ (sign && \
+ (b->element[i] == UINT##bit##_MAX) && \
+ (a->element[i] == INT##bit##_MIN)))) { \
+ /* Undefined, No Special Registers Altered */ \
+ continue; \
+ } \
+ r->element[i] = a->element[i] op b->element[i]; \
+ } \
+ }
+VDIV_MOD_DO(divsw, /, s32, 1, 32)
+VDIV_MOD_DO(divuw, /, u32, 0, 32)
+VDIV_MOD_DO(divsd, /, s64, 1, 64)
+VDIV_MOD_DO(divud, /, u64, 0, 64)
+VDIV_MOD_DO(modsw, %, s32, 1, 32)
+VDIV_MOD_DO(moduw, %, u32, 0, 32)
+VDIV_MOD_DO(modsd, %, s64, 1, 64)
+VDIV_MOD_DO(modud, %, u64, 0, 64)
+#undef VDIV_MOD_DO
+
+
void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 590c3e3bc7..55f0e1a01d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -388,6 +388,9 @@ GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
#define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
+#define GEN_HANDLER_BOTH(name, opc1, opc2, opc3, inval0, inval1, type0, type1) \
+GEN_OPCODE_DUAL(name, opc1, opc2, opc3, inval0, inval1, type0, type1)
+
typedef struct opcode_t {
unsigned char opc1, opc2, opc3, opc4;
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 0910807232..ac5e820541 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -798,6 +798,9 @@ static void trans_vclzd(DisasContext *ctx)
tcg_temp_free_i64(avr);
}
+static void gen_vexptefp(DisasContext *ctx);
+static void gen_vlogefp(DisasContext *ctx);
+
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulouw, 4, 2);
@@ -822,6 +825,18 @@ GEN_VXFORM(vmulhsw, 4, 14);
GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
vmulhsw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM(vmulhsd, 4, 15);
+GEN_VXFORM(vdivuw, 5, 2);
+GEN_VXFORM(vdivud, 5, 3);
+GEN_VXFORM(vdivsw, 5, 6);
+GEN_VXFORM_DUAL_EXT(vexptefp, PPC_ALTIVEC, PPC_NONE, 0x001f0000,
+ vdivsw, PPC_NONE, PPC2_ISA310, 0x00000000);
+GEN_VXFORM(vdivsd, 5, 7);
+GEN_VXFORM_DUAL_EXT(vlogefp, PPC_ALTIVEC, PPC_NONE, 0x001f0000,
+ vdivsd, PPC_NONE, PPC2_ISA310, 0x00000000);
+GEN_VXFORM(vmoduw, 5, 26);
+GEN_VXFORM(vmodud, 5, 27);
+GEN_VXFORM(vmodsw, 5, 30);
+GEN_VXFORM(vmodsd, 5, 31);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index f3f4855111..528458cb25 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -54,6 +54,11 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
+#define GEN_VXFORM_DUAL_BOTH(name0, name1, opc2, opc3, inval0, \
+ inval1, type0, type1) \
+GEN_HANDLER_BOTH(name0##_##name1, 0x4, opc2, opc3, inval0, \
+ inval1, type0, type1)
+
#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
@@ -116,6 +121,16 @@ GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_310(vmulhsd, 4, 15),
+GEN_VXFORM_310(vdivuw, 5, 2),
+GEN_VXFORM_310(vdivud, 5, 3),
+GEN_VXFORM_DUAL_BOTH(vexptefp, vdivsw, 5, 6, 0x001f0000, 0x00000000,
+ PPC_ALTIVEC, PPC2_ISA310),
+GEN_VXFORM_DUAL_BOTH(vlogefp, vdivsd, 5, 7, 0x001f0000, 0x00000000,
+ PPC_ALTIVEC, PPC2_ISA310),
+GEN_VXFORM_310(vmoduw, 5, 26),
+GEN_VXFORM_310(vmodud, 5, 27),
+GEN_VXFORM_310(vmodsw, 5, 30),
+GEN_VXFORM_310(vmodsd, 5, 31),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
@@ -259,8 +274,6 @@ GEN_VXFORM_NOA(vupkhpx, 7, 13),
GEN_VXFORM_NOA(vupklpx, 7, 15),
GEN_VXFORM_NOA(vrefp, 5, 4),
GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
-GEN_VXFORM_NOA(vexptefp, 5, 6),
-GEN_VXFORM_NOA(vlogefp, 5, 7),
GEN_VXFORM_NOA(vrfim, 5, 11),
GEN_VXFORM_NOA(vrfin, 5, 8),
GEN_VXFORM_NOA(vrfip, 5, 10),
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (4 preceding siblings ...)
2020-07-24 4:58 ` [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
@ 2020-07-24 4:58 ` Lijun Pan
2020-07-24 18:00 ` Richard Henderson
2020-07-27 6:33 ` [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
6 siblings, 1 reply; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 4:58 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, richard.henderson, david; +Cc: Lijun Pan
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
VA-form.
vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
Doubleword VA-form.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v5: update instruction flag for vmsumcud.
integrate into this isa3.1 patch series
v3: implement vmsumudm/vmsumcud through int128 functions,
suggested by Richard Henderson.
disas/ppc.c | 2 ++
target/ppc/helper.h | 4 ++-
target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++-
target/ppc/translate.c | 1 -
target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++-----------
target/ppc/translate/vmx-ops.inc.c | 2 ++
6 files changed, 76 insertions(+), 21 deletions(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index 63e97cfe1d..bd76fae4c4 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
+{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 70a14029ca..00a31d64bc 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -274,10 +274,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr)
DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr)
+DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
-DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
+DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr)
+DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr)
DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
DEF_HELPER_3(lvebx, void, env, avr, tl)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 62b93b4568..2e919a7b8e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -913,7 +913,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
}
-void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
+ ppc_avr_t *b, ppc_avr_t *c)
{
int i;
@@ -1051,6 +1052,52 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
}
+void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r,
+ ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ Int128 sum;
+ uint64_t lo, hi;
+
+ sum = int128_make128(c->VsrD(1), c->VsrD(0));
+
+ mulu64(&lo, &hi, a->VsrD(0), b->VsrD(0));
+ sum = int128_add(sum, int128_make128(lo, hi));
+
+ mulu64(&lo, &hi, a->VsrD(1), b->VsrD(1));
+ sum = int128_add(sum, int128_make128(lo, hi));
+
+ r->VsrD(0) = int128_gethi(sum);
+ r->VsrD(1) = int128_getlo(sum);
+}
+
+void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r,
+ ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ Int128 sum;
+ uint64_t p1lo, p1hi, p2lo, p2hi;
+
+ mulu64(&p1lo, &p1hi, a->VsrD(0), b->VsrD(0));
+ mulu64(&p2lo, &p2hi, a->VsrD(1), b->VsrD(1));
+
+ /* Sum lowest 64-bit elements. */
+ sum = int128_make128(c->VsrD(1), 0);
+ sum = int128_add(sum, int128_make128(p1lo, 0));
+ sum = int128_add(sum, int128_make128(p2lo, 0));
+
+ /*
+ * Discard low 64-bits, leaving the carry into bit 64.
+ * Then sum the higher 64-bit elements.
+ */
+ sum = int128_rshift(sum, 64);
+ sum = int128_add(sum, int128_make128(c->VsrD(0), 0));
+ sum = int128_add(sum, int128_make128(p1hi, 0));
+ sum = int128_add(sum, int128_make128(p2hi, 0));
+
+ /* The result is only the carry into bits 64 & 65. */
+ r->VsrD(1) = int128_gethi(sum);
+ r->VsrD(0) = 0;
+}
+
#define VMUL_DO_EVN(name, mul_element, mul_access, prod_access, cast) \
void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 55f0e1a01d..b33b2d87a4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7324,7 +7324,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
-GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
PPC2_ISA300),
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index ac5e820541..5b85b6ea06 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1272,6 +1272,25 @@ static void gen_vsldoi(DisasContext *ctx)
tcg_temp_free_i32(sh);
}
+#define GEN_VAFORM(name, opc2) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr ra, rb, rc, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rc = gen_avr_ptr(rC(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name(cpu_env, rd, ra, rb, rc); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rc); \
+ tcg_temp_free_ptr(rd); \
+}
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
@@ -1296,24 +1315,8 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
}
GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
-
-static void gen_vmladduhm(DisasContext *ctx)
-{
- TCGv_ptr ra, rb, rc, rd;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rb = gen_avr_ptr(rB(ctx->opcode));
- rc = gen_avr_ptr(rC(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_vmladduhm(rd, ra, rb, rc);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rb);
- tcg_temp_free_ptr(rc);
- tcg_temp_free_ptr(rd);
-}
+GEN_VAFORM(vmsumcud, 11)
+GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17)
static void gen_vpermr(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 528458cb25..fd689a5086 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -295,6 +295,8 @@ GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
+GEN_HANDLER(vmsumcud, 0x4, 11, 0xFF, 0x00000000, PPC2_ISA310),
+GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17),
GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition
2020-07-24 4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
@ 2020-07-24 17:54 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2020-07-24 17:54 UTC (permalink / raw)
To: Lijun Pan, qemu-ppc, qemu-devel, david
On 7/23/20 9:58 PM, Lijun Pan wrote:
> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
We should add the rest of the bits as well at some point.
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case
2020-07-24 4:58 ` [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
@ 2020-07-24 17:56 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2020-07-24 17:56 UTC (permalink / raw)
To: Lijun Pan, qemu-ppc, qemu-devel, david
On 7/23/20 9:58 PM, Lijun Pan wrote:
> Group vmuluwm and vmulld. Make vmulld-specific
> changes since it belongs to new ISA 3.1.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v5: no change
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_mul()
> v2: fix coding style
> use Power ISA 3.1 flag
>
> tcg/ppc/tcg-target.h | 2 ++
> tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions
2020-07-24 4:58 ` [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions Lijun Pan
@ 2020-07-24 17:57 ` Richard Henderson
2020-07-27 6:32 ` David Gibson
0 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2020-07-24 17:57 UTC (permalink / raw)
To: Lijun Pan, qemu-ppc, qemu-devel, david
On 7/23/20 9:58 PM, Lijun Pan wrote:
> vmulhsw: Vector Multiply High Signed Word
> vmulhuw: Vector Multiply High Unsigned Word
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v4/v5: no change
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> v3: inline the helper_vmulh{su}w multiply directly instead of using macro
> v2: fix coding style
> use Power ISA 3.1 flag
The Reviewed-by tag goes above the "---" marker so that it is included when the
patch is applied.
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions
2020-07-24 4:58 ` [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions Lijun Pan
@ 2020-07-24 18:00 ` Richard Henderson
2020-07-24 18:46 ` Lijun Pan
0 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2020-07-24 18:00 UTC (permalink / raw)
To: Lijun Pan, qemu-ppc, qemu-devel, david
On 7/23/20 9:58 PM, Lijun Pan wrote:
> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
> VA-form.
> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
> Doubleword VA-form.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v5: update instruction flag for vmsumcud.
> integrate into this isa3.1 patch series
> v3: implement vmsumudm/vmsumcud through int128 functions,
> suggested by Richard Henderson.
>
> disas/ppc.c | 2 ++
> target/ppc/helper.h | 4 ++-
> target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++-
> target/ppc/translate.c | 1 -
> target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++-----------
> target/ppc/translate/vmx-ops.inc.c | 2 ++
> 6 files changed, 76 insertions(+), 21 deletions(-)
>
> diff --git a/disas/ppc.c b/disas/ppc.c
> index 63e97cfe1d..bd76fae4c4 100644
> --- a/disas/ppc.c
> +++ b/disas/ppc.c
> @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
> { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
> { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
> { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 70a14029ca..00a31d64bc 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -274,10 +274,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr)
> DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr)
> +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
> -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
> +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr)
> +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr)
> DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
> DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
> DEF_HELPER_3(lvebx, void, env, avr, tl)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 62b93b4568..2e919a7b8e 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -913,7 +913,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
> }
> }
>
> -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
> + ppc_avr_t *b, ppc_avr_t *c)
Why?
> +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r,
> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
...
> +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r,
> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
You don't actually use env in either helper, so you shouldn't pass it in.
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions
2020-07-24 18:00 ` Richard Henderson
@ 2020-07-24 18:46 ` Lijun Pan
2020-07-24 23:07 ` Lijun Pan
0 siblings, 1 reply; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 18:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-ppc, Lijun Pan, qemu-devel, David Gibson
[-- Attachment #1: Type: text/plain, Size: 4299 bytes --]
> On Jul 24, 2020, at 1:00 PM, Richard Henderson <richard.henderson@linaro.org> wrote:
>
> On 7/23/20 9:58 PM, Lijun Pan wrote:
>> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
>> VA-form.
>> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
>> Doubleword VA-form.
>>
>> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
>> ---
>> v5: update instruction flag for vmsumcud.
>> integrate into this isa3.1 patch series
>> v3: implement vmsumudm/vmsumcud through int128 functions,
>> suggested by Richard Henderson.
>>
>> disas/ppc.c | 2 ++
>> target/ppc/helper.h | 4 ++-
>> target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++-
>> target/ppc/translate.c | 1 -
>> target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++-----------
>> target/ppc/translate/vmx-ops.inc.c | 2 ++
>> 6 files changed, 76 insertions(+), 21 deletions(-)
>>
>> diff --git a/disas/ppc.c b/disas/ppc.c
>> index 63e97cfe1d..bd76fae4c4 100644
>> --- a/disas/ppc.c
>> +++ b/disas/ppc.c
>> @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>> { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
>> { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
>> { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
>> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
>> index 70a14029ca..00a31d64bc 100644
>> --- a/target/ppc/helper.h
>> +++ b/target/ppc/helper.h
>> @@ -274,10 +274,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr)
>> DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr)
>> DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr)
>> DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr)
>> +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr)
>> DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
>> DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
>> DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
>> -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
>> +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr)
>> +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr)
>> DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
>> DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
>> DEF_HELPER_3(lvebx, void, env, avr, tl)
>> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
>> index 62b93b4568..2e919a7b8e 100644
>> --- a/target/ppc/int_helper.c
>> +++ b/target/ppc/int_helper.c
>> @@ -913,7 +913,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
>> }
>> }
>>
>> -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>> +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
>> + ppc_avr_t *b, ppc_avr_t *c)
>
> Why?
>
>> +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r,
>> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>> +{
>
> ...
>
>> +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r,
>> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>
> You don't actually use env in either helper, so you shouldn't pass it in.
>
>
I just wanted to reuse GEN_VAFORM_PAIRED which has env passed in,
rather than creating a GEN_VAFORM_PAIRED_NOENV which does not have env.
I created GEN_VAFORM which includes env so that it can cover both env and non-env case.
I re-look at the code, and find out that GEN_**FORM** differentiate in env and non-env.
So I can rename current GEN_VAFORM_PAIRED (env passed in) to GEN_VAFORM_PAIRED_ENV,
create a new GEN_VAFORM_PAIRED (no env) to cater vmladduhm and vmsumudm
remove the env part code in GEN_VAFORM to have vmsumcud fit into.
What do you think, Richard?
Lijun
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions
2020-07-24 18:46 ` Lijun Pan
@ 2020-07-24 23:07 ` Lijun Pan
0 siblings, 0 replies; 15+ messages in thread
From: Lijun Pan @ 2020-07-24 23:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-ppc, Lijun Pan, qemu-devel, David Gibson
[-- Attachment #1: Type: text/plain, Size: 4963 bytes --]
> On Jul 24, 2020, at 1:46 PM, Lijun Pan <ljp@linux.vnet.ibm.com> wrote:
>
>
>
>> On Jul 24, 2020, at 1:00 PM, Richard Henderson <richard.henderson@linaro.org <mailto:richard.henderson@linaro.org>> wrote:
>>
>> On 7/23/20 9:58 PM, Lijun Pan wrote:
>>> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
>>> VA-form.
>>> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
>>> Doubleword VA-form.
>>>
>>> Signed-off-by: Lijun Pan <ljp@linux.ibm.com <mailto:ljp@linux.ibm.com>>
>>> ---
>>> v5: update instruction flag for vmsumcud.
>>> integrate into this isa3.1 patch series
>>> v3: implement vmsumudm/vmsumcud through int128 functions,
>>> suggested by Richard Henderson.
>>>
>>> disas/ppc.c | 2 ++
>>> target/ppc/helper.h | 4 ++-
>>> target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++-
>>> target/ppc/translate.c | 1 -
>>> target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++-----------
>>> target/ppc/translate/vmx-ops.inc.c | 2 ++
>>> 6 files changed, 76 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/disas/ppc.c b/disas/ppc.c
>>> index 63e97cfe1d..bd76fae4c4 100644
>>> --- a/disas/ppc.c
>>> +++ b/disas/ppc.c
>>> @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>>> { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
>>> { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
>>> { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
>>> { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
>>> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
>>> index 70a14029ca..00a31d64bc 100644
>>> --- a/target/ppc/helper.h
>>> +++ b/target/ppc/helper.h
>>> @@ -274,10 +274,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr)
>>> DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr)
>>> +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
>>> -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
>>> +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr)
>>> +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr)
>>> DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
>>> DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
>>> DEF_HELPER_3(lvebx, void, env, avr, tl)
>>> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
>>> index 62b93b4568..2e919a7b8e 100644
>>> --- a/target/ppc/int_helper.c
>>> +++ b/target/ppc/int_helper.c
>>> @@ -913,7 +913,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
>>> }
>>> }
>>>
>>> -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>>> +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
>>> + ppc_avr_t *b, ppc_avr_t *c)
>>
>> Why?
>>
>>> +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r,
>>> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>>> +{
>>
>> ...
>>
>>> +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r,
>>> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>>
>> You don't actually use env in either helper, so you shouldn't pass it in.
>>
>>
>
> I just wanted to reuse GEN_VAFORM_PAIRED which has env passed in,
> rather than creating a GEN_VAFORM_PAIRED_NOENV which does not have env.
> I created GEN_VAFORM which includes env so that it can cover both env and non-env case.
>
> I re-look at the code, and find out that GEN_**FORM** differentiate in env and non-env.
> So I can rename current GEN_VAFORM_PAIRED (env passed in) to GEN_VAFORM_PAIRED_ENV,
> create a new GEN_VAFORM_PAIRED (no env) to cater vmladduhm and vmsumudm
> remove the env part code in GEN_VAFORM to have vmsumcud fit into.
>
I take back what I said in the second paragraph.
I think we need to keep GEN_VAFORM_PAIRED having env to cover both env and non-env cases
because some pair has both non-env, some pair has both env, some pair has env and non-env.
e.g. GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) vmsumuhm non-env, vmsumuhs env.
It is the same for GEN_VAFORM. though for now, no instructions uses env, adding env to
GEN_VAFORM saves for later changes.
Lijun
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions
2020-07-24 17:57 ` Richard Henderson
@ 2020-07-27 6:32 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2020-07-27 6:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-ppc, Lijun Pan, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 848 bytes --]
On Fri, Jul 24, 2020 at 10:57:51AM -0700, Richard Henderson wrote:
> On 7/23/20 9:58 PM, Lijun Pan wrote:
> > vmulhsw: Vector Multiply High Signed Word
> > vmulhuw: Vector Multiply High Unsigned Word
> >
> > Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> > ---
> > v4/v5: no change
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > v3: inline the helper_vmulh{su}w multiply directly instead of using macro
> > v2: fix coding style
> > use Power ISA 3.1 flag
>
> The Reviewed-by tag goes above the "---" marker so that it is included when the
> patch is applied.
Right, but I've fixed it up on this occasion.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (5 preceding siblings ...)
2020-07-24 4:58 ` [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions Lijun Pan
@ 2020-07-27 6:33 ` David Gibson
6 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2020-07-27 6:33 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1742 bytes --]
On Thu, Jul 23, 2020 at 11:58:39PM -0500, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
> this version. In v4 version, coding style issues are fixed, community
> reviews/suggestions are taken into consideration. 1/11 - 5/11 of v4 were
> accepted by David Gibson, and 9/11 of v4 was accepted by Lauren Vivier.
> This v5 version updates PPC_FEATURE2_ARCH_3_10 definition in 6/11 of v4,
> rebases 7/11 8/11 10/11 11/11 of v4, and integrates vmsumudm/vmsumcud
> patch.
I've applied 1..4 to ppx-for-5.2. Still looking for a review from
Richard on the last two.
>
> Lijun Pan (6):
> Update PowerPC AT_HWCAP2 definition
> target/ppc: add vmulld to INDEX_op_mul_vec case
> target/ppc: add vmulh{su}w instructions
> target/ppc: add vmulh{su}d instructions
> target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
> target/ppc: add vmsumudm vmsumcud instructions
>
> disas/ppc.c | 2 +
> include/elf.h | 1 +
> target/ppc/helper.h | 16 +++-
> target/ppc/int_helper.c | 111 +++++++++++++++++++++++++++-
> target/ppc/translate.c | 4 +-
> target/ppc/translate/vmx-impl.inc.c | 62 +++++++++++-----
> target/ppc/translate/vmx-ops.inc.c | 25 ++++++-
> tcg/ppc/tcg-target.h | 2 +
> tcg/ppc/tcg-target.inc.c | 12 ++-
> 9 files changed, 208 insertions(+), 27 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 15+ messages in thread
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Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-24 4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-24 4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-24 17:54 ` Richard Henderson
2020-07-24 4:58 ` [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
2020-07-24 17:56 ` Richard Henderson
2020-07-24 4:58 ` [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-07-24 17:57 ` Richard Henderson
2020-07-27 6:32 ` David Gibson
2020-07-24 4:58 ` [PATCH v5 4/6] target/ppc: add vmulh{su}d instructions Lijun Pan
2020-07-24 4:58 ` [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-07-24 4:58 ` [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions Lijun Pan
2020-07-24 18:00 ` Richard Henderson
2020-07-24 18:46 ` Lijun Pan
2020-07-24 23:07 ` Lijun Pan
2020-07-27 6:33 ` [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
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