* [PATCH 1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
@ 2020-08-11 6:07 LIU Zhiwei
2020-08-13 20:56 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: LIU Zhiwei @ 2020-08-11 6:07 UTC (permalink / raw)
To: qemu-devel, qemu-arm; +Cc: peter.maydell, richard.henderson, LIU Zhiwei
From DDI0487Fc_armv8_arm.pdf, the CPTR_EL2 has two kinds
of layouts according to HCR_EL2.E2H.
When HCR_EL2.E2H is 1, fp_exception_el should refer to
HCR_EL2.FPEN and sve_exception_el should refer to HCR_EL2.ZEN.
Change-Id: If1c8f88db9fb505c36211ceafbf25e838ed96ec0
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 45 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8ef0fb478f..19b74b25e4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6116,11 +6116,29 @@ int sve_exception_el(CPUARMState *env, int el)
* they will be zero when EL2 is not present.
*/
if (el <= 2 && !arm_is_secure_below_el3(env)) {
- if (env->cp15.cptr_el[2] & CPTR_TZ) {
- return 2;
- }
- if (env->cp15.cptr_el[2] & CPTR_TFP) {
- return 0;
+ if ((arm_hcr_el2_eff(env) & HCR_E2H) == HCR_E2H) {
+ int zen = extract32(env->cp15.cptr_el[2], 16, 2);
+ switch (zen) {
+ case 0:
+ case 2:
+ return 2;
+ case 1:
+ if ((arm_hcr_el2_eff(env) & HCR_TGE) == HCR_TGE) {
+ if (el == 0) {
+ return 2;
+ }
+ }
+ break;
+ case 3:
+ break;
+ }
+ } else {
+ if (env->cp15.cptr_el[2] & CPTR_TZ) {
+ return 2;
+ }
+ if (env->cp15.cptr_el[2] & CPTR_TFP) {
+ return 0;
+ }
}
}
@@ -12492,10 +12510,29 @@ int fp_exception_el(CPUARMState *env, int cur_el)
*/
/* CPTR_EL2 : present in v7VE or v8 */
- if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
- && !arm_is_secure_below_el3(env)) {
+ if ((cur_el <= 2) && !arm_is_secure_below_el3(env)) {
/* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
- return 2;
+ if ((arm_hcr_el2_eff(env) & HCR_E2H) == HCR_E2H) {
+ int fpen = extract32(env->cp15.cptr_el[2], 20, 2);
+ switch (fpen) {
+ case 0:
+ case 2:
+ return 2;
+ case 1:
+ if ((arm_hcr_el2_eff(env) & HCR_TGE) == HCR_TGE) {
+ if (cur_el == 0) {
+ return 2;
+ }
+ }
+ break;
+ case 3:
+ break;
+ }
+ } else {
+ if (extract32(env->cp15.cptr_el[2], 10, 1)) {
+ return 2;
+ }
+ }
}
/* CPTR_EL3 : present in v8 */
--
2.23.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
2020-08-11 6:07 [PATCH 1/1] target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H LIU Zhiwei
@ 2020-08-13 20:56 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2020-08-13 20:56 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-arm; +Cc: peter.maydell
On 8/10/20 11:07 PM, LIU Zhiwei wrote:
> if (el <= 2 && !arm_is_secure_below_el3(env)) {
> - if (env->cp15.cptr_el[2] & CPTR_TZ) {
> - return 2;
> - }
> - if (env->cp15.cptr_el[2] & CPTR_TFP) {
> - return 0;
> + if ((arm_hcr_el2_eff(env) & HCR_E2H) == HCR_E2H) {
> + int zen = extract32(env->cp15.cptr_el[2], 16, 2);
> + switch (zen) {
> + case 0:
> + case 2:
> + return 2;
> + case 1:
> + if ((arm_hcr_el2_eff(env) & HCR_TGE) == HCR_TGE) {
Since the outer if checks that we're in non-secure state, and (by nature of
sve) we know we're in aarch64 mode, then we don't need to use arm_hcr_el2_eff
and can just use env->cp15.hcr_el2.
Add a comment
> /* Since we exclude secure first, we may read HCR_EL2 directly. */
like we do in vae1_tlbmask.
You do not need to write
if ((x & bit) == bit)
just use
if (x & bit)
here.
With those changes,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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