* [PATCH 1/2] hw/virtio-pci Added counter for pcie capabilities offsets.
@ 2020-08-13 7:19 andrew
2020-08-13 7:19 ` [PATCH 2/2] hw/virtio-pci Added AER capability andrew
0 siblings, 1 reply; 4+ messages in thread
From: andrew @ 2020-08-13 7:19 UTC (permalink / raw)
To: qemu-devel; +Cc: mst
From: Andrew <andrew@daynix.com>
Removed hardcoded offset for ats. Added cap offset counter
for future capabilities like AER.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index ccdf54e81c..8e02709605 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1787,6 +1787,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
if (pcie_port && pci_is_express(pci_dev)) {
int pos;
+ uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
pos = pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
@@ -1822,7 +1823,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
}
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, 256);
+ pcie_ats_init(pci_dev, last_pcie_cap_offset);
+ last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
}
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] hw/virtio-pci Added AER capability.
2020-08-13 7:19 [PATCH 1/2] hw/virtio-pci Added counter for pcie capabilities offsets andrew
@ 2020-08-13 7:19 ` andrew
2020-08-31 9:29 ` Yan Vugenfirer
2020-09-08 14:19 ` Michael S. Tsirkin
0 siblings, 2 replies; 4+ messages in thread
From: andrew @ 2020-08-13 7:19 UTC (permalink / raw)
To: qemu-devel; +Cc: mst
From: Andrew <andrew@daynix.com>
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1857668
Added AER capability for virtio-pci devices.
Also added property for devices, by default AER is enabled.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 16 ++++++++++++++++
hw/virtio/virtio-pci.h | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 8e02709605..646dfb8a0d 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1806,6 +1806,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
*/
pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
+ pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
+ PCI_ERR_SIZEOF, NULL);
+ last_pcie_cap_offset += PCI_ERR_SIZEOF;
+ }
+
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
/* Init error enabling flags */
pcie_cap_deverr_init(pci_dev);
@@ -1847,7 +1853,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
static void virtio_pci_exit(PCIDevice *pci_dev)
{
+ VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
+ bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
+ !pci_bus_is_root(pci_get_bus(pci_dev));
+
msix_uninit_exclusive_bar(pci_dev);
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
+ pci_is_express(pci_dev)) {
+ pcie_aer_exit(pci_dev);
+ }
}
static void virtio_pci_reset(DeviceState *qdev)
@@ -1900,6 +1914,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
+ DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_AER_BIT, true),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index e2eaaa9182..4b2491ff15 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -45,6 +45,7 @@ enum {
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
VIRTIO_PCI_FLAG_INIT_PM_BIT,
VIRTIO_PCI_FLAG_INIT_FLR_BIT,
+ VIRTIO_PCI_FLAG_AER_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -84,6 +85,9 @@ enum {
/* Init Function Level Reset capability */
#define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
+/* Advanced Error Reporting capability */
+#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] hw/virtio-pci Added AER capability.
2020-08-13 7:19 ` [PATCH 2/2] hw/virtio-pci Added AER capability andrew
@ 2020-08-31 9:29 ` Yan Vugenfirer
2020-09-08 14:19 ` Michael S. Tsirkin
1 sibling, 0 replies; 4+ messages in thread
From: Yan Vugenfirer @ 2020-08-31 9:29 UTC (permalink / raw)
To: Andrew Melnichenko; +Cc: qemu-devel, mst
Ping.
> On 13 Aug 2020, at 10:19 AM, andrew@daynix.com wrote:
>
> From: Andrew <andrew@daynix.com>
>
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1857668
> Added AER capability for virtio-pci devices.
> Also added property for devices, by default AER is enabled.
>
> Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
> ---
> hw/virtio/virtio-pci.c | 16 ++++++++++++++++
> hw/virtio/virtio-pci.h | 4 ++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index 8e02709605..646dfb8a0d 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -1806,6 +1806,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
> */
> pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
>
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
> + pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
> + PCI_ERR_SIZEOF, NULL);
> + last_pcie_cap_offset += PCI_ERR_SIZEOF;
> + }
> +
> if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
> /* Init error enabling flags */
> pcie_cap_deverr_init(pci_dev);
> @@ -1847,7 +1853,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>
> static void virtio_pci_exit(PCIDevice *pci_dev)
> {
> + VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
> + bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
> + !pci_bus_is_root(pci_get_bus(pci_dev));
> +
> msix_uninit_exclusive_bar(pci_dev);
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
> + pci_is_express(pci_dev)) {
> + pcie_aer_exit(pci_dev);
> + }
> }
>
> static void virtio_pci_reset(DeviceState *qdev)
> @@ -1900,6 +1914,8 @@ static Property virtio_pci_properties[] = {
> VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
> DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
> + DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
> + VIRTIO_PCI_FLAG_AER_BIT, true),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
> index e2eaaa9182..4b2491ff15 100644
> --- a/hw/virtio/virtio-pci.h
> +++ b/hw/virtio/virtio-pci.h
> @@ -45,6 +45,7 @@ enum {
> VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
> VIRTIO_PCI_FLAG_INIT_PM_BIT,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT,
> + VIRTIO_PCI_FLAG_AER_BIT,
> };
>
> /* Need to activate work-arounds for buggy guests at vmstate load. */
> @@ -84,6 +85,9 @@ enum {
> /* Init Function Level Reset capability */
> #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>
> +/* Advanced Error Reporting capability */
> +#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
> +
> typedef struct {
> MSIMessage msg;
> int virq;
> --
> 2.27.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] hw/virtio-pci Added AER capability.
2020-08-13 7:19 ` [PATCH 2/2] hw/virtio-pci Added AER capability andrew
2020-08-31 9:29 ` Yan Vugenfirer
@ 2020-09-08 14:19 ` Michael S. Tsirkin
1 sibling, 0 replies; 4+ messages in thread
From: Michael S. Tsirkin @ 2020-09-08 14:19 UTC (permalink / raw)
To: andrew; +Cc: qemu-devel
On Thu, Aug 13, 2020 at 10:19:31AM +0300, andrew@daynix.com wrote:
> From: Andrew <andrew@daynix.com>
>
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1857668
> Added AER capability for virtio-pci devices.
> Also added property for devices, by default AER is enabled.
>
> Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Well AER is pci express only. I suspect you need to limit
this to express, fail on pci.
> ---
> hw/virtio/virtio-pci.c | 16 ++++++++++++++++
> hw/virtio/virtio-pci.h | 4 ++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index 8e02709605..646dfb8a0d 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -1806,6 +1806,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
> */
> pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
>
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
> + pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
> + PCI_ERR_SIZEOF, NULL);
> + last_pcie_cap_offset += PCI_ERR_SIZEOF;
> + }
> +
> if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
> /* Init error enabling flags */
> pcie_cap_deverr_init(pci_dev);
> @@ -1847,7 +1853,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>
> static void virtio_pci_exit(PCIDevice *pci_dev)
> {
> + VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
> + bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
> + !pci_bus_is_root(pci_get_bus(pci_dev));
> +
> msix_uninit_exclusive_bar(pci_dev);
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
> + pci_is_express(pci_dev)) {
> + pcie_aer_exit(pci_dev);
> + }
> }
>
> static void virtio_pci_reset(DeviceState *qdev)
> @@ -1900,6 +1914,8 @@ static Property virtio_pci_properties[] = {
> VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
> DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
> + DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
> + VIRTIO_PCI_FLAG_AER_BIT, true),
> DEFINE_PROP_END_OF_LIST(),
> };
>
This will break cross version migration. Please disable this for
old machine types.
I am also unsure why it's on by default generally.
It is optional in express spec.
> diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
> index e2eaaa9182..4b2491ff15 100644
> --- a/hw/virtio/virtio-pci.h
> +++ b/hw/virtio/virtio-pci.h
> @@ -45,6 +45,7 @@ enum {
> VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
> VIRTIO_PCI_FLAG_INIT_PM_BIT,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT,
> + VIRTIO_PCI_FLAG_AER_BIT,
> };
>
> /* Need to activate work-arounds for buggy guests at vmstate load. */
> @@ -84,6 +85,9 @@ enum {
> /* Init Function Level Reset capability */
> #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>
> +/* Advanced Error Reporting capability */
> +#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
> +
> typedef struct {
> MSIMessage msg;
> int virq;
> --
> 2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-09-08 14:20 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-13 7:19 [PATCH 1/2] hw/virtio-pci Added counter for pcie capabilities offsets andrew
2020-08-13 7:19 ` [PATCH 2/2] hw/virtio-pci Added AER capability andrew
2020-08-31 9:29 ` Yan Vugenfirer
2020-09-08 14:19 ` Michael S. Tsirkin
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).