From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, alistair.francis@wdc.com
Subject: [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions
Date: Tue, 25 Aug 2020 11:48:25 -0700 [thread overview]
Message-ID: <20200825184836.1282371-8-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/helper.h | 3 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 11 +
target/riscv/op_helper.c | 114 ++++++++
target/riscv/insn_trans/trans_rvh.c.inc | 340 ++++++++++++++++++++++++
6 files changed, 474 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ba0a5b50ff..7abae4267f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -443,6 +443,7 @@
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HU 0x00000200
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..c8029d83f9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,9 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
+DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
#endif
/* Vector functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 86153d93fa..8157dee8b7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -81,3 +81,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32H Base Instruction Set ***
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563067..84080dd18c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,6 +78,7 @@
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -223,6 +224,16 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
# *** RV32H Base Instruction Set ***
+hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
+hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
+hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
+hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
+hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
+hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
+hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
+hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
+hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
+hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7cccd42a1e..3d306c343c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ pte = cpu_ldsb_data_ra(env, address, GETPC());
+ break;
+ case MO_UB:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TESW:
+ pte = cpu_ldsw_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ case MO_TESL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEQ:
+ pte = cpu_ldq_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
+void helper_hyp_store(CPURISCVState *env, target_ulong address,
+ target_ulong val, target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ case MO_UB:
+ cpu_stb_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESW:
+ case MO_TEUW:
+ cpu_stw_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESL:
+ case MO_TEUL:
+ cpu_stl_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TEQ:
+ cpu_stq_data_ra(env, address, val, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
+target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_TEUL:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 263b652d90..db650ae62a 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -16,6 +16,346 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_UB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+#endif
+
+static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
--
2.28.0
next prev parent reply other threads:[~2020-08-25 19:03 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 18:48 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-08-25 18:48 ` [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT Alistair Francis
2020-08-25 18:48 ` [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC Alistair Francis
2020-08-25 18:48 ` [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines Alistair Francis
2020-08-25 18:48 ` [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets Alistair Francis
2020-08-25 18:48 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-08-09 9:46 ` Peter Maydell
2021-08-12 14:57 ` Peter Maydell
2020-08-25 18:48 ` [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-08-25 18:48 ` Alistair Francis [this message]
2020-08-25 18:48 ` [PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions Alistair Francis
2020-08-25 18:48 ` [PULL 09/18] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-08-25 18:48 ` [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-08-25 18:48 ` [PULL 11/18] target/riscv: Fix the interrupt cause code Alistair Francis
2020-08-25 18:48 ` [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-08-25 18:48 ` [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-08-25 18:48 ` [PULL 14/18] target/riscv: Only support a single VSXL length Alistair Francis
2020-08-25 18:48 ` [PULL 15/18] target/riscv: Only support little endian guests Alistair Francis
2020-08-25 18:48 ` [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-08-25 18:48 ` [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-08-25 18:48 ` [PULL 18/18] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-08-25 21:24 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-08-25 21:21 ` Alistair Francis
2020-08-25 21:49 ` Peter Maydell
2020-08-25 22:30 ` Alistair Francis
2020-08-26 3:21 ` Bin Meng
2020-08-26 9:25 ` Peter Maydell
2020-08-26 10:06 ` Bin Meng
2020-08-27 15:44 ` Alistair Francis
2020-08-29 15:49 ` LIU Zhiwei
2020-08-29 17:30 ` Alistair Francis
2020-08-26 9:28 ` Peter Maydell
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