From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/18] riscv-to-apply queue
Date: Thu, 27 Aug 2020 08:44:37 -0700 [thread overview]
Message-ID: <CAKmqyKPtrKfcdmEt6NSLa4ZqmjqVUHL_DHzLLZPUoB-xDek6Pw@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmWv52oeQb6z3JTpa16utD2NmB1sKZ-sT7uD1R8_3KwNMw@mail.gmail.com>
On Wed, Aug 26, 2020 at 3:06 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Peter,
>
> On Wed, Aug 26, 2020 at 5:25 PM Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > On Wed, 26 Aug 2020 at 04:21, Bin Meng <bmeng.cn@gmail.com> wrote:
> > > On Wed, Aug 26, 2020 at 6:41 AM Alistair Francis <alistair23@gmail.com> wrote:
> > > > Richard and Philippe review patches and some of the RISC-V patches get
> > > > reviewed by the RISC-V community. The main problem (which is a common
> > > > problem in open source) is that large technical patch series just get
> > > > ignored.
> > >
> > > Yep, I am only comfortable reviewing patches which I have confidence
> > > in. Right now I am not working on any H- or V - extension for RISC-V
> > > so I cannot contribute to any review of these large numbers of H- or
> > > V- extension related patches. Sorry!
> >
> > So, everybody has a ton of work they need to do and only a limited
> > amount of time they might have for code review, so it's important to
> > prioritise. But I would encourage you, and other people contributing
> > to RISC-V parts of QEMU, to at least sometimes review changes that are
> > a little bit out of your "comfort zone" if nobody else seems to be
> > doing so. Review can find bugs, areas that are confusing or need
> > comments, etc, even without a thorough knowledge of the relevant spec.
> > (In fact, not knowing the spec can help in identifying where
> > explanatory comments can help the reader!) And for the project it means
> > we have more people who at least have some idea of what that bit of code
> > is doing. Review that is limited to "this code seems to make sense but
> > I haven't checked it against the spec" is better than patches getting
> > no review at all, I think. And it's a good way to build your knowledge
> > of the codebase and the architecture over time.
>
> Agree. I really wanted to spend more time on this project but like you
> said it's priorities.
>
> One thing I do not understand is that according to MAINTAINTERS there
> are 4 custodians for the RISC-V maintenance work but it looks to me so
> far only Alistair is actively reviewing patches. I know Palmer used to
> review patches but if it's only one person that might be some issues.
> At least MAINTAINTERS can cross-review, and we have 4 there.
Yeah, most of the people in the RISC-V MAINTAINERS file are inactive.
Besides Palmer and myself I haven't seen an email from anyone.
Alistair
>
> Regards,
> Bin
next prev parent reply other threads:[~2020-08-27 15:56 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 18:48 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-08-25 18:48 ` [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT Alistair Francis
2020-08-25 18:48 ` [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC Alistair Francis
2020-08-25 18:48 ` [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines Alistair Francis
2020-08-25 18:48 ` [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets Alistair Francis
2020-08-25 18:48 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-08-09 9:46 ` Peter Maydell
2021-08-12 14:57 ` Peter Maydell
2020-08-25 18:48 ` [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-08-25 18:48 ` [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-08-25 18:48 ` [PULL 08/18] target/riscv: Do two-stage lookups on " Alistair Francis
2020-08-25 18:48 ` [PULL 09/18] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-08-25 18:48 ` [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-08-25 18:48 ` [PULL 11/18] target/riscv: Fix the interrupt cause code Alistair Francis
2020-08-25 18:48 ` [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-08-25 18:48 ` [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-08-25 18:48 ` [PULL 14/18] target/riscv: Only support a single VSXL length Alistair Francis
2020-08-25 18:48 ` [PULL 15/18] target/riscv: Only support little endian guests Alistair Francis
2020-08-25 18:48 ` [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-08-25 18:48 ` [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-08-25 18:48 ` [PULL 18/18] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-08-25 21:24 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-08-25 21:21 ` Alistair Francis
2020-08-25 21:49 ` Peter Maydell
2020-08-25 22:30 ` Alistair Francis
2020-08-26 3:21 ` Bin Meng
2020-08-26 9:25 ` Peter Maydell
2020-08-26 10:06 ` Bin Meng
2020-08-27 15:44 ` Alistair Francis [this message]
2020-08-29 15:49 ` LIU Zhiwei
2020-08-29 17:30 ` Alistair Francis
2020-08-26 9:28 ` Peter Maydell
2020-10-29 14:13 Alistair Francis
2020-11-01 14:02 ` Peter Maydell
2020-11-01 16:27 ` Bin Meng
2021-10-28 4:43 Alistair Francis
2021-10-28 16:54 ` Richard Henderson
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