* [PATCH 01/17] pci: pass along the return value of dma_memory_rw
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 02/17] hw/block/nvme: handle dma errors Klaus Jensen
` (16 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen,
Philippe Mathieu-Daudé
From: Klaus Jensen <k.jensen@samsung.com>
Some devices might want to know the return value of dma_memory_rw, so
pass it along instead of ignoring it.
There are no existing users of the return value, so this patch should be
safe.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Keith Busch <kbusch@kernel.org>
---
include/hw/pci/pci.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 4ca7258b5b71..896cef9ad476 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -788,8 +788,7 @@ static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len, DMADirection dir)
{
- dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
- return 0;
+ return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
}
static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 02/17] hw/block/nvme: handle dma errors
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
2020-09-04 14:19 ` [PATCH 01/17] pci: pass along the return value of dma_memory_rw Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-07 2:34 ` Philippe Mathieu-Daudé
2020-09-04 14:19 ` [PATCH 03/17] hw/block/nvme: commonize nvme_rw error handling Klaus Jensen
` (15 subsequent siblings)
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen,
Maxim Levitsky
From: Klaus Jensen <k.jensen@samsung.com>
Handling DMA errors gracefully is required for the device to pass the
block/011 test ("disable PCI device while doing I/O") in the blktests
suite.
With this patch the device passes the test by retrying "critical"
transfers (posting of completion entries and processing of submission
queue entries).
If DMA errors occur at any other point in the execution of the command
(say, while mapping the PRPs), the command is aborted with a Data
Transfer Error status code.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
hw/block/nvme.c | 43 ++++++++++++++++++++++++++++++++-----------
hw/block/trace-events | 2 ++
include/block/nvme.h | 2 +-
3 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 63078f600920..49bcdf31ced6 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -140,14 +140,14 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
return &n->cmbuf[addr - n->ctrl_mem.addr];
}
-static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
+static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) {
memcpy(buf, nvme_addr_to_cmb(n, addr), size);
- return;
+ return 0;
}
- pci_dma_read(&n->parent_obj, addr, buf, size);
+ return pci_dma_read(&n->parent_obj, addr, buf, size);
}
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
@@ -253,7 +253,7 @@ static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
trace_pci_nvme_map_addr_cmb(addr, len);
if (!nvme_addr_is_cmb(n, addr) || !nvme_addr_is_cmb(n, addr + len - 1)) {
- return NVME_DATA_TRAS_ERROR;
+ return NVME_DATA_TRANSFER_ERROR;
}
qemu_iovec_add(iov, nvme_addr_to_cmb(n, addr), len);
@@ -307,6 +307,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
int num_prps = (len >> n->page_bits) + 1;
uint16_t status;
bool prp_list_in_cmb = false;
+ int ret;
QEMUSGList *qsg = &req->qsg;
QEMUIOVector *iov = &req->iov;
@@ -347,7 +348,11 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
- nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
+ ret = nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
+ if (ret) {
+ trace_pci_nvme_err_addr_read(prp2);
+ return NVME_DATA_TRANSFER_ERROR;
+ }
while (len != 0) {
uint64_t prp_ent = le64_to_cpu(prp_list[i]);
@@ -364,8 +369,12 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
- nvme_addr_read(n, prp_ent, (void *)prp_list,
- prp_trans);
+ ret = nvme_addr_read(n, prp_ent, (void *)prp_list,
+ prp_trans);
+ if (ret) {
+ trace_pci_nvme_err_addr_read(prp_ent);
+ return NVME_DATA_TRANSFER_ERROR;
+ }
prp_ent = le64_to_cpu(prp_list[i]);
}
@@ -457,6 +466,7 @@ static void nvme_post_cqes(void *opaque)
NvmeCQueue *cq = opaque;
NvmeCtrl *n = cq->ctrl;
NvmeRequest *req, *next;
+ int ret;
QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
NvmeSQueue *sq;
@@ -466,15 +476,21 @@ static void nvme_post_cqes(void *opaque)
break;
}
- QTAILQ_REMOVE(&cq->req_list, req, entry);
sq = req->sq;
req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
req->cqe.sq_id = cpu_to_le16(sq->sqid);
req->cqe.sq_head = cpu_to_le16(sq->head);
addr = cq->dma_addr + cq->tail * n->cqe_size;
+ ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
+ sizeof(req->cqe));
+ if (ret) {
+ trace_pci_nvme_err_addr_write(addr);
+ timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ 500 * SCALE_MS);
+ break;
+ }
+ QTAILQ_REMOVE(&cq->req_list, req, entry);
nvme_inc_cq_tail(cq);
- pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
- sizeof(req->cqe));
nvme_req_exit(req);
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
@@ -1611,7 +1627,12 @@ static void nvme_process_sq(void *opaque)
while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
addr = sq->dma_addr + sq->head * n->sqe_size;
- nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
+ if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) {
+ trace_pci_nvme_err_addr_read(addr);
+ timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ 500 * SCALE_MS);
+ break;
+ }
nvme_inc_sq_head(sq);
req = QTAILQ_FIRST(&sq->req_list);
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 72cf2d15cb8e..50d5702e6b80 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -86,6 +86,8 @@ pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
# nvme traces for error conditions
pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu"
+pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64""
+pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64""
pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64""
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
diff --git a/include/block/nvme.h b/include/block/nvme.h
index 65e68a82c897..c8d0a3473f0d 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -630,7 +630,7 @@ enum NvmeStatusCodes {
NVME_INVALID_OPCODE = 0x0001,
NVME_INVALID_FIELD = 0x0002,
NVME_CID_CONFLICT = 0x0003,
- NVME_DATA_TRAS_ERROR = 0x0004,
+ NVME_DATA_TRANSFER_ERROR = 0x0004,
NVME_POWER_LOSS_ABORT = 0x0005,
NVME_INTERNAL_DEV_ERROR = 0x0006,
NVME_CMD_ABORT_REQ = 0x0007,
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 02/17] hw/block/nvme: handle dma errors
2020-09-04 14:19 ` [PATCH 02/17] hw/block/nvme: handle dma errors Klaus Jensen
@ 2020-09-07 2:34 ` Philippe Mathieu-Daudé
2020-09-07 7:49 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 2:34 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Maxim Levitsky
Hi Klaus,
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Handling DMA errors gracefully is required for the device to pass the
> block/011 test ("disable PCI device while doing I/O") in the blktests
> suite.
>
> With this patch the device passes the test by retrying "critical"
> transfers (posting of completion entries and processing of submission
> queue entries).
>
> If DMA errors occur at any other point in the execution of the command
> (say, while mapping the PRPs), the command is aborted with a Data
> Transfer Error status code.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> Acked-by: Keith Busch <kbusch@kernel.org>
> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> ---
> hw/block/nvme.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/block/trace-events | 2 ++
> include/block/nvme.h | 2 +-
> 3 files changed, 35 insertions(+), 12 deletions(-)
>
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index 63078f600920..49bcdf31ced6 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -140,14 +140,14 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
> return &n->cmbuf[addr - n->ctrl_mem.addr];
> }
>
> -static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
> +static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
If this get merged first:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg737483.html
then please return MemTxResult, ...
> {
> if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) {
> memcpy(buf, nvme_addr_to_cmb(n, addr), size);
> - return;
> + return 0;
> }
>
> - pci_dma_read(&n->parent_obj, addr, buf, size);
> + return pci_dma_read(&n->parent_obj, addr, buf, size);
> }
>
> static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
> @@ -253,7 +253,7 @@ static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
> trace_pci_nvme_map_addr_cmb(addr, len);
>
> if (!nvme_addr_is_cmb(n, addr) || !nvme_addr_is_cmb(n, addr + len - 1)) {
> - return NVME_DATA_TRAS_ERROR;
> + return NVME_DATA_TRANSFER_ERROR;
> }
>
> qemu_iovec_add(iov, nvme_addr_to_cmb(n, addr), len);
> @@ -307,6 +307,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
> int num_prps = (len >> n->page_bits) + 1;
> uint16_t status;
> bool prp_list_in_cmb = false;
> + int ret;
>
> QEMUSGList *qsg = &req->qsg;
> QEMUIOVector *iov = &req->iov;
> @@ -347,7 +348,11 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
>
> nents = (len + n->page_size - 1) >> n->page_bits;
> prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
> - nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
> + ret = nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
> + if (ret) {
... and check it (other cases following).
> + trace_pci_nvme_err_addr_read(prp2);
> + return NVME_DATA_TRANSFER_ERROR;
> + }
> while (len != 0) {
> uint64_t prp_ent = le64_to_cpu(prp_list[i]);
>
> @@ -364,8 +369,12 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
> i = 0;
> nents = (len + n->page_size - 1) >> n->page_bits;
> prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
> - nvme_addr_read(n, prp_ent, (void *)prp_list,
> - prp_trans);
> + ret = nvme_addr_read(n, prp_ent, (void *)prp_list,
> + prp_trans);
> + if (ret) {
> + trace_pci_nvme_err_addr_read(prp_ent);
> + return NVME_DATA_TRANSFER_ERROR;
> + }
> prp_ent = le64_to_cpu(prp_list[i]);
> }
>
> @@ -457,6 +466,7 @@ static void nvme_post_cqes(void *opaque)
> NvmeCQueue *cq = opaque;
> NvmeCtrl *n = cq->ctrl;
> NvmeRequest *req, *next;
> + int ret;
>
> QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
> NvmeSQueue *sq;
> @@ -466,15 +476,21 @@ static void nvme_post_cqes(void *opaque)
> break;
> }
>
> - QTAILQ_REMOVE(&cq->req_list, req, entry);
> sq = req->sq;
> req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
> req->cqe.sq_id = cpu_to_le16(sq->sqid);
> req->cqe.sq_head = cpu_to_le16(sq->head);
> addr = cq->dma_addr + cq->tail * n->cqe_size;
> + ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
> + sizeof(req->cqe));
> + if (ret) {
> + trace_pci_nvme_err_addr_write(addr);
> + timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> + 500 * SCALE_MS);
> + break;
> + }
> + QTAILQ_REMOVE(&cq->req_list, req, entry);
> nvme_inc_cq_tail(cq);
> - pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
> - sizeof(req->cqe));
> nvme_req_exit(req);
> QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
> }
> @@ -1611,7 +1627,12 @@ static void nvme_process_sq(void *opaque)
>
> while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
> addr = sq->dma_addr + sq->head * n->sqe_size;
> - nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
> + if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) {
> + trace_pci_nvme_err_addr_read(addr);
> + timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
> + 500 * SCALE_MS);
> + break;
> + }
> nvme_inc_sq_head(sq);
>
> req = QTAILQ_FIRST(&sq->req_list);
> diff --git a/hw/block/trace-events b/hw/block/trace-events
> index 72cf2d15cb8e..50d5702e6b80 100644
> --- a/hw/block/trace-events
> +++ b/hw/block/trace-events
> @@ -86,6 +86,8 @@ pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
>
> # nvme traces for error conditions
> pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu"
> +pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64""
> +pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64""
> pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
> pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64""
> pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
> diff --git a/include/block/nvme.h b/include/block/nvme.h
> index 65e68a82c897..c8d0a3473f0d 100644
> --- a/include/block/nvme.h
> +++ b/include/block/nvme.h
> @@ -630,7 +630,7 @@ enum NvmeStatusCodes {
> NVME_INVALID_OPCODE = 0x0001,
> NVME_INVALID_FIELD = 0x0002,
> NVME_CID_CONFLICT = 0x0003,
> - NVME_DATA_TRAS_ERROR = 0x0004,
> + NVME_DATA_TRANSFER_ERROR = 0x0004,
> NVME_POWER_LOSS_ABORT = 0x0005,
> NVME_INTERNAL_DEV_ERROR = 0x0006,
> NVME_CMD_ABORT_REQ = 0x0007,
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 02/17] hw/block/nvme: handle dma errors
2020-09-07 2:34 ` Philippe Mathieu-Daudé
@ 2020-09-07 7:49 ` Klaus Jensen
0 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 7:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch, Maxim Levitsky
[-- Attachment #1: Type: text/plain, Size: 1693 bytes --]
On Sep 7 04:34, Philippe Mathieu-Daudé wrote:
> Hi Klaus,
>
> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > Handling DMA errors gracefully is required for the device to pass the
> > block/011 test ("disable PCI device while doing I/O") in the blktests
> > suite.
> >
> > With this patch the device passes the test by retrying "critical"
> > transfers (posting of completion entries and processing of submission
> > queue entries).
> >
> > If DMA errors occur at any other point in the execution of the command
> > (say, while mapping the PRPs), the command is aborted with a Data
> > Transfer Error status code.
> >
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > Acked-by: Keith Busch <kbusch@kernel.org>
> > Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> > ---
> > hw/block/nvme.c | 43 ++++++++++++++++++++++++++++++++-----------
> > hw/block/trace-events | 2 ++
> > include/block/nvme.h | 2 +-
> > 3 files changed, 35 insertions(+), 12 deletions(-)
> >
> > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > index 63078f600920..49bcdf31ced6 100644
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -140,14 +140,14 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
> > return &n->cmbuf[addr - n->ctrl_mem.addr];
> > }
> >
> > -static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
> > +static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
>
> If this get merged first:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg737483.html
> then please return MemTxResult, ...
>
Noted! :)
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 03/17] hw/block/nvme: commonize nvme_rw error handling
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
2020-09-04 14:19 ` [PATCH 01/17] pci: pass along the return value of dma_memory_rw Klaus Jensen
2020-09-04 14:19 ` [PATCH 02/17] hw/block/nvme: handle dma errors Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 04/17] hw/block/nvme: alignment style fixes Klaus Jensen
` (14 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Move common error handling to a label.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 49bcdf31ced6..a94e648a80e4 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -687,20 +687,18 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
status = nvme_check_mdts(n, data_size);
if (status) {
trace_pci_nvme_err_mdts(nvme_cid(req), data_size);
- block_acct_invalid(blk_get_stats(n->conf.blk), acct);
- return status;
+ goto invalid;
}
status = nvme_check_bounds(n, ns, slba, nlb);
if (status) {
trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
- block_acct_invalid(blk_get_stats(n->conf.blk), acct);
- return status;
+ goto invalid;
}
- if (nvme_map_dptr(n, data_size, req)) {
- block_acct_invalid(blk_get_stats(n->conf.blk), acct);
- return NVME_INVALID_FIELD | NVME_DNR;
+ status = nvme_map_dptr(n, data_size, req);
+ if (status) {
+ goto invalid;
}
if (req->qsg.nsg > 0) {
@@ -722,6 +720,10 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
}
return NVME_NO_COMPLETE;
+
+invalid:
+ block_acct_invalid(blk_get_stats(n->conf.blk), acct);
+ return status;
}
static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 04/17] hw/block/nvme: alignment style fixes
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (2 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 03/17] hw/block/nvme: commonize nvme_rw error handling Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-07 2:29 ` Philippe Mathieu-Daudé
2020-09-04 14:19 ` [PATCH 05/17] hw/block/nvme: add a lba to bytes helper Klaus Jensen
` (13 subsequent siblings)
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Style fixes.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index a94e648a80e4..88b4e6288bea 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -634,7 +634,7 @@ static void nvme_rw_cb(void *opaque, int ret)
static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
{
block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
- BLOCK_ACCT_FLUSH);
+ BLOCK_ACCT_FLUSH);
req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
return NVME_NO_COMPLETE;
@@ -663,7 +663,7 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
BLOCK_ACCT_WRITE);
req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
- BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
+ BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
return NVME_NO_COMPLETE;
}
@@ -803,7 +803,7 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
}
static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
- uint16_t sqid, uint16_t cqid, uint16_t size)
+ uint16_t sqid, uint16_t cqid, uint16_t size)
{
int i;
NvmeCQueue *cq;
@@ -1058,7 +1058,8 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req)
}
static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
- uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
+ uint16_t cqid, uint16_t vector, uint16_t size,
+ uint16_t irq_enabled)
{
int ret;
@@ -1118,7 +1119,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
cq = g_malloc0(sizeof(*cq));
nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
- NVME_CQ_FLAGS_IEN(qflags));
+ NVME_CQ_FLAGS_IEN(qflags));
/*
* It is only required to set qs_created when creating a completion queue;
@@ -1520,7 +1521,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
}
if (((n->temperature >= n->features.temp_thresh_hi) ||
- (n->temperature <= n->features.temp_thresh_low)) &&
+ (n->temperature <= n->features.temp_thresh_low)) &&
NVME_AEC_SMART(n->features.async_config) & NVME_SMART_TEMPERATURE) {
nvme_enqueue_event(n, NVME_AER_TYPE_SMART,
NVME_AER_INFO_SMART_TEMP_THRESH,
@@ -1770,9 +1771,9 @@ static int nvme_start_ctrl(NvmeCtrl *n)
n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
- NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
+ NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
- NVME_AQA_ASQS(n->bar.aqa) + 1);
+ NVME_AQA_ASQS(n->bar.aqa) + 1);
nvme_set_timestamp(n, 0ULL);
@@ -1782,7 +1783,7 @@ static int nvme_start_ctrl(NvmeCtrl *n)
}
static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
- unsigned size)
+ unsigned size)
{
if (unlikely(offset & (sizeof(uint32_t) - 1))) {
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
@@ -1925,7 +1926,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
"invalid write to PMRSWTP register, ignored");
return;
case 0xE14: /* TODO PMRMSC */
- break;
+ break;
default:
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
"invalid MMIO write,"
@@ -2101,7 +2102,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
}
static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
- unsigned size)
+ unsigned size)
{
NvmeCtrl *n = (NvmeCtrl *)opaque;
@@ -2125,7 +2126,7 @@ static const MemoryRegionOps nvme_mmio_ops = {
};
static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
- unsigned size)
+ unsigned size)
{
NvmeCtrl *n = (NvmeCtrl *)opaque;
stn_le_p(&n->cmbuf[addr], size, data);
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 04/17] hw/block/nvme: alignment style fixes
2020-09-04 14:19 ` [PATCH 04/17] hw/block/nvme: alignment style fixes Klaus Jensen
@ 2020-09-07 2:29 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 2:29 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Style fixes.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> ---
> hw/block/nvme.c | 25 +++++++++++++------------
> 1 file changed, 13 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 05/17] hw/block/nvme: add a lba to bytes helper
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (3 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 04/17] hw/block/nvme: alignment style fixes Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 06/17] hw/block/nvme: fix endian conversion Klaus Jensen
` (12 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Add the nvme_l2b helper and use it for converting NLB and SLBA to byte
counts and offsets.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 12 ++++--------
hw/block/nvme.h | 6 ++++++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 88b4e6288bea..08f824dd807d 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -644,12 +644,10 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
- const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
- const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
uint64_t slba = le64_to_cpu(rw->slba);
uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
- uint64_t offset = slba << data_shift;
- uint32_t count = nlb << data_shift;
+ uint64_t offset = nvme_l2b(ns, slba);
+ uint32_t count = nvme_l2b(ns, nlb);
uint16_t status;
trace_pci_nvme_write_zeroes(nvme_cid(req), slba, nlb);
@@ -674,10 +672,8 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
uint32_t nlb = le32_to_cpu(rw->nlb) + 1;
uint64_t slba = le64_to_cpu(rw->slba);
- uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
- uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
- uint64_t data_size = (uint64_t)nlb << data_shift;
- uint64_t data_offset = slba << data_shift;
+ uint64_t data_size = nvme_l2b(ns, nlb);
+ uint64_t data_offset = nvme_l2b(ns, slba);
int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
uint16_t status;
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 52ba794f2e9a..1675c1e0755c 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -77,6 +77,12 @@ static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
return nvme_ns_lbaf(ns)->ds;
}
+/* convert an LBA to the equivalent in bytes */
+static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
+{
+ return lba << nvme_ns_lbads(ns);
+}
+
#define TYPE_NVME "nvme"
#define NVME(obj) \
OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 06/17] hw/block/nvme: fix endian conversion
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (4 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 05/17] hw/block/nvme: add a lba to bytes helper Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 07/17] hw/block/nvme: add symbolic command name to trace events Klaus Jensen
` (11 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
The raw NLB field is a 16 bit value, so use le16_to_cpu instead of
le32_to_cpu and cast to uint32_t before incrementing the value to not
wrap around.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 08f824dd807d..50851ab8d90f 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -645,7 +645,7 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
uint64_t slba = le64_to_cpu(rw->slba);
- uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
+ uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
uint64_t offset = nvme_l2b(ns, slba);
uint32_t count = nvme_l2b(ns, nlb);
uint16_t status;
@@ -669,7 +669,7 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
- uint32_t nlb = le32_to_cpu(rw->nlb) + 1;
+ uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
uint64_t slba = le64_to_cpu(rw->slba);
uint64_t data_size = nvme_l2b(ns, nlb);
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 07/17] hw/block/nvme: add symbolic command name to trace events
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (5 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 06/17] hw/block/nvme: fix endian conversion Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-07 2:14 ` Philippe Mathieu-Daudé
2020-09-04 14:19 ` [PATCH 08/17] hw/block/nvme: refactor aio submission Klaus Jensen
` (10 subsequent siblings)
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Add the symbolic command name to the pci_nvme_{io,admin}_cmd and
pci_nvme_rw trace events.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 8 +++++---
hw/block/nvme.h | 28 ++++++++++++++++++++++++++++
hw/block/trace-events | 6 +++---
3 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 50851ab8d90f..bfac3385cb64 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -678,7 +678,8 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
uint16_t status;
- trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
+ trace_pci_nvme_rw(nvme_cid(req), nvme_io_opc_str(rw->opcode), nlb,
+ data_size, slba);
status = nvme_check_mdts(n, data_size);
if (status) {
@@ -727,7 +728,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
uint32_t nsid = le32_to_cpu(req->cmd.nsid);
trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req),
- req->cmd.opcode);
+ req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode));
if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
@@ -1584,7 +1585,8 @@ static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req)
static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
{
- trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode);
+ trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
+ nvme_adm_opc_str(req->cmd.opcode));
switch (req->cmd.opcode) {
case NVME_ADM_CMD_DELETE_SQ:
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 1675c1e0755c..ce9e931420d7 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -32,6 +32,34 @@ typedef struct NvmeRequest {
QTAILQ_ENTRY(NvmeRequest)entry;
} NvmeRequest;
+static inline const char *nvme_adm_opc_str(uint8_t opc)
+{
+ switch (opc) {
+ case NVME_ADM_CMD_DELETE_SQ: return "NVME_ADM_CMD_DELETE_SQ";
+ case NVME_ADM_CMD_CREATE_SQ: return "NVME_ADM_CMD_CREATE_SQ";
+ case NVME_ADM_CMD_GET_LOG_PAGE: return "NVME_ADM_CMD_GET_LOG_PAGE";
+ case NVME_ADM_CMD_DELETE_CQ: return "NVME_ADM_CMD_DELETE_CQ";
+ case NVME_ADM_CMD_CREATE_CQ: return "NVME_ADM_CMD_CREATE_CQ";
+ case NVME_ADM_CMD_IDENTIFY: return "NVME_ADM_CMD_IDENTIFY";
+ case NVME_ADM_CMD_ABORT: return "NVME_ADM_CMD_ABORT";
+ case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
+ case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
+ case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
+ default: return "NVME_ADM_CMD_UNKNOWN";
+ }
+}
+
+static inline const char *nvme_io_opc_str(uint8_t opc)
+{
+ switch (opc) {
+ case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH";
+ case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE";
+ case NVME_CMD_READ: return "NVME_NVM_CMD_READ";
+ case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
+ default: return "NVME_NVM_CMD_UNKNOWN";
+ }
+}
+
typedef struct NvmeSQueue {
struct NvmeCtrl *ctrl;
uint16_t sqid;
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 50d5702e6b80..0823d0fb47c5 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -36,9 +36,9 @@ pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2
pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
-pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8""
-pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8""
-pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64""
+pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
+pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
+pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" \"%s\" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
pci_nvme_rw_cb(uint16_t cid) "cid %"PRIu16""
pci_nvme_write_zeroes(uint16_t cid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" slba %"PRIu64" nlb %"PRIu32""
pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 07/17] hw/block/nvme: add symbolic command name to trace events
2020-09-04 14:19 ` [PATCH 07/17] hw/block/nvme: add symbolic command name to trace events Klaus Jensen
@ 2020-09-07 2:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 2:14 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add the symbolic command name to the pci_nvme_{io,admin}_cmd and
> pci_nvme_rw trace events.
>
[...]> diff --git a/hw/block/trace-events b/hw/block/trace-events
> index 50d5702e6b80..0823d0fb47c5 100644
> --- a/hw/block/trace-events
> +++ b/hw/block/trace-events
> @@ -36,9 +36,9 @@ pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2
> pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
> pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
> pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
> -pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8""
> -pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8""
> -pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64""
> +pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
> +pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
> +pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" \"%s\" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
> pci_nvme_rw_cb(uint16_t cid) "cid %"PRIu16""
> pci_nvme_write_zeroes(uint16_t cid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" slba %"PRIu64" nlb %"PRIu32""
> pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
>
I'd display the command name using simple quote.
Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 08/17] hw/block/nvme: refactor aio submission
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (6 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 07/17] hw/block/nvme: add symbolic command name to trace events Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 19:47 ` Keith Busch
2020-09-04 14:19 ` [PATCH 09/17] hw/block/nvme: default request status to success Klaus Jensen
` (9 subsequent siblings)
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
This pulls block layer aio submission to a common function an introduces
the NvmeAIO structure that encapsulates this.
This adds more code with no immediate benefit, but is in preparation for
supporting multiple aios per request.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 191 ++++++++++++++++++++++++++++++++----------
hw/block/nvme.h | 51 +++++++++++
hw/block/trace-events | 3 +
3 files changed, 203 insertions(+), 42 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index bfac3385cb64..3e32f39c7c1d 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
};
static void nvme_process_sq(void *opaque);
+static void nvme_aio_cb(void *opaque, int ret);
static uint16_t nvme_cid(NvmeRequest *req)
{
@@ -611,39 +612,151 @@ static inline uint16_t nvme_check_bounds(NvmeCtrl *n, NvmeNamespace *ns,
return NVME_SUCCESS;
}
-static void nvme_rw_cb(void *opaque, int ret)
+static NvmeAIO *nvme_aio_new(NvmeAIOOp opc, BlockBackend *blk, int64_t offset)
{
- NvmeRequest *req = opaque;
- NvmeSQueue *sq = req->sq;
- NvmeCtrl *n = sq->ctrl;
- NvmeCQueue *cq = n->cq[sq->cqid];
+ NvmeAIO *aio = g_new0(NvmeAIO, 1);
- trace_pci_nvme_rw_cb(nvme_cid(req));
+ aio->opc = opc;
+ aio->blk = blk;
+ aio->offset = offset;
- if (!ret) {
- block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
- req->status = NVME_SUCCESS;
- } else {
- block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
- req->status = NVME_INTERNAL_DEV_ERROR;
+ return aio;
+}
+
+static void nvme_aio_destroy(NvmeAIO *aio)
+{
+ g_free(aio);
+}
+
+static uint16_t nvme_do_aio(NvmeAIO *aio)
+{
+ NvmeRequest *req = aio->req;
+
+ BlockBackend *blk = aio->blk;
+ BlockAcctCookie *acct = &req->acct;
+ BlockAcctStats *stats = blk_get_stats(blk);
+
+ bool is_write;
+
+ switch (aio->opc) {
+ case NVME_AIO_OPC_FLUSH:
+ block_acct_start(stats, acct, 0, BLOCK_ACCT_FLUSH);
+ req->aiocb = blk_aio_flush(blk, nvme_aio_cb, aio);
+ break;
+
+ case NVME_AIO_OPC_WRITE_ZEROES:
+ block_acct_start(stats, acct, aio->len, BLOCK_ACCT_WRITE);
+ req->aiocb = blk_aio_pwrite_zeroes(blk, aio->offset, aio->len,
+ BDRV_REQ_MAY_UNMAP, nvme_aio_cb,
+ aio);
+ break;
+
+ case NVME_AIO_OPC_READ:
+ case NVME_AIO_OPC_WRITE:
+ is_write = (aio->opc == NVME_AIO_OPC_WRITE);
+
+ block_acct_start(stats, acct, aio->len,
+ is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
+
+ if (aio->flags & NVME_AIO_DMA) {
+ QEMUSGList *qsg = (QEMUSGList *)aio->payload;
+
+ if (is_write) {
+ req->aiocb = dma_blk_write(blk, qsg, aio->offset,
+ BDRV_SECTOR_SIZE, nvme_aio_cb, aio);
+ } else {
+ req->aiocb = dma_blk_read(blk, qsg, aio->offset,
+ BDRV_SECTOR_SIZE, nvme_aio_cb, aio);
+ }
+ } else {
+ QEMUIOVector *iov = (QEMUIOVector *)aio->payload;
+
+ if (is_write) {
+ req->aiocb = blk_aio_pwritev(blk, aio->offset, iov, 0,
+ nvme_aio_cb, aio);
+ } else {
+ req->aiocb = blk_aio_preadv(blk, aio->offset, iov, 0,
+ nvme_aio_cb, aio);
+ }
+ }
+
+ break;
}
- nvme_enqueue_req_completion(cq, req);
+ return NVME_NO_COMPLETE;
+}
+
+static uint16_t nvme_aio_add(NvmeRequest *req, NvmeAIO *aio)
+{
+ aio->req = req;
+
+ trace_pci_nvme_aio_add(nvme_cid(req), aio, blk_name(aio->blk),
+ aio->offset, aio->len, nvme_aio_opc_str(aio),
+ req);
+
+ return nvme_do_aio(aio);
+}
+
+static void nvme_aio_cb(void *opaque, int ret)
+{
+ NvmeAIO *aio = opaque;
+ NvmeRequest *req = aio->req;
+
+ BlockBackend *blk = aio->blk;
+ BlockAcctCookie *acct = &req->acct;
+ BlockAcctStats *stats = blk_get_stats(blk);
+
+ Error *local_err = NULL;
+
+ trace_pci_nvme_aio_cb(nvme_cid(req), aio, blk_name(blk), aio->offset,
+ aio->len, nvme_aio_opc_str(aio), req);
+
+ if (!ret) {
+ block_acct_done(stats, acct);
+ req->status = NVME_SUCCESS;
+ } else {
+ uint16_t status;
+
+ block_acct_failed(stats, acct);
+
+ switch (aio->opc) {
+ case NVME_AIO_OPC_READ:
+ status = NVME_UNRECOVERED_READ;
+ break;
+ case NVME_AIO_OPC_FLUSH:
+ case NVME_AIO_OPC_WRITE:
+ case NVME_AIO_OPC_WRITE_ZEROES:
+ status = NVME_WRITE_FAULT;
+ break;
+ default:
+ status = NVME_INTERNAL_DEV_ERROR;
+ break;
+ }
+
+ trace_pci_nvme_err_aio(nvme_cid(req), aio, blk_name(blk),
+ aio->offset, nvme_aio_opc_str(aio), req,
+ status);
+
+ error_setg_errno(&local_err, -ret, "aio failed");
+ error_report_err(local_err);
+
+ req->status = status;
+ }
+
+ nvme_enqueue_req_completion(nvme_cq(req), req);
+ nvme_aio_destroy(aio);
}
static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
{
- block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
- BLOCK_ACCT_FLUSH);
- req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
-
- return NVME_NO_COMPLETE;
+ return nvme_aio_add(req, nvme_aio_new(NVME_AIO_OPC_FLUSH, n->conf.blk, 0));
}
static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
+ NvmeAIO *aio;
uint64_t slba = le64_to_cpu(rw->slba);
uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
uint64_t offset = nvme_l2b(ns, slba);
@@ -658,24 +771,23 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
return status;
}
- block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
- BLOCK_ACCT_WRITE);
- req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
- BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
- return NVME_NO_COMPLETE;
+ aio = nvme_aio_new(NVME_AIO_OPC_WRITE_ZEROES, n->conf.blk, offset);
+ aio->len = count;
+
+ return nvme_aio_add(req, aio);
}
static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
{
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
NvmeNamespace *ns = req->ns;
+ NvmeAIO *aio;
uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1;
uint64_t slba = le64_to_cpu(rw->slba);
uint64_t data_size = nvme_l2b(ns, nlb);
uint64_t data_offset = nvme_l2b(ns, slba);
- int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
- enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
+ bool is_write = nvme_req_is_write(req);
uint16_t status;
trace_pci_nvme_rw(nvme_cid(req), nvme_io_opc_str(rw->opcode), nlb,
@@ -698,28 +810,23 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
goto invalid;
}
- if (req->qsg.nsg > 0) {
- block_acct_start(blk_get_stats(n->conf.blk), &req->acct, req->qsg.size,
- acct);
- req->aiocb = is_write ?
- dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
- nvme_rw_cb, req) :
- dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
- nvme_rw_cb, req);
+ aio = nvme_aio_new(is_write ? NVME_AIO_OPC_WRITE : NVME_AIO_OPC_READ,
+ n->conf.blk, data_offset);
+
+ if (req->qsg.sg) {
+ aio->payload = &req->qsg;
+ aio->len = req->qsg.size;
+ aio->flags |= NVME_AIO_DMA;
} else {
- block_acct_start(blk_get_stats(n->conf.blk), &req->acct, req->iov.size,
- acct);
- req->aiocb = is_write ?
- blk_aio_pwritev(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
- req) :
- blk_aio_preadv(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
- req);
+ aio->payload = &req->iov;
+ aio->len = req->iov.size;
}
- return NVME_NO_COMPLETE;
+ return nvme_aio_add(req, aio);
invalid:
- block_acct_invalid(blk_get_stats(n->conf.blk), acct);
+ block_acct_invalid(blk_get_stats(n->conf.blk),
+ is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
return status;
}
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index ce9e931420d7..7a11b0b37317 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -32,6 +32,17 @@ typedef struct NvmeRequest {
QTAILQ_ENTRY(NvmeRequest)entry;
} NvmeRequest;
+static inline bool nvme_req_is_write(NvmeRequest *req)
+{
+ switch (req->cmd.opcode) {
+ case NVME_CMD_WRITE:
+ case NVME_CMD_WRITE_ZEROES:
+ return true;
+ default:
+ return false;
+ }
+}
+
static inline const char *nvme_adm_opc_str(uint8_t opc)
{
switch (opc) {
@@ -60,6 +71,38 @@ static inline const char *nvme_io_opc_str(uint8_t opc)
}
}
+typedef enum NvmeAIOOp {
+ NVME_AIO_OPC_FLUSH = 0x1,
+ NVME_AIO_OPC_READ = 0x2,
+ NVME_AIO_OPC_WRITE = 0x3,
+ NVME_AIO_OPC_WRITE_ZEROES = 0x4,
+} NvmeAIOOp;
+
+typedef enum NvmeAIOFlags {
+ NVME_AIO_DMA = 1 << 0,
+} NvmeAIOFlags;
+
+typedef struct NvmeAIO {
+ NvmeAIOOp opc;
+ NvmeRequest *req;
+ BlockBackend *blk;
+ int64_t offset;
+ size_t len;
+ int flags;
+ void *payload;
+} NvmeAIO;
+
+static inline const char *nvme_aio_opc_str(NvmeAIO *aio)
+{
+ switch (aio->opc) {
+ case NVME_AIO_OPC_FLUSH: return "NVME_AIO_OPC_FLUSH";
+ case NVME_AIO_OPC_READ: return "NVME_AIO_OPC_READ";
+ case NVME_AIO_OPC_WRITE: return "NVME_AIO_OPC_WRITE";
+ case NVME_AIO_OPC_WRITE_ZEROES: return "NVME_AIO_OPC_WRITE_ZEROES";
+ default: return "NVME_AIO_OPC_UNKNOWN";
+ }
+}
+
typedef struct NvmeSQueue {
struct NvmeCtrl *ctrl;
uint16_t sqid;
@@ -171,4 +214,12 @@ static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns)
return n->ns_size >> nvme_ns_lbads(ns);
}
+static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
+{
+ NvmeSQueue *sq = req->sq;
+ NvmeCtrl *n = sq->ctrl;
+
+ return n->cq[sq->cqid];
+}
+
#endif /* HW_NVME_H */
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 0823d0fb47c5..fb3bf1be5e07 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -39,6 +39,8 @@ pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2,
pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" \"%s\" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
+pci_nvme_aio_add(uint16_t cid, void *aio, const char *blkname, uint64_t offset, uint64_t len, const char *opc, void *req) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" len %"PRIu64" opc \"%s\" req %p"
+pci_nvme_aio_cb(uint16_t cid, void *aio, const char *blkname, uint64_t offset, uint64_t len, const char *opc, void *req) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" len %"PRIu64" opc \"%s\" req %p"
pci_nvme_rw_cb(uint16_t cid) "cid %"PRIu16""
pci_nvme_write_zeroes(uint16_t cid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" slba %"PRIu64" nlb %"PRIu32""
pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
@@ -88,6 +90,7 @@ pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared"
pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu"
pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64""
pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64""
+pci_nvme_err_aio(uint16_t cid, void *aio, const char *blkname, uint64_t offset, const char *opc, void *req, uint16_t status) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" opc \"%s\" req %p status 0x%"PRIx16""
pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64""
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 08/17] hw/block/nvme: refactor aio submission
2020-09-04 14:19 ` [PATCH 08/17] hw/block/nvme: refactor aio submission Klaus Jensen
@ 2020-09-04 19:47 ` Keith Busch
2020-09-04 20:38 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Keith Busch @ 2020-09-04 19:47 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz
On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index bfac3385cb64..3e32f39c7c1d 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
> };
>
> static void nvme_process_sq(void *opaque);
> +static void nvme_aio_cb(void *opaque, int ret);
You don't need the forward declaration here. Just move the
implementation above where it's used. It looks safe: nvme_aio_cb()
doesn't have any circular dependencies.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 08/17] hw/block/nvme: refactor aio submission
2020-09-04 19:47 ` Keith Busch
@ 2020-09-04 20:38 ` Klaus Jensen
2020-09-04 21:15 ` Keith Busch
0 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 20:38 UTC (permalink / raw)
To: Keith Busch
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz
On Sep 4 12:47, Keith Busch wrote:
> On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > index bfac3385cb64..3e32f39c7c1d 100644
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
> > };
> >
> > static void nvme_process_sq(void *opaque);
> > +static void nvme_aio_cb(void *opaque, int ret);
>
> You don't need the forward declaration here. Just move the
> implementation above where it's used. It looks safe: nvme_aio_cb()
> doesn't have any circular dependencies.
You are right, of course. But it is getting a circular dependency in a
later patch. I left it there to reduce code movement later.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 08/17] hw/block/nvme: refactor aio submission
2020-09-04 20:38 ` Klaus Jensen
@ 2020-09-04 21:15 ` Keith Busch
2020-09-04 21:38 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Keith Busch @ 2020-09-04 21:15 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz
On Fri, Sep 04, 2020 at 10:38:39PM +0200, Klaus Jensen wrote:
> On Sep 4 12:47, Keith Busch wrote:
> > On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > index bfac3385cb64..3e32f39c7c1d 100644
> > > --- a/hw/block/nvme.c
> > > +++ b/hw/block/nvme.c
> > > @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
> > > };
> > >
> > > static void nvme_process_sq(void *opaque);
> > > +static void nvme_aio_cb(void *opaque, int ret);
> >
> > You don't need the forward declaration here. Just move the
> > implementation above where it's used. It looks safe: nvme_aio_cb()
> > doesn't have any circular dependencies.
>
> You are right, of course. But it is getting a circular dependency in a
> later patch. I left it there to reduce code movement later.
Is that coming in a future patch? Not finding it in this series.
About the whole patch in general, are multiple aio's per-request coming
in later patch as well? I didn't see any use for it here, and the
overhead of dynamic allocation and zeroing a new struct in the IO path
is a bit concerning for performance. I'd like to see your intended use
for this.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 08/17] hw/block/nvme: refactor aio submission
2020-09-04 21:15 ` Keith Busch
@ 2020-09-04 21:38 ` Klaus Jensen
0 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 21:38 UTC (permalink / raw)
To: Keith Busch
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz
On Sep 4 14:15, Keith Busch wrote:
> On Fri, Sep 04, 2020 at 10:38:39PM +0200, Klaus Jensen wrote:
> > On Sep 4 12:47, Keith Busch wrote:
> > > On Fri, Sep 04, 2020 at 04:19:47PM +0200, Klaus Jensen wrote:
> > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > > index bfac3385cb64..3e32f39c7c1d 100644
> > > > --- a/hw/block/nvme.c
> > > > +++ b/hw/block/nvme.c
> > > > @@ -110,6 +110,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = {
> > > > };
> > > >
> > > > static void nvme_process_sq(void *opaque);
> > > > +static void nvme_aio_cb(void *opaque, int ret);
> > >
> > > You don't need the forward declaration here. Just move the
> > > implementation above where it's used. It looks safe: nvme_aio_cb()
> > > doesn't have any circular dependencies.
> >
> > You are right, of course. But it is getting a circular dependency in a
> > later patch. I left it there to reduce code movement later.
>
> Is that coming in a future patch? Not finding it in this series.
>
> About the whole patch in general, are multiple aio's per-request coming
> in later patch as well? I didn't see any use for it here, and the
> overhead of dynamic allocation and zeroing a new struct in the IO path
> is a bit concerning for performance. I'd like to see your intended use
> for this.
Intended use-case was parallel aios. There are a lot of use cases for
this, DSM, metadata, block allocation tracking and zns zoneinfo.
But I'll rip it out of the series and repost so we can focus on multiple
namespaces.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 09/17] hw/block/nvme: default request status to success
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (7 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 08/17] hw/block/nvme: refactor aio submission Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-07 2:17 ` Philippe Mathieu-Daudé
2020-09-04 14:19 ` [PATCH 10/17] hw/block/nvme: support multiple parallel aios per request Klaus Jensen
` (8 subsequent siblings)
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Make the default request status NVME_SUCCESS so only error status codes
has to be set.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 3e32f39c7c1d..64c8f232e3ea 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -231,6 +231,7 @@ static void nvme_req_clear(NvmeRequest *req)
{
req->ns = NULL;
memset(&req->cqe, 0x0, sizeof(req->cqe));
+ req->status = NVME_SUCCESS;
}
static void nvme_req_exit(NvmeRequest *req)
@@ -547,8 +548,6 @@ static void nvme_process_aers(void *opaque)
result->log_page = event->result.log_page;
g_free(event);
- req->status = NVME_SUCCESS;
-
trace_pci_nvme_aer_post_cqe(result->event_type, result->event_info,
result->log_page);
@@ -713,7 +712,6 @@ static void nvme_aio_cb(void *opaque, int ret)
if (!ret) {
block_acct_done(stats, acct);
- req->status = NVME_SUCCESS;
} else {
uint16_t status;
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 09/17] hw/block/nvme: default request status to success
2020-09-04 14:19 ` [PATCH 09/17] hw/block/nvme: default request status to success Klaus Jensen
@ 2020-09-07 2:17 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 2:17 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Make the default request status NVME_SUCCESS so only error status codes
> has to be set.
Typo 'has' -> 'have'.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/block/nvme.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index 3e32f39c7c1d..64c8f232e3ea 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -231,6 +231,7 @@ static void nvme_req_clear(NvmeRequest *req)
> {
> req->ns = NULL;
> memset(&req->cqe, 0x0, sizeof(req->cqe));
> + req->status = NVME_SUCCESS;
> }
>
> static void nvme_req_exit(NvmeRequest *req)
> @@ -547,8 +548,6 @@ static void nvme_process_aers(void *opaque)
> result->log_page = event->result.log_page;
> g_free(event);
>
> - req->status = NVME_SUCCESS;
> -
> trace_pci_nvme_aer_post_cqe(result->event_type, result->event_info,
> result->log_page);
>
> @@ -713,7 +712,6 @@ static void nvme_aio_cb(void *opaque, int ret)
>
> if (!ret) {
> block_acct_done(stats, acct);
> - req->status = NVME_SUCCESS;
> } else {
> uint16_t status;
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 10/17] hw/block/nvme: support multiple parallel aios per request
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (8 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 09/17] hw/block/nvme: default request status to success Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 11/17] hw/block/nvme: harden cmb access Klaus Jensen
` (7 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Move the BlockAIOCB to NvmeAIO and add a queue of pending AIOs to the
NvmeRequest. Only when the queue is empty is a completion enqueued.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 44 ++++++++++++++++++++++++++++++--------------
hw/block/nvme.h | 6 ++++--
2 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 64c8f232e3ea..36ec8cbb1168 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -629,10 +629,8 @@ static void nvme_aio_destroy(NvmeAIO *aio)
static uint16_t nvme_do_aio(NvmeAIO *aio)
{
- NvmeRequest *req = aio->req;
-
BlockBackend *blk = aio->blk;
- BlockAcctCookie *acct = &req->acct;
+ BlockAcctCookie *acct = &aio->acct;
BlockAcctStats *stats = blk_get_stats(blk);
bool is_write;
@@ -640,12 +638,12 @@ static uint16_t nvme_do_aio(NvmeAIO *aio)
switch (aio->opc) {
case NVME_AIO_OPC_FLUSH:
block_acct_start(stats, acct, 0, BLOCK_ACCT_FLUSH);
- req->aiocb = blk_aio_flush(blk, nvme_aio_cb, aio);
+ aio->aiocb = blk_aio_flush(blk, nvme_aio_cb, aio);
break;
case NVME_AIO_OPC_WRITE_ZEROES:
block_acct_start(stats, acct, aio->len, BLOCK_ACCT_WRITE);
- req->aiocb = blk_aio_pwrite_zeroes(blk, aio->offset, aio->len,
+ aio->aiocb = blk_aio_pwrite_zeroes(blk, aio->offset, aio->len,
BDRV_REQ_MAY_UNMAP, nvme_aio_cb,
aio);
break;
@@ -661,20 +659,20 @@ static uint16_t nvme_do_aio(NvmeAIO *aio)
QEMUSGList *qsg = (QEMUSGList *)aio->payload;
if (is_write) {
- req->aiocb = dma_blk_write(blk, qsg, aio->offset,
+ aio->aiocb = dma_blk_write(blk, qsg, aio->offset,
BDRV_SECTOR_SIZE, nvme_aio_cb, aio);
} else {
- req->aiocb = dma_blk_read(blk, qsg, aio->offset,
+ aio->aiocb = dma_blk_read(blk, qsg, aio->offset,
BDRV_SECTOR_SIZE, nvme_aio_cb, aio);
}
} else {
QEMUIOVector *iov = (QEMUIOVector *)aio->payload;
if (is_write) {
- req->aiocb = blk_aio_pwritev(blk, aio->offset, iov, 0,
+ aio->aiocb = blk_aio_pwritev(blk, aio->offset, iov, 0,
nvme_aio_cb, aio);
} else {
- req->aiocb = blk_aio_preadv(blk, aio->offset, iov, 0,
+ aio->aiocb = blk_aio_preadv(blk, aio->offset, iov, 0,
nvme_aio_cb, aio);
}
}
@@ -693,6 +691,8 @@ static uint16_t nvme_aio_add(NvmeRequest *req, NvmeAIO *aio)
aio->offset, aio->len, nvme_aio_opc_str(aio),
req);
+ QTAILQ_INSERT_TAIL(&req->aio_tailq, aio, entry);
+
return nvme_do_aio(aio);
}
@@ -702,7 +702,7 @@ static void nvme_aio_cb(void *opaque, int ret)
NvmeRequest *req = aio->req;
BlockBackend *blk = aio->blk;
- BlockAcctCookie *acct = &req->acct;
+ BlockAcctCookie *acct = &aio->acct;
BlockAcctStats *stats = blk_get_stats(blk);
Error *local_err = NULL;
@@ -710,6 +710,8 @@ static void nvme_aio_cb(void *opaque, int ret)
trace_pci_nvme_aio_cb(nvme_cid(req), aio, blk_name(blk), aio->offset,
aio->len, nvme_aio_opc_str(aio), req);
+ QTAILQ_REMOVE(&req->aio_tailq, aio, entry);
+
if (!ret) {
block_acct_done(stats, acct);
} else {
@@ -738,10 +740,19 @@ static void nvme_aio_cb(void *opaque, int ret)
error_setg_errno(&local_err, -ret, "aio failed");
error_report_err(local_err);
- req->status = status;
+ /*
+ * An Internal Error trumps all other errors. For other errors, only
+ * set the first encountered.
+ */
+ if (!req->status || (status & 0xfff) == NVME_INTERNAL_DEV_ERROR) {
+ req->status = status;
+ }
+ }
+
+ if (QTAILQ_EMPTY(&req->aio_tailq)) {
+ nvme_enqueue_req_completion(nvme_cq(req), req);
}
- nvme_enqueue_req_completion(nvme_cq(req), req);
nvme_aio_destroy(aio);
}
@@ -872,6 +883,7 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
NvmeRequest *r, *next;
NvmeSQueue *sq;
NvmeCQueue *cq;
+ NvmeAIO *aio;
uint16_t qid = le16_to_cpu(c->qid);
if (unlikely(!qid || nvme_check_sqid(n, qid))) {
@@ -884,8 +896,11 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
sq = n->sq[qid];
while (!QTAILQ_EMPTY(&sq->out_req_list)) {
r = QTAILQ_FIRST(&sq->out_req_list);
- assert(r->aiocb);
- blk_aio_cancel(r->aiocb);
+ while (!QTAILQ_EMPTY(&r->aio_tailq)) {
+ aio = QTAILQ_FIRST(&r->aio_tailq);
+ assert(aio->aiocb);
+ blk_aio_cancel(aio->aiocb);
+ }
}
if (!nvme_check_cqid(n, sq->cqid)) {
cq = n->cq[sq->cqid];
@@ -923,6 +938,7 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
for (i = 0; i < sq->size; i++) {
sq->io_req[i].sq = sq;
QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
+ QTAILQ_INIT(&(sq->io_req[i].aio_tailq));
}
sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 7a11b0b37317..baedcb226cb1 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -22,14 +22,13 @@ typedef struct NvmeAsyncEvent {
typedef struct NvmeRequest {
struct NvmeSQueue *sq;
struct NvmeNamespace *ns;
- BlockAIOCB *aiocb;
uint16_t status;
NvmeCqe cqe;
NvmeCmd cmd;
- BlockAcctCookie acct;
QEMUSGList qsg;
QEMUIOVector iov;
QTAILQ_ENTRY(NvmeRequest)entry;
+ QTAILQ_HEAD(, NvmeAIO) aio_tailq;
} NvmeRequest;
static inline bool nvme_req_is_write(NvmeRequest *req)
@@ -86,10 +85,13 @@ typedef struct NvmeAIO {
NvmeAIOOp opc;
NvmeRequest *req;
BlockBackend *blk;
+ BlockAcctCookie acct;
+ BlockAIOCB *aiocb;
int64_t offset;
size_t len;
int flags;
void *payload;
+ QTAILQ_ENTRY(NvmeAIO) entry;
} NvmeAIO;
static inline const char *nvme_aio_opc_str(NvmeAIO *aio)
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 11/17] hw/block/nvme: harden cmb access
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (9 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 10/17] hw/block/nvme: support multiple parallel aios per request Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 12/17] hw/block/nvme: add support for scatter gather lists Klaus Jensen
` (6 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
Since the controller has only supported PRPs so far it has not been
required to check the ending address (addr + len - 1) of the CMB access
for validity since it has been guaranteed to be in range of the CMB.
This changes when the controller adds support for SGLs (next patch), so
add that check.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 36ec8cbb1168..6ef4dc762b80 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -143,7 +143,12 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
- if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) {
+ hwaddr hi = addr + size - 1;
+ if (hi < addr) {
+ return 1;
+ }
+
+ if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) {
memcpy(buf, nvme_addr_to_cmb(n, addr), size);
return 0;
}
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 12/17] hw/block/nvme: add support for scatter gather lists
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (10 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 11/17] hw/block/nvme: harden cmb access Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 13/17] hw/block/nvme: add support for sgl bit bucket descriptor Klaus Jensen
` (5 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen, Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
For now, support the Data Block, Segment and Last Segment descriptor
types.
See NVM Express 1.3d, Section 4.4 ("Scatter Gather List (SGL)").
Signed-off-by: Klaus Jensen <klaus.jensen@cnexlabs.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Keith Busch <kbusch@kernel.org>
---
hw/block/nvme.c | 329 ++++++++++++++++++++++++++++++++++--------
hw/block/trace-events | 4 +
include/block/nvme.h | 6 +-
3 files changed, 279 insertions(+), 60 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6ef4dc762b80..9bdcfeb901d9 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -414,13 +414,262 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
return NVME_SUCCESS;
}
-static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
- uint64_t prp1, uint64_t prp2, DMADirection dir,
+/*
+ * Map 'nsgld' data descriptors from 'segment'. The function will subtract the
+ * number of bytes mapped in len.
+ */
+static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
+ QEMUIOVector *iov,
+ NvmeSglDescriptor *segment, uint64_t nsgld,
+ size_t *len, NvmeRequest *req)
+{
+ dma_addr_t addr, trans_len;
+ uint32_t dlen;
+ uint16_t status;
+
+ for (int i = 0; i < nsgld; i++) {
+ uint8_t type = NVME_SGL_TYPE(segment[i].type);
+
+ switch (type) {
+ case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
+ break;
+ case NVME_SGL_DESCR_TYPE_SEGMENT:
+ case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
+ return NVME_INVALID_NUM_SGL_DESCRS | NVME_DNR;
+ default:
+ return NVME_SGL_DESCR_TYPE_INVALID | NVME_DNR;
+ }
+
+ dlen = le32_to_cpu(segment[i].len);
+ if (!dlen) {
+ continue;
+ }
+
+ if (*len == 0) {
+ /*
+ * All data has been mapped, but the SGL contains additional
+ * segments and/or descriptors. The controller might accept
+ * ignoring the rest of the SGL.
+ */
+ uint16_t sgls = le16_to_cpu(n->id_ctrl.sgls);
+ if (sgls & NVME_CTRL_SGLS_EXCESS_LENGTH) {
+ break;
+ }
+
+ trace_pci_nvme_err_invalid_sgl_excess_length(nvme_cid(req));
+ return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
+ }
+
+ trans_len = MIN(*len, dlen);
+ addr = le64_to_cpu(segment[i].addr);
+
+ if (UINT64_MAX - addr < dlen) {
+ return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
+ }
+
+ status = nvme_map_addr(n, qsg, iov, addr, trans_len);
+ if (status) {
+ return status;
+ }
+
+ *len -= trans_len;
+ }
+
+ return NVME_SUCCESS;
+}
+
+static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
+ NvmeSglDescriptor sgl, size_t len,
NvmeRequest *req)
+{
+ /*
+ * Read the segment in chunks of 256 descriptors (one 4k page) to avoid
+ * dynamically allocating a potentially huge SGL. The spec allows the SGL
+ * to be larger (as in number of bytes required to describe the SGL
+ * descriptors and segment chain) than the command transfer size, so it is
+ * not bounded by MDTS.
+ */
+ const int SEG_CHUNK_SIZE = 256;
+
+ NvmeSglDescriptor segment[SEG_CHUNK_SIZE], *sgld, *last_sgld;
+ uint64_t nsgld;
+ uint32_t seg_len;
+ uint16_t status;
+ bool sgl_in_cmb = false;
+ hwaddr addr;
+ int ret;
+
+ sgld = &sgl;
+ addr = le64_to_cpu(sgl.addr);
+
+ trace_pci_nvme_map_sgl(nvme_cid(req), NVME_SGL_TYPE(sgl.type), len);
+
+ /*
+ * If the entire transfer can be described with a single data block it can
+ * be mapped directly.
+ */
+ if (NVME_SGL_TYPE(sgl.type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
+ status = nvme_map_sgl_data(n, qsg, iov, sgld, 1, &len, req);
+ if (status) {
+ goto unmap;
+ }
+
+ goto out;
+ }
+
+ /*
+ * If the segment is located in the CMB, the submission queue of the
+ * request must also reside there.
+ */
+ if (nvme_addr_is_cmb(n, addr)) {
+ if (!nvme_addr_is_cmb(n, req->sq->dma_addr)) {
+ return NVME_INVALID_USE_OF_CMB | NVME_DNR;
+ }
+
+ sgl_in_cmb = true;
+ }
+
+ for (;;) {
+ switch (NVME_SGL_TYPE(sgld->type)) {
+ case NVME_SGL_DESCR_TYPE_SEGMENT:
+ case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
+ break;
+ default:
+ return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
+ }
+
+ seg_len = le32_to_cpu(sgld->len);
+
+ /* check the length of the (Last) Segment descriptor */
+ if (!seg_len || seg_len & 0xf) {
+ return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
+ }
+
+ if (UINT64_MAX - addr < seg_len) {
+ return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
+ }
+
+ nsgld = seg_len / sizeof(NvmeSglDescriptor);
+
+ while (nsgld > SEG_CHUNK_SIZE) {
+ if (nvme_addr_read(n, addr, segment, sizeof(segment))) {
+ trace_pci_nvme_err_addr_read(addr);
+ status = NVME_DATA_TRANSFER_ERROR;
+ goto unmap;
+ }
+
+ status = nvme_map_sgl_data(n, qsg, iov, segment, SEG_CHUNK_SIZE,
+ &len, req);
+ if (status) {
+ goto unmap;
+ }
+
+ nsgld -= SEG_CHUNK_SIZE;
+ addr += SEG_CHUNK_SIZE * sizeof(NvmeSglDescriptor);
+ }
+
+ ret = nvme_addr_read(n, addr, segment, nsgld *
+ sizeof(NvmeSglDescriptor));
+ if (ret) {
+ trace_pci_nvme_err_addr_read(addr);
+ status = NVME_DATA_TRANSFER_ERROR;
+ goto unmap;
+ }
+
+ last_sgld = &segment[nsgld - 1];
+
+ /* if the segment ends with a Data Block, then we are done */
+ if (NVME_SGL_TYPE(last_sgld->type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
+ status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld, &len, req);
+ if (status) {
+ goto unmap;
+ }
+
+ goto out;
+ }
+
+ /*
+ * If the last descriptor was not a Data Block, then the current
+ * segment must not be a Last Segment.
+ */
+ if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) {
+ status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
+ goto unmap;
+ }
+
+ sgld = last_sgld;
+ addr = le64_to_cpu(sgld->addr);
+
+ /*
+ * Do not map the last descriptor; it will be a Segment or Last Segment
+ * descriptor and is handled by the next iteration.
+ */
+ status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld - 1, &len, req);
+ if (status) {
+ goto unmap;
+ }
+
+ /*
+ * If the next segment is in the CMB, make sure that the sgl was
+ * already located there.
+ */
+ if (sgl_in_cmb != nvme_addr_is_cmb(n, addr)) {
+ status = NVME_INVALID_USE_OF_CMB | NVME_DNR;
+ goto unmap;
+ }
+ }
+
+out:
+ /* if there is any residual left in len, the SGL was too short */
+ if (len) {
+ status = NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
+ goto unmap;
+ }
+
+ return NVME_SUCCESS;
+
+unmap:
+ if (iov->iov) {
+ qemu_iovec_destroy(iov);
+ }
+
+ if (qsg->sg) {
+ qemu_sglist_destroy(qsg);
+ }
+
+ return status;
+}
+
+static uint16_t nvme_map_dptr(NvmeCtrl *n, size_t len, NvmeRequest *req)
+{
+ uint64_t prp1, prp2;
+
+ switch (NVME_CMD_FLAGS_PSDT(req->cmd.flags)) {
+ case NVME_PSDT_PRP:
+ prp1 = le64_to_cpu(req->cmd.dptr.prp1);
+ prp2 = le64_to_cpu(req->cmd.dptr.prp2);
+
+ return nvme_map_prp(n, prp1, prp2, len, req);
+ case NVME_PSDT_SGL_MPTR_CONTIGUOUS:
+ case NVME_PSDT_SGL_MPTR_SGL:
+ /* SGLs shall not be used for Admin commands in NVMe over PCIe */
+ if (!req->sq->sqid) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
+ return nvme_map_sgl(n, &req->qsg, &req->iov, req->cmd.dptr.sgl, len,
+ req);
+ default:
+ return NVME_INVALID_FIELD;
+ }
+}
+
+static uint16_t nvme_dma(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
+ DMADirection dir, NvmeRequest *req)
{
uint16_t status = NVME_SUCCESS;
- status = nvme_map_prp(n, prp1, prp2, len, req);
+ status = nvme_map_dptr(n, len, req);
if (status) {
return status;
}
@@ -459,15 +708,6 @@ static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
return status;
}
-static uint16_t nvme_map_dptr(NvmeCtrl *n, size_t len, NvmeRequest *req)
-{
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
-
- return nvme_map_prp(n, prp1, prp2, len, req);
-}
-
static void nvme_post_cqes(void *opaque)
{
NvmeCQueue *cq = opaque;
@@ -994,10 +1234,7 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req)
static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
uint64_t off, NvmeRequest *req)
{
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
- uint32_t nsid = le32_to_cpu(cmd->nsid);
+ uint32_t nsid = le32_to_cpu(req->cmd.nsid);
uint32_t trans_len;
time_t current_ms;
@@ -1046,17 +1283,14 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
nvme_clear_events(n, NVME_AER_TYPE_SMART);
}
- return nvme_dma_prp(n, (uint8_t *) &smart + off, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *) &smart + off, trans_len,
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
NvmeRequest *req)
{
uint32_t trans_len;
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
NvmeFwSlotInfoLog fw_log = {
.afi = 0x1,
};
@@ -1069,17 +1303,14 @@ static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
trans_len = MIN(sizeof(fw_log) - off, buf_len);
- return nvme_dma_prp(n, (uint8_t *) &fw_log + off, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *) &fw_log + off, trans_len,
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
uint64_t off, NvmeRequest *req)
{
uint32_t trans_len;
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
NvmeErrorLog errlog;
if (!rae) {
@@ -1094,8 +1325,8 @@ static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
trans_len = MIN(sizeof(errlog) - off, buf_len);
- return nvme_dma_prp(n, (uint8_t *)&errlog, trans_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *)&errlog, trans_len,
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
@@ -1255,14 +1486,10 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
{
- NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
- uint64_t prp1 = le64_to_cpu(c->prp1);
- uint64_t prp2 = le64_to_cpu(c->prp2);
-
trace_pci_nvme_identify_ctrl();
- return nvme_dma_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
@@ -1270,8 +1497,6 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid);
- uint64_t prp1 = le64_to_cpu(c->prp1);
- uint64_t prp2 = le64_to_cpu(c->prp2);
trace_pci_nvme_identify_ns(nsid);
@@ -1282,8 +1507,8 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
ns = &n->namespaces[nsid - 1];
- return nvme_dma_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
@@ -1291,8 +1516,6 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
static const int data_len = NVME_IDENTIFY_DATA_SIZE;
uint32_t min_nsid = le32_to_cpu(c->nsid);
- uint64_t prp1 = le64_to_cpu(c->prp1);
- uint64_t prp2 = le64_to_cpu(c->prp2);
uint32_t *list;
uint16_t ret;
int i, j = 0;
@@ -1319,8 +1542,8 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
break;
}
}
- ret = nvme_dma_prp(n, (uint8_t *)list, data_len, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE, req);
+ ret = nvme_dma(n, (uint8_t *)list, data_len, DMA_DIRECTION_FROM_DEVICE,
+ req);
g_free(list);
return ret;
}
@@ -1329,8 +1552,6 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
{
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid);
- uint64_t prp1 = le64_to_cpu(c->prp1);
- uint64_t prp2 = le64_to_cpu(c->prp2);
uint8_t list[NVME_IDENTIFY_DATA_SIZE];
@@ -1362,8 +1583,8 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
ns_descrs->uuid.hdr.nidl = NVME_NIDT_UUID_LEN;
stl_be_p(&ns_descrs->uuid.v, nsid);
- return nvme_dma_prp(n, list, NVME_IDENTIFY_DATA_SIZE, prp1, prp2,
- DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, list, NVME_IDENTIFY_DATA_SIZE,
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
@@ -1439,14 +1660,10 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
{
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
-
uint64_t timestamp = nvme_get_timestamp(n);
- return nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
- prp2, DMA_DIRECTION_FROM_DEVICE, req);
+ return nvme_dma(n, (uint8_t *)×tamp, sizeof(timestamp),
+ DMA_DIRECTION_FROM_DEVICE, req);
}
static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
@@ -1575,12 +1792,9 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
{
uint16_t ret;
uint64_t timestamp;
- NvmeCmd *cmd = &req->cmd;
- uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
- uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
- ret = nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
- prp2, DMA_DIRECTION_TO_DEVICE, req);
+ ret = nvme_dma(n, (uint8_t *)×tamp, sizeof(timestamp),
+ DMA_DIRECTION_TO_DEVICE, req);
if (ret != NVME_SUCCESS) {
return ret;
}
@@ -2507,6 +2721,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->nn = cpu_to_le32(n->num_namespaces);
id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
NVME_ONCS_FEATURES);
+ id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN);
subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s", n->params.serial);
strpadcpy((char *)id->subnqn, sizeof(id->subnqn), subnqn, '\0');
diff --git a/hw/block/trace-events b/hw/block/trace-events
index fb3bf1be5e07..7fe119bd625c 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -36,6 +36,7 @@ pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2
pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
+pci_nvme_map_sgl(uint16_t cid, uint8_t typ, uint64_t len) "cid %"PRIu16" type 0x%"PRIx8" len %"PRIu64""
pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" \"%s\" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
@@ -91,6 +92,9 @@ pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu"
pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64""
pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64""
pci_nvme_err_aio(uint16_t cid, void *aio, const char *blkname, uint64_t offset, const char *opc, void *req, uint16_t status) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" opc \"%s\" req %p status 0x%"PRIx16""
+pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8""
+pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8""
+pci_nvme_err_invalid_sgl_excess_length(uint16_t cid) "cid %"PRIu16""
pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64""
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
diff --git a/include/block/nvme.h b/include/block/nvme.h
index c8d0a3473f0d..7eba658073f5 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -412,9 +412,9 @@ typedef union NvmeCmdDptr {
} NvmeCmdDptr;
enum NvmePsdt {
- PSDT_PRP = 0x0,
- PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
- PSDT_SGL_MPTR_SGL = 0x2,
+ NVME_PSDT_PRP = 0x0,
+ NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
+ NVME_PSDT_SGL_MPTR_SGL = 0x2,
};
typedef struct QEMU_PACKED NvmeCmd {
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 13/17] hw/block/nvme: add support for sgl bit bucket descriptor
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (11 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 12/17] hw/block/nvme: add support for scatter gather lists Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 14/17] hw/block/nvme: refactor identify active namespace id list Klaus Jensen
` (4 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Gollu Appalanaidu, Max Reitz, Keith Busch,
Klaus Jensen
From: Gollu Appalanaidu <anaidu.gollu@samsung.com>
This adds support for SGL descriptor type 0x1 (bit bucket descriptor).
See the NVM Express v1.3d specification, Section 4.4 ("Scatter Gather
List (SGL)").
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 33 +++++++++++++++++++++++++++------
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 9bdcfeb901d9..6340af226341 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -431,6 +431,10 @@ static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
uint8_t type = NVME_SGL_TYPE(segment[i].type);
switch (type) {
+ case NVME_SGL_DESCR_TYPE_BIT_BUCKET:
+ if (req->cmd.opcode == NVME_CMD_WRITE) {
+ continue;
+ }
case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
break;
case NVME_SGL_DESCR_TYPE_SEGMENT:
@@ -441,6 +445,7 @@ static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
}
dlen = le32_to_cpu(segment[i].len);
+
if (!dlen) {
continue;
}
@@ -461,6 +466,11 @@ static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
}
trans_len = MIN(*len, dlen);
+
+ if (type == NVME_SGL_DESCR_TYPE_BIT_BUCKET) {
+ goto next;
+ }
+
addr = le64_to_cpu(segment[i].addr);
if (UINT64_MAX - addr < dlen) {
@@ -472,6 +482,7 @@ static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
return status;
}
+next:
*len -= trans_len;
}
@@ -541,7 +552,8 @@ static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
seg_len = le32_to_cpu(sgld->len);
/* check the length of the (Last) Segment descriptor */
- if (!seg_len || seg_len & 0xf) {
+ if ((!seg_len || seg_len & 0xf) &&
+ (NVME_SGL_TYPE(sgld->type) != NVME_SGL_DESCR_TYPE_BIT_BUCKET)) {
return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
}
@@ -578,19 +590,27 @@ static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
last_sgld = &segment[nsgld - 1];
- /* if the segment ends with a Data Block, then we are done */
- if (NVME_SGL_TYPE(last_sgld->type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
+ /*
+ * If the segment ends with a Data Block or Bit Bucket Descriptor Type,
+ * then we are done.
+ */
+ switch (NVME_SGL_TYPE(last_sgld->type)) {
+ case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
+ case NVME_SGL_DESCR_TYPE_BIT_BUCKET:
status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld, &len, req);
if (status) {
goto unmap;
}
goto out;
+
+ default:
+ break;
}
/*
- * If the last descriptor was not a Data Block, then the current
- * segment must not be a Last Segment.
+ * If the last descriptor was not a Data Block or Bit Bucket, then the
+ * current segment must not be a Last Segment.
*/
if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) {
status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
@@ -2721,7 +2741,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->nn = cpu_to_le32(n->num_namespaces);
id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
NVME_ONCS_FEATURES);
- id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN);
+ id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN |
+ NVME_CTRL_SGLS_BITBUCKET);
subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s", n->params.serial);
strpadcpy((char *)id->subnqn, sizeof(id->subnqn), subnqn, '\0');
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 14/17] hw/block/nvme: refactor identify active namespace id list
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (12 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 13/17] hw/block/nvme: add support for sgl bit bucket descriptor Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 15/17] hw/block/nvme: support multiple namespaces Klaus Jensen
` (3 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen,
Maxim Levitsky
From: Klaus Jensen <k.jensen@samsung.com>
Prepare to support inactive namespaces.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
hw/block/nvme.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 6340af226341..4155cb797856 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -1538,7 +1538,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
uint32_t min_nsid = le32_to_cpu(c->nsid);
uint32_t *list;
uint16_t ret;
- int i, j = 0;
+ int j = 0;
trace_pci_nvme_identify_nslist(min_nsid);
@@ -1553,11 +1553,11 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
}
list = g_malloc0(data_len);
- for (i = 0; i < n->num_namespaces; i++) {
- if (i < min_nsid) {
+ for (int i = 1; i <= n->num_namespaces; i++) {
+ if (i <= min_nsid) {
continue;
}
- list[j++] = cpu_to_le32(i + 1);
+ list[j++] = cpu_to_le32(i);
if (j == data_len / sizeof(uint32_t)) {
break;
}
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 15/17] hw/block/nvme: support multiple namespaces
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (13 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 14/17] hw/block/nvme: refactor identify active namespace id list Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 16/17] pci: allocate pci id for nvme Klaus Jensen
` (2 subsequent siblings)
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Minwoo Im, Klaus Jensen,
Klaus Jensen
From: Klaus Jensen <k.jensen@samsung.com>
This adds support for multiple namespaces by introducing a new 'nvme-ns'
device model. The nvme device creates a bus named from the device name
('id'). The nvme-ns devices then connect to this and registers
themselves with the nvme device.
This changes how an nvme device is created. Example with two namespaces:
-drive file=nvme0n1.img,if=none,id=disk1
-drive file=nvme0n2.img,if=none,id=disk2
-device nvme,serial=deadbeef,id=nvme0
-device nvme-ns,drive=disk1,bus=nvme0,nsid=1
-device nvme-ns,drive=disk2,bus=nvme0,nsid=2
The drive property is kept on the nvme device to keep the change
backward compatible, but the property is now optional. Specifying a
drive for the nvme device will always create the namespace with nsid 1.
Signed-off-by: Klaus Jensen <klaus.jensen@cnexlabs.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
---
hw/block/meson.build | 2 +-
hw/block/nvme-ns.c | 185 +++++++++++++++++++++++++++++++
hw/block/nvme-ns.h | 74 +++++++++++++
hw/block/nvme.c | 247 +++++++++++++++++++++++++++---------------
hw/block/nvme.h | 46 ++++----
hw/block/trace-events | 8 +-
6 files changed, 447 insertions(+), 115 deletions(-)
create mode 100644 hw/block/nvme-ns.c
create mode 100644 hw/block/nvme-ns.h
diff --git a/hw/block/meson.build b/hw/block/meson.build
index 78cad8f7cba1..602ca6c8541d 100644
--- a/hw/block/meson.build
+++ b/hw/block/meson.build
@@ -13,7 +13,7 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('tc58128.c'))
-softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c'))
+softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c'))
specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c'))
specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk.c'))
diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
new file mode 100644
index 000000000000..0d65b0998617
--- /dev/null
+++ b/hw/block/nvme-ns.c
@@ -0,0 +1,185 @@
+/*
+ * QEMU NVM Express Virtual Namespace
+ *
+ * Copyright (c) 2019 CNEX Labs
+ * Copyright (c) 2020 Samsung Electronics
+ *
+ * Authors:
+ * Klaus Jensen <k.jensen@samsung.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See the
+ * COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qemu/log.h"
+#include "hw/block/block.h"
+#include "hw/pci/pci.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/block-backend.h"
+#include "qapi/error.h"
+
+#include "hw/qdev-properties.h"
+#include "hw/qdev-core.h"
+
+#include "nvme.h"
+#include "nvme-ns.h"
+
+static void nvme_ns_init(NvmeNamespace *ns)
+{
+ NvmeIdNs *id_ns = &ns->id_ns;
+
+ if (blk_get_flags(ns->blk) & BDRV_O_UNMAP) {
+ ns->id_ns.dlfeat = 0x9;
+ }
+
+ id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
+
+ id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns));
+
+ /* no thin provisioning */
+ id_ns->ncap = id_ns->nsze;
+ id_ns->nuse = id_ns->ncap;
+}
+
+static int nvme_ns_init_blk(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
+{
+ uint64_t perm, shared_perm;
+
+ Error *local_err = NULL;
+ int ret;
+
+ perm = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE;
+ shared_perm = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE_UNCHANGED |
+ BLK_PERM_GRAPH_MOD;
+
+ ret = blk_set_perm(ns->blk, perm, shared_perm, &local_err);
+ if (ret) {
+ error_propagate_prepend(errp, local_err,
+ "could not set block permissions: ");
+ return ret;
+ }
+
+ ns->size = blk_getlength(ns->blk);
+ if (ns->size < 0) {
+ error_setg_errno(errp, -ns->size, "could not get blockdev size");
+ return -1;
+ }
+
+ switch (n->conf.wce) {
+ case ON_OFF_AUTO_ON:
+ n->features.vwc = 1;
+ break;
+ case ON_OFF_AUTO_OFF:
+ n->features.vwc = 0;
+ break;
+ case ON_OFF_AUTO_AUTO:
+ n->features.vwc = blk_enable_write_cache(ns->blk);
+ break;
+ default:
+ abort();
+ }
+
+ blk_set_enable_write_cache(ns->blk, n->features.vwc);
+
+ return 0;
+}
+
+static int nvme_ns_check_constraints(NvmeNamespace *ns, Error **errp)
+{
+ if (!ns->blk) {
+ error_setg(errp, "block backend not configured");
+ return -1;
+ }
+
+ return 0;
+}
+
+int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
+{
+ if (nvme_ns_check_constraints(ns, errp)) {
+ return -1;
+ }
+
+ if (nvme_ns_init_blk(n, ns, errp)) {
+ return -1;
+ }
+
+ nvme_ns_init(ns);
+ if (nvme_register_namespace(n, ns, errp)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+void nvme_ns_drain(NvmeNamespace *ns)
+{
+ blk_drain(ns->blk);
+}
+
+void nvme_ns_flush(NvmeNamespace *ns)
+{
+ blk_flush(ns->blk);
+}
+
+static void nvme_ns_realize(DeviceState *dev, Error **errp)
+{
+ NvmeNamespace *ns = NVME_NS(dev);
+ BusState *s = qdev_get_parent_bus(dev);
+ NvmeCtrl *n = NVME(s->parent);
+ Error *local_err = NULL;
+
+ if (nvme_ns_setup(n, ns, &local_err)) {
+ error_propagate_prepend(errp, local_err,
+ "could not setup namespace: ");
+ return;
+ }
+}
+
+static Property nvme_ns_props[] = {
+ DEFINE_PROP_DRIVE("drive", NvmeNamespace, blk),
+ DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nvme_ns_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
+
+ dc->bus_type = TYPE_NVME_BUS;
+ dc->realize = nvme_ns_realize;
+ device_class_set_props(dc, nvme_ns_props);
+ dc->desc = "Virtual NVMe namespace";
+}
+
+static void nvme_ns_instance_init(Object *obj)
+{
+ NvmeNamespace *ns = NVME_NS(obj);
+ char *bootindex = g_strdup_printf("/namespace@%d,0", ns->params.nsid);
+
+ device_add_bootindex_property(obj, &ns->bootindex, "bootindex",
+ bootindex, DEVICE(obj));
+
+ g_free(bootindex);
+}
+
+static const TypeInfo nvme_ns_info = {
+ .name = TYPE_NVME_NS,
+ .parent = TYPE_DEVICE,
+ .class_init = nvme_ns_class_init,
+ .instance_size = sizeof(NvmeNamespace),
+ .instance_init = nvme_ns_instance_init,
+};
+
+static void nvme_ns_register_types(void)
+{
+ type_register_static(&nvme_ns_info);
+}
+
+type_init(nvme_ns_register_types)
diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h
new file mode 100644
index 000000000000..4659e566f443
--- /dev/null
+++ b/hw/block/nvme-ns.h
@@ -0,0 +1,74 @@
+/*
+ * QEMU NVM Express Virtual Namespace
+ *
+ * Copyright (c) 2019 CNEX Labs
+ * Copyright (c) 2020 Samsung Electronics
+ *
+ * Authors:
+ * Klaus Jensen <k.jensen@samsung.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See the
+ * COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef NVME_NS_H
+#define NVME_NS_H
+
+#define TYPE_NVME_NS "nvme-ns"
+#define NVME_NS(obj) \
+ OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS)
+
+typedef struct NvmeNamespaceParams {
+ uint32_t nsid;
+} NvmeNamespaceParams;
+
+typedef struct NvmeNamespace {
+ DeviceState parent_obj;
+ BlockBackend *blk;
+ int32_t bootindex;
+ int64_t size;
+ NvmeIdNs id_ns;
+
+ NvmeNamespaceParams params;
+} NvmeNamespace;
+
+static inline uint32_t nvme_nsid(NvmeNamespace *ns)
+{
+ if (ns) {
+ return ns->params.nsid;
+ }
+
+ return -1;
+}
+
+static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
+{
+ NvmeIdNs *id_ns = &ns->id_ns;
+ return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
+}
+
+static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
+{
+ return nvme_ns_lbaf(ns)->ds;
+}
+
+/* calculate the number of LBAs that the namespace can accomodate */
+static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns)
+{
+ return ns->size >> nvme_ns_lbads(ns);
+}
+
+/* convert an LBA to the equivalent in bytes */
+static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
+{
+ return lba << nvme_ns_lbads(ns);
+}
+
+typedef struct NvmeCtrl NvmeCtrl;
+
+int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
+void nvme_ns_drain(NvmeNamespace *ns);
+void nvme_ns_flush(NvmeNamespace *ns);
+
+#endif /* NVME_NS_H */
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 4155cb797856..453d3a89d475 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -17,12 +17,13 @@
/**
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
- * -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
+ * -device nvme,serial=<serial>,id=<bus_name>, \
* cmb_size_mb=<cmb_size_mb[optional]>, \
* [pmrdev=<mem_backend_file_id>,] \
* max_ioqpairs=<N[optional]>, \
* aerl=<N[optional]>, aer_max_queued=<N[optional]>, \
* mdts=<N[optional]>
+ * -device nvme-ns,drive=<drive_id>,bus=bus_name,nsid=<nsid>
*
* Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
* offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
@@ -69,6 +70,7 @@
#include "qemu/cutils.h"
#include "trace.h"
#include "nvme.h"
+#include "nvme-ns.h"
#define NVME_MAX_IOQPAIRS 0xffff
#define NVME_DB_SIZE 4
@@ -156,6 +158,11 @@ static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
return pci_dma_read(&n->parent_obj, addr, buf, size);
}
+static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsid)
+{
+ return nsid && (nsid == NVME_NSID_BROADCAST || nsid <= n->num_namespaces);
+}
+
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{
return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1;
@@ -1023,7 +1030,9 @@ static void nvme_aio_cb(void *opaque, int ret)
static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
{
- return nvme_aio_add(req, nvme_aio_new(NVME_AIO_OPC_FLUSH, n->conf.blk, 0));
+ NvmeNamespace *ns = req->ns;
+
+ return nvme_aio_add(req, nvme_aio_new(NVME_AIO_OPC_FLUSH, ns->blk, 0));
}
static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
@@ -1037,7 +1046,7 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
uint32_t count = nvme_l2b(ns, nlb);
uint16_t status;
- trace_pci_nvme_write_zeroes(nvme_cid(req), slba, nlb);
+ trace_pci_nvme_write_zeroes(nvme_cid(req), nvme_nsid(ns), slba, nlb);
status = nvme_check_bounds(n, ns, slba, nlb);
if (status) {
@@ -1045,7 +1054,7 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
return status;
}
- aio = nvme_aio_new(NVME_AIO_OPC_WRITE_ZEROES, n->conf.blk, offset);
+ aio = nvme_aio_new(NVME_AIO_OPC_WRITE_ZEROES, ns->blk, offset);
aio->len = count;
return nvme_aio_add(req, aio);
@@ -1064,8 +1073,8 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
bool is_write = nvme_req_is_write(req);
uint16_t status;
- trace_pci_nvme_rw(nvme_cid(req), nvme_io_opc_str(rw->opcode), nlb,
- data_size, slba);
+ trace_pci_nvme_rw(nvme_cid(req), nvme_io_opc_str(rw->opcode),
+ nvme_nsid(ns), nlb, data_size, slba);
status = nvme_check_mdts(n, data_size);
if (status) {
@@ -1085,7 +1094,7 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
}
aio = nvme_aio_new(is_write ? NVME_AIO_OPC_WRITE : NVME_AIO_OPC_READ,
- n->conf.blk, data_offset);
+ ns->blk, data_offset);
if (req->qsg.sg) {
aio->payload = &req->qsg;
@@ -1099,7 +1108,7 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req)
return nvme_aio_add(req, aio);
invalid:
- block_acct_invalid(blk_get_stats(n->conf.blk),
+ block_acct_invalid(blk_get_stats(ns->blk),
is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ);
return status;
}
@@ -1111,12 +1120,15 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req),
req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode));
- if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
- trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
+ if (!nvme_nsid_valid(n, nsid)) {
return NVME_INVALID_NSID | NVME_DNR;
}
- req->ns = &n->namespaces[nsid - 1];
+ req->ns = nvme_ns(n, nsid);
+ if (unlikely(!req->ns)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
switch (req->cmd.opcode) {
case NVME_CMD_FLUSH:
return nvme_flush(n, req);
@@ -1261,18 +1273,24 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
uint64_t units_read = 0, units_written = 0;
uint64_t read_commands = 0, write_commands = 0;
NvmeSmartLog smart;
- BlockAcctStats *s;
if (nsid && nsid != 0xffffffff) {
return NVME_INVALID_FIELD | NVME_DNR;
}
- s = blk_get_stats(n->conf.blk);
+ for (int i = 1; i <= n->num_namespaces; i++) {
+ NvmeNamespace *ns = nvme_ns(n, i);
+ if (!ns) {
+ continue;
+ }
- units_read = s->nr_bytes[BLOCK_ACCT_READ] >> BDRV_SECTOR_BITS;
- units_written = s->nr_bytes[BLOCK_ACCT_WRITE] >> BDRV_SECTOR_BITS;
- read_commands = s->nr_ops[BLOCK_ACCT_READ];
- write_commands = s->nr_ops[BLOCK_ACCT_WRITE];
+ BlockAcctStats *s = blk_get_stats(ns->blk);
+
+ units_read += s->nr_bytes[BLOCK_ACCT_READ] >> BDRV_SECTOR_BITS;
+ units_written += s->nr_bytes[BLOCK_ACCT_WRITE] >> BDRV_SECTOR_BITS;
+ read_commands += s->nr_ops[BLOCK_ACCT_READ];
+ write_commands += s->nr_ops[BLOCK_ACCT_WRITE];
+ }
if (off > sizeof(smart)) {
return NVME_INVALID_FIELD | NVME_DNR;
@@ -1516,18 +1534,23 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
{
NvmeNamespace *ns;
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
+ NvmeIdNs *id_ns, inactive = { 0 };
uint32_t nsid = le32_to_cpu(c->nsid);
trace_pci_nvme_identify_ns(nsid);
- if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
- trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
+ if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
return NVME_INVALID_NSID | NVME_DNR;
}
- ns = &n->namespaces[nsid - 1];
+ ns = nvme_ns(n, nsid);
+ if (unlikely(!ns)) {
+ id_ns = &inactive;
+ } else {
+ id_ns = &ns->id_ns;
+ }
- return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
+ return nvme_dma(n, (uint8_t *)id_ns, sizeof(NvmeIdNs),
DMA_DIRECTION_FROM_DEVICE, req);
}
@@ -1554,7 +1577,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
list = g_malloc0(data_len);
for (int i = 1; i <= n->num_namespaces; i++) {
- if (i <= min_nsid) {
+ if (i <= min_nsid || !nvme_ns(n, i)) {
continue;
}
list[j++] = cpu_to_le32(i);
@@ -1572,7 +1595,6 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
{
NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
uint32_t nsid = le32_to_cpu(c->nsid);
-
uint8_t list[NVME_IDENTIFY_DATA_SIZE];
struct data {
@@ -1586,11 +1608,14 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
trace_pci_nvme_identify_ns_descr_list(nsid);
- if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
- trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces);
+ if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
return NVME_INVALID_NSID | NVME_DNR;
}
+ if (unlikely(!nvme_ns(n, nsid))) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
memset(list, 0x0, sizeof(list));
/*
@@ -1708,7 +1733,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
}
if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
- if (!nsid || nsid > n->num_namespaces) {
+ if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) {
/*
* The Reservation Notification Mask and Reservation Persistence
* features require a status code of Invalid Field in Command when
@@ -1718,6 +1743,10 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
*/
return NVME_INVALID_NSID | NVME_DNR;
}
+
+ if (!nvme_ns(n, nsid)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
}
switch (sel) {
@@ -1755,7 +1784,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR;
case NVME_VOLATILE_WRITE_CACHE:
- result = blk_enable_write_cache(n->conf.blk);
+ result = n->features.vwc;
trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
goto out;
case NVME_ASYNCHRONOUS_EVENT_CONF:
@@ -1826,6 +1855,8 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
{
+ NvmeNamespace *ns;
+
NvmeCmd *cmd = &req->cmd;
uint32_t dw10 = le32_to_cpu(cmd->cdw10);
uint32_t dw11 = le32_to_cpu(cmd->cdw11);
@@ -1844,12 +1875,18 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
}
if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) {
- if (!nsid || (nsid != NVME_NSID_BROADCAST &&
- nsid > n->num_namespaces)) {
- return NVME_INVALID_NSID | NVME_DNR;
+ if (nsid != NVME_NSID_BROADCAST) {
+ if (!nvme_nsid_valid(n, nsid)) {
+ return NVME_INVALID_NSID | NVME_DNR;
+ }
+
+ ns = nvme_ns(n, nsid);
+ if (unlikely(!ns)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
}
} else if (nsid && nsid != NVME_NSID_BROADCAST) {
- if (nsid > n->num_namespaces) {
+ if (!nvme_nsid_valid(n, nsid)) {
return NVME_INVALID_NSID | NVME_DNR;
}
@@ -1887,12 +1924,23 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
break;
case NVME_VOLATILE_WRITE_CACHE:
- if (!(dw11 & 0x1) && blk_enable_write_cache(n->conf.blk)) {
- blk_flush(n->conf.blk);
+ n->features.vwc = dw11 & 0x1;
+
+ for (int i = 1; i <= n->num_namespaces; i++) {
+ ns = nvme_ns(n, i);
+ if (!ns) {
+ continue;
+ }
+
+ if (!(dw11 & 0x1) && blk_enable_write_cache(ns->blk)) {
+ blk_flush(ns->blk);
+ }
+
+ blk_set_enable_write_cache(ns->blk, dw11 & 1);
}
- blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
break;
+
case NVME_NUMBER_OF_QUEUES:
if (n->qs_created) {
return NVME_CMD_SEQ_ERROR | NVME_DNR;
@@ -2014,9 +2062,17 @@ static void nvme_process_sq(void *opaque)
static void nvme_clear_ctrl(NvmeCtrl *n)
{
+ NvmeNamespace *ns;
int i;
- blk_drain(n->conf.blk);
+ for (i = 1; i <= n->num_namespaces; i++) {
+ ns = nvme_ns(n, i);
+ if (!ns) {
+ continue;
+ }
+
+ nvme_ns_drain(ns);
+ }
for (i = 0; i < n->params.max_ioqpairs + 1; i++) {
if (n->sq[i] != NULL) {
@@ -2039,7 +2095,15 @@ static void nvme_clear_ctrl(NvmeCtrl *n)
n->outstanding_aers = 0;
n->qs_created = false;
- blk_flush(n->conf.blk);
+ for (i = 1; i <= n->num_namespaces; i++) {
+ ns = nvme_ns(n, i);
+ if (!ns) {
+ continue;
+ }
+
+ nvme_ns_flush(ns);
+ }
+
n->bar.cc = 0;
}
@@ -2517,6 +2581,11 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
params->max_ioqpairs = params->num_queues - 1;
}
+ if (n->namespace.blk) {
+ warn_report("drive property is deprecated; "
+ "please use an nvme-ns device instead");
+ }
+
if (params->max_ioqpairs < 1 ||
params->max_ioqpairs > NVME_MAX_IOQPAIRS) {
error_setg(errp, "max_ioqpairs must be between 1 and %d",
@@ -2531,11 +2600,6 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
return;
}
- if (!n->conf.blk) {
- error_setg(errp, "drive property not set");
- return;
- }
-
if (!params->serial) {
error_setg(errp, "serial property not set");
return;
@@ -2559,11 +2623,10 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
static void nvme_init_state(NvmeCtrl *n)
{
- n->num_namespaces = 1;
+ n->num_namespaces = NVME_MAX_NAMESPACES;
/* add one to max_ioqpairs to account for the admin queue pair */
n->reg_size = pow2ceil(sizeof(NvmeBar) +
2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE);
- n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1);
n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1);
n->temperature = NVME_TEMPERATURE;
@@ -2572,34 +2635,41 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
}
-static void nvme_init_blk(NvmeCtrl *n, Error **errp)
+int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
{
- if (!blkconf_blocksizes(&n->conf, errp)) {
- return;
- }
- blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
- false, errp);
-}
+ uint32_t nsid = nvme_nsid(ns);
-static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
-{
- int64_t bs_size;
- NvmeIdNs *id_ns = &ns->id_ns;
-
- bs_size = blk_getlength(n->conf.blk);
- if (bs_size < 0) {
- error_setg_errno(errp, -bs_size, "could not get backing file size");
- return;
+ if (nsid > NVME_MAX_NAMESPACES) {
+ error_setg(errp, "invalid namespace id (must be between 0 and %d)",
+ NVME_MAX_NAMESPACES);
+ return -1;
}
- n->ns_size = bs_size;
+ if (!nsid) {
+ for (int i = 1; i <= n->num_namespaces; i++) {
+ NvmeNamespace *ns = nvme_ns(n, i);
+ if (!ns) {
+ nsid = i;
+ break;
+ }
+ }
- id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
- id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(n, ns));
+ if (!nsid) {
+ error_setg(errp, "no free namespace id");
+ return -1;
+ }
+ } else {
+ if (n->namespaces[nsid - 1]) {
+ error_setg(errp, "namespace id '%d' is already in use", nsid);
+ return -1;
+ }
+ }
- /* no thin provisioning */
- id_ns->ncap = id_ns->nsze;
- id_ns->nuse = id_ns->ncap;
+ trace_pci_nvme_register_namespace(nsid);
+
+ n->namespaces[nsid - 1] = ns;
+
+ return 0;
}
static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
@@ -2741,6 +2811,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->nn = cpu_to_le32(n->num_namespaces);
id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
NVME_ONCS_FEATURES);
+
+ id->vwc = 0x1;
id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN |
NVME_CTRL_SGLS_BITBUCKET);
@@ -2751,9 +2823,6 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->psd[0].mp = cpu_to_le16(0x9c4);
id->psd[0].enlat = cpu_to_le32(0x10);
id->psd[0].exlat = cpu_to_le32(0x4);
- if (blk_enable_write_cache(n->conf.blk)) {
- id->vwc = 1;
- }
n->bar.cap = 0;
NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
@@ -2769,23 +2838,19 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
static void nvme_realize(PCIDevice *pci_dev, Error **errp)
{
NvmeCtrl *n = NVME(pci_dev);
+ NvmeNamespace *ns;
Error *local_err = NULL;
- int i;
-
nvme_check_constraints(n, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- nvme_init_state(n);
- nvme_init_blk(n, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
+ qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
+ &pci_dev->qdev, n->parent_obj.qdev.id);
+ nvme_init_state(n);
nvme_init_pci(n, pci_dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -2794,10 +2859,12 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
nvme_init_ctrl(n, pci_dev);
- for (i = 0; i < n->num_namespaces; i++) {
- nvme_init_namespace(n, &n->namespaces[i], &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ /* setup a namespace if the controller drive property was given */
+ if (n->namespace.blk) {
+ ns = &n->namespace;
+ ns->params.nsid = 1;
+
+ if (nvme_ns_setup(n, ns, errp)) {
return;
}
}
@@ -2824,7 +2891,8 @@ static void nvme_exit(PCIDevice *pci_dev)
}
static Property nvme_props[] = {
- DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
+ DEFINE_BLOCK_PROPERTIES_BASE(NvmeCtrl, conf),
+ DEFINE_PROP_DRIVE("drive", NvmeCtrl, namespace.blk),
DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
HostMemoryBackend *),
DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
@@ -2865,26 +2933,35 @@ static void nvme_instance_init(Object *obj)
{
NvmeCtrl *s = NVME(obj);
- device_add_bootindex_property(obj, &s->conf.bootindex,
- "bootindex", "/namespace@1,0",
- DEVICE(obj));
+ if (s->namespace.blk) {
+ device_add_bootindex_property(obj, &s->conf.bootindex,
+ "bootindex", "/namespace@1,0",
+ DEVICE(obj));
+ }
}
static const TypeInfo nvme_info = {
.name = TYPE_NVME,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(NvmeCtrl),
- .class_init = nvme_class_init,
.instance_init = nvme_instance_init,
+ .class_init = nvme_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_PCIE_DEVICE },
{ }
},
};
+static const TypeInfo nvme_bus_info = {
+ .name = TYPE_NVME_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(NvmeBus),
+};
+
static void nvme_register_types(void)
{
type_register_static(&nvme_info);
+ type_register_static(&nvme_bus_info);
}
type_init(nvme_register_types)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index baedcb226cb1..72260f2e8ea9 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -2,6 +2,9 @@
#define HW_NVME_H
#include "block/nvme.h"
+#include "nvme-ns.h"
+
+#define NVME_MAX_NAMESPACES 256
typedef struct NvmeParams {
char *serial;
@@ -135,26 +138,12 @@ typedef struct NvmeCQueue {
QTAILQ_HEAD(, NvmeRequest) req_list;
} NvmeCQueue;
-typedef struct NvmeNamespace {
- NvmeIdNs id_ns;
-} NvmeNamespace;
+#define TYPE_NVME_BUS "nvme-bus"
+#define NVME_BUS(obj) OBJECT_CHECK(NvmeBus, (obj), TYPE_NVME_BUS)
-static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
-{
- NvmeIdNs *id_ns = &ns->id_ns;
- return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
-}
-
-static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
-{
- return nvme_ns_lbaf(ns)->ds;
-}
-
-/* convert an LBA to the equivalent in bytes */
-static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
-{
- return lba << nvme_ns_lbads(ns);
-}
+typedef struct NvmeBus {
+ BusState parent_bus;
+} NvmeBus;
#define TYPE_NVME "nvme"
#define NVME(obj) \
@@ -166,6 +155,7 @@ typedef struct NvmeFeatureVal {
uint16_t temp_thresh_low;
};
uint32_t async_config;
+ uint32_t vwc;
} NvmeFeatureVal;
typedef struct NvmeCtrl {
@@ -173,8 +163,9 @@ typedef struct NvmeCtrl {
MemoryRegion iomem;
MemoryRegion ctrl_mem;
NvmeBar bar;
- BlockConf conf;
NvmeParams params;
+ NvmeBus bus;
+ BlockConf conf;
bool qs_created;
uint32_t page_size;
@@ -185,7 +176,6 @@ typedef struct NvmeCtrl {
uint32_t reg_size;
uint32_t num_namespaces;
uint32_t max_q_ents;
- uint64_t ns_size;
uint8_t outstanding_aers;
uint8_t *cmbuf;
uint32_t irq_status;
@@ -201,7 +191,8 @@ typedef struct NvmeCtrl {
QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
int aer_queued;
- NvmeNamespace *namespaces;
+ NvmeNamespace namespace;
+ NvmeNamespace *namespaces[NVME_MAX_NAMESPACES];
NvmeSQueue **sq;
NvmeCQueue **cq;
NvmeSQueue admin_sq;
@@ -210,10 +201,13 @@ typedef struct NvmeCtrl {
NvmeFeatureVal features;
} NvmeCtrl;
-/* calculate the number of LBAs that the namespace can accomodate */
-static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns)
+static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
{
- return n->ns_size >> nvme_ns_lbads(ns);
+ if (!nsid || nsid > n->num_namespaces) {
+ return NULL;
+ }
+
+ return n->namespaces[nsid - 1];
}
static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
@@ -224,4 +218,6 @@ static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
return n->cq[sq->cqid];
}
+int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
+
#endif /* HW_NVME_H */
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 7fe119bd625c..52c88e01a090 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -29,6 +29,7 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t heads, uint32_t secs, int t
# nvme.c
# nvme traces for successful events
+pci_nvme_register_namespace(uint32_t nsid) "nsid %"PRIu32""
pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
pci_nvme_irq_pin(void) "pulsing IRQ pin"
pci_nvme_irq_masked(void) "IRQ is masked"
@@ -39,11 +40,11 @@ pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2,
pci_nvme_map_sgl(uint16_t cid, uint8_t typ, uint64_t len) "cid %"PRIu16" type 0x%"PRIx8" len %"PRIu64""
pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname \"%s\""
-pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" \"%s\" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
+pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" opname \"%s\" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
+pci_nvme_rw_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32""
+pci_nvme_write_zeroes(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32""
pci_nvme_aio_add(uint16_t cid, void *aio, const char *blkname, uint64_t offset, uint64_t len, const char *opc, void *req) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" len %"PRIu64" opc \"%s\" req %p"
pci_nvme_aio_cb(uint16_t cid, void *aio, const char *blkname, uint64_t offset, uint64_t len, const char *opc, void *req) "cid %"PRIu16" aio %p blk \"%s\" offset %"PRIu64" len %"PRIu64" opc \"%s\" req %p"
-pci_nvme_rw_cb(uint16_t cid) "cid %"PRIu16""
-pci_nvme_write_zeroes(uint16_t cid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" slba %"PRIu64" nlb %"PRIu32""
pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien) "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d"
pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16""
@@ -100,7 +101,6 @@ pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or no
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
pci_nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be transferred"
pci_nvme_err_invalid_prp(void) "invalid PRP"
-pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not within 1-%u"
pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8""
pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8""
pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64""
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 16/17] pci: allocate pci id for nvme
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (14 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 15/17] hw/block/nvme: support multiple namespaces Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-04 14:19 ` [PATCH 17/17] hw/block/nvme: change controller pci id Klaus Jensen
2020-09-04 16:12 ` [PATCH 00/17] hw/block/nvme: multiple namespaces support Philippe Mathieu-Daudé
17 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Gerd Hoffmann,
Klaus Jensen, Maxim Levitsky
From: Klaus Jensen <k.jensen@samsung.com>
The emulated nvme device (hw/block/nvme.c) is currently using an
internal Intel device id.
Prepare to change that by allocating a device id under the 1b36 (Red
Hat, Inc.) vendor id.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Keith Busch <kbusch@kernel.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
MAINTAINERS | 1 +
docs/specs/nvme.txt | 23 +++++++++++++++++++++++
docs/specs/pci-ids.txt | 1 +
include/hw/pci/pci.h | 1 +
4 files changed, 26 insertions(+)
create mode 100644 docs/specs/nvme.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index b233da2a7379..5de612aae381 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1861,6 +1861,7 @@ L: qemu-block@nongnu.org
S: Supported
F: hw/block/nvme*
F: tests/qtest/nvme-test.c
+F: docs/specs/nvme.txt
T: git git://git.infradead.org/qemu-nvme.git nvme-next
megasas
diff --git a/docs/specs/nvme.txt b/docs/specs/nvme.txt
new file mode 100644
index 000000000000..56d393884e7a
--- /dev/null
+++ b/docs/specs/nvme.txt
@@ -0,0 +1,23 @@
+NVM Express Controller
+======================
+
+The nvme device (-device nvme) emulates an NVM Express Controller.
+
+
+Reference Specifications
+------------------------
+
+The device currently implements most mandatory features of NVMe v1.3d, see
+
+ https://nvmexpress.org/resources/specifications/
+
+for the specification.
+
+
+Known issues
+------------
+
+* The accounting numbers in the SMART/Health are reset across power cycles
+
+* Interrupt Coalescing is not supported and is disabled by default in volation
+ of the specification.
diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt
index 4d53e5c7d9d5..abbdbca6be38 100644
--- a/docs/specs/pci-ids.txt
+++ b/docs/specs/pci-ids.txt
@@ -63,6 +63,7 @@ PCI devices (other than virtio):
1b36:000b PCIe Expander Bridge (-device pxb-pcie)
1b36:000d PCI xhci usb host adapter
1b36:000f mdpy (mdev sample device), linux/samples/vfio-mdev/mdpy.c
+1b36:0010 PCIe NVMe device (-device nvme)
All these devices are documented in docs/specs.
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 896cef9ad476..f7123c5b8a2e 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -105,6 +105,7 @@ extern bool pci_available;
#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
+#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
#define FMT_PCIBUS PRIx64
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (15 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 16/17] pci: allocate pci id for nvme Klaus Jensen
@ 2020-09-04 14:19 ` Klaus Jensen
2020-09-07 2:28 ` Philippe Mathieu-Daudé
2020-09-04 16:12 ` [PATCH 00/17] hw/block/nvme: multiple namespaces support Philippe Mathieu-Daudé
17 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 14:19 UTC (permalink / raw)
To: qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch, Klaus Jensen,
Maxim Levitsky
From: Klaus Jensen <k.jensen@samsung.com>
There are two reasons for changing this:
1. The nvme device currently uses an internal Intel device id.
2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
support multiple namespaces" the controller device no longer has
the quirks that the Linux kernel think it has.
As the quirks are applied based on pci vendor and device id, change
them to get rid of the quirks.
To keep backward compatibility, add a new 'x-use-intel-id' parameter to
the nvme device to force use of the Intel vendor and device id. This is
off by default but add a compat property to set this for 5.1 machines
and older.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
hw/block/nvme.c | 12 ++++++++++--
hw/block/nvme.h | 1 +
hw/core/machine.c | 1 +
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 453d3a89d475..8018f8679366 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
+
+ if (n->params.use_intel_id) {
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, 0x5846);
+ } else {
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
+ }
+
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
pcie_endpoint_cap_init(pci_dev, 0x80);
@@ -2903,6 +2912,7 @@ static Property nvme_props[] = {
DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
+ DEFINE_PROP_BOOL("x-use-intel-id", NvmeCtrl, params.use_intel_id, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -2919,8 +2929,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
pc->realize = nvme_realize;
pc->exit = nvme_exit;
pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
- pc->vendor_id = PCI_VENDOR_ID_INTEL;
- pc->device_id = 0x5845;
pc->revision = 2;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 72260f2e8ea9..a734a5e1370d 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -15,6 +15,7 @@ typedef struct NvmeParams {
uint8_t aerl;
uint32_t aer_max_queued;
uint8_t mdts;
+ bool use_intel_id;
} NvmeParams;
typedef struct NvmeAsyncEvent {
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ea26d612374d..67990232528c 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -34,6 +34,7 @@ GlobalProperty hw_compat_5_1[] = {
{ "vhost-user-scsi", "num_queues", "1"},
{ "virtio-blk-device", "num-queues", "1"},
{ "virtio-scsi-device", "num_queues", "1"},
+ { "nvme", "x-use-intel-id", "on"},
};
const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
--
2.28.0
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-04 14:19 ` [PATCH 17/17] hw/block/nvme: change controller pci id Klaus Jensen
@ 2020-09-07 2:28 ` Philippe Mathieu-Daudé
2020-09-07 7:23 ` Klaus Jensen
2020-09-07 10:37 ` Dr. David Alan Gilbert
0 siblings, 2 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 2:28 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Dr. David Alan Gilbert, Max Reitz, Keith Busch,
Maxim Levitsky
+David in case
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> There are two reasons for changing this:
>
> 1. The nvme device currently uses an internal Intel device id.
>
> 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> support multiple namespaces" the controller device no longer has
> the quirks that the Linux kernel think it has.
>
> As the quirks are applied based on pci vendor and device id, change
> them to get rid of the quirks.
>
> To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> the nvme device to force use of the Intel vendor and device id. This is
> off by default but add a compat property to set this for 5.1 machines
> and older.
So now what happens if you start a 5.1 machine with a recent kernel?
Simply the kernel will use unnecessary quirks, or are there more
changes in behavior?
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> Reviewed-by: Keith Busch <kbusch@kernel.org>
> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> ---
> hw/block/nvme.c | 12 ++++++++++--
> hw/block/nvme.h | 1 +
> hw/core/machine.c | 1 +
> 3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> index 453d3a89d475..8018f8679366 100644
> --- a/hw/block/nvme.c
> +++ b/hw/block/nvme.c
> @@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
>
> pci_conf[PCI_INTERRUPT_PIN] = 1;
> pci_config_set_prog_interface(pci_conf, 0x2);
> +
> + if (n->params.use_intel_id) {
> + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> + pci_config_set_device_id(pci_conf, 0x5846);
> + } else {
> + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
> + pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
> + }
> +
> pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
> pcie_endpoint_cap_init(pci_dev, 0x80);
>
> @@ -2903,6 +2912,7 @@ static Property nvme_props[] = {
> DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
> DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
> DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
> + DEFINE_PROP_BOOL("x-use-intel-id", NvmeCtrl, params.use_intel_id, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -2919,8 +2929,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
> pc->realize = nvme_realize;
> pc->exit = nvme_exit;
> pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
> - pc->vendor_id = PCI_VENDOR_ID_INTEL;
> - pc->device_id = 0x5845;
> pc->revision = 2;
>
> set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
> diff --git a/hw/block/nvme.h b/hw/block/nvme.h
> index 72260f2e8ea9..a734a5e1370d 100644
> --- a/hw/block/nvme.h
> +++ b/hw/block/nvme.h
> @@ -15,6 +15,7 @@ typedef struct NvmeParams {
> uint8_t aerl;
> uint32_t aer_max_queued;
> uint8_t mdts;
> + bool use_intel_id;
> } NvmeParams;
>
> typedef struct NvmeAsyncEvent {
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index ea26d612374d..67990232528c 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -34,6 +34,7 @@ GlobalProperty hw_compat_5_1[] = {
> { "vhost-user-scsi", "num_queues", "1"},
> { "virtio-blk-device", "num-queues", "1"},
> { "virtio-scsi-device", "num_queues", "1"},
> + { "nvme", "x-use-intel-id", "on"},
> };
> const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 2:28 ` Philippe Mathieu-Daudé
@ 2020-09-07 7:23 ` Klaus Jensen
2020-09-07 8:36 ` Philippe Mathieu-Daudé
2020-09-07 10:37 ` Dr. David Alan Gilbert
1 sibling, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 7:23 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Dr. David Alan Gilbert, Keith Busch,
Max Reitz
[-- Attachment #1: Type: text/plain, Size: 1678 bytes --]
On Sep 7 04:28, Philippe Mathieu-Daudé wrote:
> +David in case
>
> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > There are two reasons for changing this:
> >
> > 1. The nvme device currently uses an internal Intel device id.
> >
> > 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > support multiple namespaces" the controller device no longer has
> > the quirks that the Linux kernel think it has.
> >
> > As the quirks are applied based on pci vendor and device id, change
> > them to get rid of the quirks.
> >
> > To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > the nvme device to force use of the Intel vendor and device id. This is
> > off by default but add a compat property to set this for 5.1 machines
> > and older.
>
> So now what happens if you start a 5.1 machine with a recent kernel?
> Simply the kernel will use unnecessary quirks, or are there more
> changes in behavior?
>
Yes, the kernel will then just apply unneccesary quirks, these are:
1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
anything else than values 0x0 and 0x1 for CNS (Identify Namespace and
Identify Namespace). With multiple namespace support, this just
means that the kernel will "scan" namespaces instead of using
"Active Namespace ID list" (CNS 0x2).
2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
broken Write Zeroes implementation which has since been fixed in
commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 7:23 ` Klaus Jensen
@ 2020-09-07 8:36 ` Philippe Mathieu-Daudé
2020-09-07 8:58 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 8:36 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Dr. David Alan Gilbert, Keith Busch,
Max Reitz
On 9/7/20 9:23 AM, Klaus Jensen wrote:
> On Sep 7 04:28, Philippe Mathieu-Daudé wrote:
>> +David in case
>>
>> On 9/4/20 4:19 PM, Klaus Jensen wrote:
>>> From: Klaus Jensen <k.jensen@samsung.com>
>>>
>>> There are two reasons for changing this:
>>>
>>> 1. The nvme device currently uses an internal Intel device id.
>>>
>>> 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
>>> support multiple namespaces" the controller device no longer has
>>> the quirks that the Linux kernel think it has.
>>>
>>> As the quirks are applied based on pci vendor and device id, change
>>> them to get rid of the quirks.
>>>
>>> To keep backward compatibility, add a new 'x-use-intel-id' parameter to
>>> the nvme device to force use of the Intel vendor and device id. This is
>>> off by default but add a compat property to set this for 5.1 machines
>>> and older.
>>
>> So now what happens if you start a 5.1 machine with a recent kernel?
>> Simply the kernel will use unnecessary quirks, or are there more
>> changes in behavior?
>>
>
> Yes, the kernel will then just apply unneccesary quirks, these are:
>
> 1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
> anything else than values 0x0 and 0x1 for CNS (Identify Namespace and
> Identify Namespace). With multiple namespace support, this just
> means that the kernel will "scan" namespaces instead of using
> "Active Namespace ID list" (CNS 0x2).
>
> 2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
> broken Write Zeroes implementation which has since been fixed in
> commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
OK thanks. Can you amend that information in the commit
description please?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 8:36 ` Philippe Mathieu-Daudé
@ 2020-09-07 8:58 ` Klaus Jensen
2020-09-07 9:20 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 8:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Dr. David Alan Gilbert, Keith Busch,
Max Reitz
[-- Attachment #1: Type: text/plain, Size: 1977 bytes --]
On Sep 7 10:36, Philippe Mathieu-Daudé wrote:
> On 9/7/20 9:23 AM, Klaus Jensen wrote:
> > On Sep 7 04:28, Philippe Mathieu-Daudé wrote:
> >> +David in case
> >>
> >> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> >>> From: Klaus Jensen <k.jensen@samsung.com>
> >>>
> >>> There are two reasons for changing this:
> >>>
> >>> 1. The nvme device currently uses an internal Intel device id.
> >>>
> >>> 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> >>> support multiple namespaces" the controller device no longer has
> >>> the quirks that the Linux kernel think it has.
> >>>
> >>> As the quirks are applied based on pci vendor and device id, change
> >>> them to get rid of the quirks.
> >>>
> >>> To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> >>> the nvme device to force use of the Intel vendor and device id. This is
> >>> off by default but add a compat property to set this for 5.1 machines
> >>> and older.
> >>
> >> So now what happens if you start a 5.1 machine with a recent kernel?
> >> Simply the kernel will use unnecessary quirks, or are there more
> >> changes in behavior?
> >>
> >
> > Yes, the kernel will then just apply unneccesary quirks, these are:
> >
> > 1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
> > anything else than values 0x0 and 0x1 for CNS (Identify Namespace and
> > Identify Namespace). With multiple namespace support, this just
> > means that the kernel will "scan" namespaces instead of using
> > "Active Namespace ID list" (CNS 0x2).
> >
> > 2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
> > broken Write Zeroes implementation which has since been fixed in
> > commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
>
> OK thanks. Can you amend that information in the commit
> description please?
>
Yes, absolutely.
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 8:58 ` Klaus Jensen
@ 2020-09-07 9:20 ` Klaus Jensen
2020-09-07 9:33 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 9:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Dr. David Alan Gilbert, Keith Busch,
Max Reitz
[-- Attachment #1: Type: text/plain, Size: 2350 bytes --]
On Sep 7 10:58, Klaus Jensen wrote:
> On Sep 7 10:36, Philippe Mathieu-Daudé wrote:
> > On 9/7/20 9:23 AM, Klaus Jensen wrote:
> > > On Sep 7 04:28, Philippe Mathieu-Daudé wrote:
> > >> +David in case
> > >>
> > >> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > >>> From: Klaus Jensen <k.jensen@samsung.com>
> > >>>
> > >>> There are two reasons for changing this:
> > >>>
> > >>> 1. The nvme device currently uses an internal Intel device id.
> > >>>
> > >>> 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > >>> support multiple namespaces" the controller device no longer has
> > >>> the quirks that the Linux kernel think it has.
> > >>>
> > >>> As the quirks are applied based on pci vendor and device id, change
> > >>> them to get rid of the quirks.
> > >>>
> > >>> To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > >>> the nvme device to force use of the Intel vendor and device id. This is
> > >>> off by default but add a compat property to set this for 5.1 machines
> > >>> and older.
> > >>
> > >> So now what happens if you start a 5.1 machine with a recent kernel?
> > >> Simply the kernel will use unnecessary quirks, or are there more
> > >> changes in behavior?
> > >>
> > >
> > > Yes, the kernel will then just apply unneccesary quirks, these are:
> > >
> > > 1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
> > > anything else than values 0x0 and 0x1 for CNS (Identify Namespace and
> > > Identify Namespace). With multiple namespace support, this just
> > > means that the kernel will "scan" namespaces instead of using
> > > "Active Namespace ID list" (CNS 0x2).
> > >
> > > 2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
> > > broken Write Zeroes implementation which has since been fixed in
> > > commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
> >
> > OK thanks. Can you amend that information in the commit
> > description please?
> >
>
> Yes, absolutely.
By the way. Is it correct use of an 'x-' parameter here - since it is
something that we might remove in the future? I was unable to find any
documentation on the purpose of the 'x-' prefix, but I was guessing it
was for stuff like this.
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 9:20 ` Klaus Jensen
@ 2020-09-07 9:33 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-07 9:33 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Dr. David Alan Gilbert, Keith Busch,
Max Reitz
On 9/7/20 11:20 AM, Klaus Jensen wrote:
> On Sep 7 10:58, Klaus Jensen wrote:
>> On Sep 7 10:36, Philippe Mathieu-Daudé wrote:
>>> On 9/7/20 9:23 AM, Klaus Jensen wrote:
>>>> On Sep 7 04:28, Philippe Mathieu-Daudé wrote:
>>>>> +David in case
>>>>>
>>>>> On 9/4/20 4:19 PM, Klaus Jensen wrote:
>>>>>> From: Klaus Jensen <k.jensen@samsung.com>
>>>>>>
>>>>>> There are two reasons for changing this:
>>>>>>
>>>>>> 1. The nvme device currently uses an internal Intel device id.
>>>>>>
>>>>>> 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
>>>>>> support multiple namespaces" the controller device no longer has
>>>>>> the quirks that the Linux kernel think it has.
>>>>>>
>>>>>> As the quirks are applied based on pci vendor and device id, change
>>>>>> them to get rid of the quirks.
>>>>>>
>>>>>> To keep backward compatibility, add a new 'x-use-intel-id' parameter to
>>>>>> the nvme device to force use of the Intel vendor and device id. This is
>>>>>> off by default but add a compat property to set this for 5.1 machines
>>>>>> and older.
>>>>>
>>>>> So now what happens if you start a 5.1 machine with a recent kernel?
>>>>> Simply the kernel will use unnecessary quirks, or are there more
>>>>> changes in behavior?
>>>>>
>>>>
>>>> Yes, the kernel will then just apply unneccesary quirks, these are:
>>>>
>>>> 1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
>>>> anything else than values 0x0 and 0x1 for CNS (Identify Namespace and
>>>> Identify Namespace). With multiple namespace support, this just
>>>> means that the kernel will "scan" namespaces instead of using
>>>> "Active Namespace ID list" (CNS 0x2).
>>>>
>>>> 2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
>>>> broken Write Zeroes implementation which has since been fixed in
>>>> commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
>>>
>>> OK thanks. Can you amend that information in the commit
>>> description please?
>>>
>>
>> Yes, absolutely.
>
> By the way. Is it correct use of an 'x-' parameter here - since it is
> something that we might remove in the future? I was unable to find any
> documentation on the purpose of the 'x-' prefix, but I was guessing it
> was for stuff like this.
Probably not. 'x-' is for unstable debugging/testing features.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 2:28 ` Philippe Mathieu-Daudé
2020-09-07 7:23 ` Klaus Jensen
@ 2020-09-07 10:37 ` Dr. David Alan Gilbert
2020-09-07 10:50 ` Klaus Jensen
1 sibling, 1 reply; 40+ messages in thread
From: Dr. David Alan Gilbert @ 2020-09-07 10:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch, Klaus Jensen,
Maxim Levitsky
* Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> +David in case
>
> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > There are two reasons for changing this:
> >
> > 1. The nvme device currently uses an internal Intel device id.
> >
> > 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > support multiple namespaces" the controller device no longer has
> > the quirks that the Linux kernel think it has.
> >
> > As the quirks are applied based on pci vendor and device id, change
> > them to get rid of the quirks.
> >
> > To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > the nvme device to force use of the Intel vendor and device id. This is
> > off by default but add a compat property to set this for 5.1 machines
> > and older.
>
> So now what happens if you start a 5.1 machine with a recent kernel?
> Simply the kernel will use unnecessary quirks, or are there more
> changes in behavior?
Seems reasonable to me...but...
> >
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > Reviewed-by: Keith Busch <kbusch@kernel.org>
> > Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> > ---
> > hw/block/nvme.c | 12 ++++++++++--
> > hw/block/nvme.h | 1 +
> > hw/core/machine.c | 1 +
> > 3 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > index 453d3a89d475..8018f8679366 100644
> > --- a/hw/block/nvme.c
> > +++ b/hw/block/nvme.c
> > @@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
> >
> > pci_conf[PCI_INTERRUPT_PIN] = 1;
> > pci_config_set_prog_interface(pci_conf, 0x2);
> > +
> > + if (n->params.use_intel_id) {
> > + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> > + pci_config_set_device_id(pci_conf, 0x5846);
Wasn't that magic number 5845 down there ?
Dave
> > + } else {
> > + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
> > + pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
> > + }
> > +
> > pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
> > pcie_endpoint_cap_init(pci_dev, 0x80);
> >
> > @@ -2903,6 +2912,7 @@ static Property nvme_props[] = {
> > DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
> > DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
> > DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
> > + DEFINE_PROP_BOOL("x-use-intel-id", NvmeCtrl, params.use_intel_id, false),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > @@ -2919,8 +2929,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
> > pc->realize = nvme_realize;
> > pc->exit = nvme_exit;
> > pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
> > - pc->vendor_id = PCI_VENDOR_ID_INTEL;
> > - pc->device_id = 0x5845;
> > pc->revision = 2;
> >
> > set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
> > diff --git a/hw/block/nvme.h b/hw/block/nvme.h
> > index 72260f2e8ea9..a734a5e1370d 100644
> > --- a/hw/block/nvme.h
> > +++ b/hw/block/nvme.h
> > @@ -15,6 +15,7 @@ typedef struct NvmeParams {
> > uint8_t aerl;
> > uint32_t aer_max_queued;
> > uint8_t mdts;
> > + bool use_intel_id;
> > } NvmeParams;
> >
> > typedef struct NvmeAsyncEvent {
> > diff --git a/hw/core/machine.c b/hw/core/machine.c
> > index ea26d612374d..67990232528c 100644
> > --- a/hw/core/machine.c
> > +++ b/hw/core/machine.c
> > @@ -34,6 +34,7 @@ GlobalProperty hw_compat_5_1[] = {
> > { "vhost-user-scsi", "num_queues", "1"},
> > { "virtio-blk-device", "num-queues", "1"},
> > { "virtio-scsi-device", "num_queues", "1"},
> > + { "nvme", "x-use-intel-id", "on"},
> > };
> > const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
> >
> >
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 10:37 ` Dr. David Alan Gilbert
@ 2020-09-07 10:50 ` Klaus Jensen
2020-09-07 10:52 ` Dr. David Alan Gilbert
0 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 10:50 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch, Maxim Levitsky,
Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 2284 bytes --]
On Sep 7 11:37, Dr. David Alan Gilbert wrote:
> * Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> > +David in case
> >
> > On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > > From: Klaus Jensen <k.jensen@samsung.com>
> > >
> > > There are two reasons for changing this:
> > >
> > > 1. The nvme device currently uses an internal Intel device id.
> > >
> > > 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > > support multiple namespaces" the controller device no longer has
> > > the quirks that the Linux kernel think it has.
> > >
> > > As the quirks are applied based on pci vendor and device id, change
> > > them to get rid of the quirks.
> > >
> > > To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > > the nvme device to force use of the Intel vendor and device id. This is
> > > off by default but add a compat property to set this for 5.1 machines
> > > and older.
> >
> > So now what happens if you start a 5.1 machine with a recent kernel?
> > Simply the kernel will use unnecessary quirks, or are there more
> > changes in behavior?
>
> Seems reasonable to me...but...
>
> > >
> > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > > Reviewed-by: Keith Busch <kbusch@kernel.org>
> > > Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> > > ---
> > > hw/block/nvme.c | 12 ++++++++++--
> > > hw/block/nvme.h | 1 +
> > > hw/core/machine.c | 1 +
> > > 3 files changed, 12 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > index 453d3a89d475..8018f8679366 100644
> > > --- a/hw/block/nvme.c
> > > +++ b/hw/block/nvme.c
> > > @@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
> > >
> > > pci_conf[PCI_INTERRUPT_PIN] = 1;
> > > pci_config_set_prog_interface(pci_conf, 0x2);
> > > +
> > > + if (n->params.use_intel_id) {
> > > + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> > > + pci_config_set_device_id(pci_conf, 0x5846);
>
> Wasn't that magic number 5845 down there ?
>
Argh! My first version of this just bumbed the intel device id and it
got left there.
Good find! Thank you!
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 10:50 ` Klaus Jensen
@ 2020-09-07 10:52 ` Dr. David Alan Gilbert
2020-09-07 11:02 ` Klaus Jensen
0 siblings, 1 reply; 40+ messages in thread
From: Dr. David Alan Gilbert @ 2020-09-07 10:52 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch, Maxim Levitsky,
Philippe Mathieu-Daudé
* Klaus Jensen (its@irrelevant.dk) wrote:
> On Sep 7 11:37, Dr. David Alan Gilbert wrote:
> > * Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> > > +David in case
> > >
> > > On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > > > From: Klaus Jensen <k.jensen@samsung.com>
> > > >
> > > > There are two reasons for changing this:
> > > >
> > > > 1. The nvme device currently uses an internal Intel device id.
> > > >
> > > > 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > > > support multiple namespaces" the controller device no longer has
> > > > the quirks that the Linux kernel think it has.
> > > >
> > > > As the quirks are applied based on pci vendor and device id, change
> > > > them to get rid of the quirks.
> > > >
> > > > To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > > > the nvme device to force use of the Intel vendor and device id. This is
> > > > off by default but add a compat property to set this for 5.1 machines
> > > > and older.
> > >
> > > So now what happens if you start a 5.1 machine with a recent kernel?
> > > Simply the kernel will use unnecessary quirks, or are there more
> > > changes in behavior?
> >
> > Seems reasonable to me...but...
> >
> > > >
> > > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > > > Reviewed-by: Keith Busch <kbusch@kernel.org>
> > > > Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> > > > ---
> > > > hw/block/nvme.c | 12 ++++++++++--
> > > > hw/block/nvme.h | 1 +
> > > > hw/core/machine.c | 1 +
> > > > 3 files changed, 12 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > > index 453d3a89d475..8018f8679366 100644
> > > > --- a/hw/block/nvme.c
> > > > +++ b/hw/block/nvme.c
> > > > @@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
> > > >
> > > > pci_conf[PCI_INTERRUPT_PIN] = 1;
> > > > pci_config_set_prog_interface(pci_conf, 0x2);
> > > > +
> > > > + if (n->params.use_intel_id) {
> > > > + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> > > > + pci_config_set_device_id(pci_conf, 0x5846);
> >
> > Wasn't that magic number 5845 down there ?
> >
>
> Argh! My first version of this just bumbed the intel device id and it
> got left there.
>
> Good find! Thank you!
It may be best to turn it into a constant in include/hw/pci/pci_ids.h if
it corresponds to some real Intel device.
Dave
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 10:52 ` Dr. David Alan Gilbert
@ 2020-09-07 11:02 ` Klaus Jensen
2020-09-08 15:39 ` Keith Busch
0 siblings, 1 reply; 40+ messages in thread
From: Klaus Jensen @ 2020-09-07 11:02 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch, Maxim Levitsky,
Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 3115 bytes --]
On Sep 7 11:52, Dr. David Alan Gilbert wrote:
> * Klaus Jensen (its@irrelevant.dk) wrote:
> > On Sep 7 11:37, Dr. David Alan Gilbert wrote:
> > > * Philippe Mathieu-Daudé (philmd@redhat.com) wrote:
> > > > +David in case
> > > >
> > > > On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > > > > From: Klaus Jensen <k.jensen@samsung.com>
> > > > >
> > > > > There are two reasons for changing this:
> > > > >
> > > > > 1. The nvme device currently uses an internal Intel device id.
> > > > >
> > > > > 2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
> > > > > support multiple namespaces" the controller device no longer has
> > > > > the quirks that the Linux kernel think it has.
> > > > >
> > > > > As the quirks are applied based on pci vendor and device id, change
> > > > > them to get rid of the quirks.
> > > > >
> > > > > To keep backward compatibility, add a new 'x-use-intel-id' parameter to
> > > > > the nvme device to force use of the Intel vendor and device id. This is
> > > > > off by default but add a compat property to set this for 5.1 machines
> > > > > and older.
> > > >
> > > > So now what happens if you start a 5.1 machine with a recent kernel?
> > > > Simply the kernel will use unnecessary quirks, or are there more
> > > > changes in behavior?
> > >
> > > Seems reasonable to me...but...
> > >
> > > > >
> > > > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > > > > Reviewed-by: Keith Busch <kbusch@kernel.org>
> > > > > Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
> > > > > ---
> > > > > hw/block/nvme.c | 12 ++++++++++--
> > > > > hw/block/nvme.h | 1 +
> > > > > hw/core/machine.c | 1 +
> > > > > 3 files changed, 12 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c
> > > > > index 453d3a89d475..8018f8679366 100644
> > > > > --- a/hw/block/nvme.c
> > > > > +++ b/hw/block/nvme.c
> > > > > @@ -2749,6 +2749,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
> > > > >
> > > > > pci_conf[PCI_INTERRUPT_PIN] = 1;
> > > > > pci_config_set_prog_interface(pci_conf, 0x2);
> > > > > +
> > > > > + if (n->params.use_intel_id) {
> > > > > + pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> > > > > + pci_config_set_device_id(pci_conf, 0x5846);
> > >
> > > Wasn't that magic number 5845 down there ?
> > >
> >
> > Argh! My first version of this just bumbed the intel device id and it
> > got left there.
> >
> > Good find! Thank you!
>
> It may be best to turn it into a constant in include/hw/pci/pci_ids.h if
> it corresponds to some real Intel device.
>
Yes, but that is just the thing - it does not correspond to an
officially allocated device; which is why I think we should leave it out
of pci_ids.h.
The end goal is to get rid of its use in the code by deprecating the
use-intel-id parameter in the future. I guess the parameter should just
be deprecated immediately? Then we can get rid of it in, what, 5.4?
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^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 17/17] hw/block/nvme: change controller pci id
2020-09-07 11:02 ` Klaus Jensen
@ 2020-09-08 15:39 ` Keith Busch
0 siblings, 0 replies; 40+ messages in thread
From: Keith Busch @ 2020-09-08 15:39 UTC (permalink / raw)
To: Klaus Jensen
Cc: Kevin Wolf, Maxim Levitsky, Eduardo Habkost, qemu-block,
Michael S. Tsirkin, Klaus Jensen, Dr. David Alan Gilbert,
qemu-devel, Max Reitz, Philippe Mathieu-Daudé
On Mon, Sep 07, 2020 at 01:02:16PM +0200, Klaus Jensen wrote:
> On Sep 7 11:52, Dr. David Alan Gilbert wrote:
>
> > It may be best to turn it into a constant in include/hw/pci/pci_ids.h if
> > it corresponds to some real Intel device.
> >
>
> Yes, but that is just the thing - it does not correspond to an
> officially allocated device; which is why I think we should leave it out
> of pci_ids.h.
>
> The end goal is to get rid of its use in the code by deprecating the
> use-intel-id parameter in the future. I guess the parameter should just
> be deprecated immediately? Then we can get rid of it in, what, 5.4?
It's not a real device yet, but it likely will not be an nvme device
once a product does release with this identifier. There may be trouble
with driver binding when that happens, so deprecating it here sooner
than later is my preference.
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 00/17] hw/block/nvme: multiple namespaces support
2020-09-04 14:19 [PATCH 00/17] hw/block/nvme: multiple namespaces support Klaus Jensen
` (16 preceding siblings ...)
2020-09-04 14:19 ` [PATCH 17/17] hw/block/nvme: change controller pci id Klaus Jensen
@ 2020-09-04 16:12 ` Philippe Mathieu-Daudé
2020-09-04 17:17 ` Klaus Jensen
17 siblings, 1 reply; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-04 16:12 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, Max Reitz, Keith Busch
Hi Klaus,
On 9/4/20 4:19 PM, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> This is the next round of my patches for the nvme device.
>
> This includes a bit of cleanup and three new features:
>
> * refactored aio submission
> This also adds support for multiple parallel AIOs per request which is in
> preparation for DULBE, ZNS and metadata support. If it is found
> controversial, it can easily be dropped from this series.
>
> * support for scatter/gather lists
>
> * multiple namespaces support through a new nvme-ns device
>
> Finally, the series ends with changing the PCI vendor and device ID to get rid
> of the internal Intel id and as a side-effect get rid of some Linux kernel
> quirks that no longer applies.
>
> "pci: pass along the return value of dma_memory_rw" has already been posted by
> Philippe in another series, but since it is not applied yet, I am including it
> here.
>
> Gollu Appalanaidu (1):
> hw/block/nvme: add support for sgl bit bucket descriptor
>
> Klaus Jensen (16):
> pci: pass along the return value of dma_memory_rw
> hw/block/nvme: handle dma errors
> hw/block/nvme: commonize nvme_rw error handling
> hw/block/nvme: alignment style fixes
> hw/block/nvme: add a lba to bytes helper
> hw/block/nvme: fix endian conversion
> hw/block/nvme: add symbolic command name to trace events
> hw/block/nvme: refactor aio submission
> hw/block/nvme: default request status to success
> hw/block/nvme: support multiple parallel aios per request
> hw/block/nvme: harden cmb access
> hw/block/nvme: add support for scatter gather lists
> hw/block/nvme: refactor identify active namespace id list
> hw/block/nvme: support multiple namespaces
> pci: allocate pci id for nvme
> hw/block/nvme: change controller pci id
>
> MAINTAINERS | 1 +
> docs/specs/nvme.txt | 23 +
> docs/specs/pci-ids.txt | 1 +
> hw/block/meson.build | 2 +-
> hw/block/nvme-ns.c | 185 +++++++++
> hw/block/nvme-ns.h | 74 ++++
> hw/block/nvme.c | 923 +++++++++++++++++++++++++++++++----------
> hw/block/nvme.h | 126 +++++-
> hw/block/trace-events | 21 +-
> hw/core/machine.c | 1 +
> include/block/nvme.h | 8 +-
> include/hw/pci/pci.h | 4 +-
To ease the review, consider setup'ing scripts/git.orderfile,
as it avoid reviewers to scroll patches in their email client.
Thanks,
Phil.
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 00/17] hw/block/nvme: multiple namespaces support
2020-09-04 16:12 ` [PATCH 00/17] hw/block/nvme: multiple namespaces support Philippe Mathieu-Daudé
@ 2020-09-04 17:17 ` Klaus Jensen
0 siblings, 0 replies; 40+ messages in thread
From: Klaus Jensen @ 2020-09-04 17:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Eduardo Habkost, qemu-block, Michael S. Tsirkin,
Klaus Jensen, qemu-devel, Max Reitz, Keith Busch
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On Sep 4 18:12, Philippe Mathieu-Daudé wrote:
> Hi Klaus,
>
> On 9/4/20 4:19 PM, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > This is the next round of my patches for the nvme device.
> >
> > This includes a bit of cleanup and three new features:
> >
> > * refactored aio submission
> > This also adds support for multiple parallel AIOs per request which is in
> > preparation for DULBE, ZNS and metadata support. If it is found
> > controversial, it can easily be dropped from this series.
> >
> > * support for scatter/gather lists
> >
> > * multiple namespaces support through a new nvme-ns device
> >
> > Finally, the series ends with changing the PCI vendor and device ID to get rid
> > of the internal Intel id and as a side-effect get rid of some Linux kernel
> > quirks that no longer applies.
> >
> > "pci: pass along the return value of dma_memory_rw" has already been posted by
> > Philippe in another series, but since it is not applied yet, I am including it
> > here.
> >
> > Gollu Appalanaidu (1):
> > hw/block/nvme: add support for sgl bit bucket descriptor
> >
> > Klaus Jensen (16):
> > pci: pass along the return value of dma_memory_rw
> > hw/block/nvme: handle dma errors
> > hw/block/nvme: commonize nvme_rw error handling
> > hw/block/nvme: alignment style fixes
> > hw/block/nvme: add a lba to bytes helper
> > hw/block/nvme: fix endian conversion
> > hw/block/nvme: add symbolic command name to trace events
> > hw/block/nvme: refactor aio submission
> > hw/block/nvme: default request status to success
> > hw/block/nvme: support multiple parallel aios per request
> > hw/block/nvme: harden cmb access
> > hw/block/nvme: add support for scatter gather lists
> > hw/block/nvme: refactor identify active namespace id list
> > hw/block/nvme: support multiple namespaces
> > pci: allocate pci id for nvme
> > hw/block/nvme: change controller pci id
> >
> > MAINTAINERS | 1 +
> > docs/specs/nvme.txt | 23 +
> > docs/specs/pci-ids.txt | 1 +
> > hw/block/meson.build | 2 +-
> > hw/block/nvme-ns.c | 185 +++++++++
> > hw/block/nvme-ns.h | 74 ++++
> > hw/block/nvme.c | 923 +++++++++++++++++++++++++++++++----------
> > hw/block/nvme.h | 126 +++++-
> > hw/block/trace-events | 21 +-
> > hw/core/machine.c | 1 +
> > include/block/nvme.h | 8 +-
> > include/hw/pci/pci.h | 4 +-
>
> To ease the review, consider setup'ing scripts/git.orderfile,
> as it avoid reviewers to scroll patches in their email client.
>
Oh wow. You learn something new everyday. That's really neat!
Thanks!
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^ permalink raw reply [flat|nested] 40+ messages in thread