* [PATCH v3 1/9] hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 2/9] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type Philippe Mathieu-Daudé
` (7 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
No code out of bcm2836.c uses (or requires) the BCM283XInfo
declarations. Move it locally to the C source file.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/arm/bcm2836.h | 8 --------
hw/arm/bcm2836.c | 14 ++++++++++++++
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index 428c15d316e..43e9f8cd0ef 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -43,12 +43,4 @@ struct BCM283XState {
BCM2835PeripheralState peripherals;
};
-typedef struct BCM283XInfo BCM283XInfo;
-
-struct BCM283XClass {
- DeviceClass parent_class;
- const BCM283XInfo *info;
-};
-
-
#endif /* BCM2836_H */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index f15cc3b4053..e7cc2c930d9 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -17,6 +17,15 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
+typedef struct BCM283XInfo BCM283XInfo;
+
+typedef struct BCM283XClass {
+ /*< private >*/
+ DeviceClass parent_class;
+ /*< public >*/
+ const BCM283XInfo *info;
+} BCM283XClass;
+
struct BCM283XInfo {
const char *name;
const char *cpu_type;
@@ -25,6 +34,11 @@ struct BCM283XInfo {
int clusterid;
};
+#define BCM283X_CLASS(klass) \
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
static const BCM283XInfo bcm283x_socs[] = {
{
.name = TYPE_BCM2836,
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/9] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 1/9] hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 3/9] hw/arm/bcm2836: Introduce BCM283XClass::core_count Philippe Mathieu-Daudé
` (6 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Igor Mammedov
Remove usage of TypeInfo::class_data. Instead fill the fields in
the corresponding class_init().
So far all children use the same values for almost all fields,
but we are going to add the BCM2711/BCM2838 SoC for the raspi4
machine which use different fields.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2836.c | 108 ++++++++++++++++++++++-------------------------
1 file changed, 51 insertions(+), 57 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index e7cc2c930d9..8f921d8e904 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -17,57 +17,31 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
-typedef struct BCM283XInfo BCM283XInfo;
-
typedef struct BCM283XClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
- const BCM283XInfo *info;
-} BCM283XClass;
-
-struct BCM283XInfo {
const char *name;
const char *cpu_type;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
-};
+} BCM283XClass;
#define BCM283X_CLASS(klass) \
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
#define BCM283X_GET_CLASS(obj) \
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
-static const BCM283XInfo bcm283x_socs[] = {
- {
- .name = TYPE_BCM2836,
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
- .peri_base = 0x3f000000,
- .ctrl_base = 0x40000000,
- .clusterid = 0xf,
- },
-#ifdef TARGET_AARCH64
- {
- .name = TYPE_BCM2837,
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
- .peri_base = 0x3f000000,
- .ctrl_base = 0x40000000,
- .clusterid = 0x0,
- },
-#endif
-};
-
static void bcm2836_init(Object *obj)
{
BCM283XState *s = BCM283X(obj);
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
- const BCM283XInfo *info = bc->info;
int n;
for (n = 0; n < BCM283X_NCPUS; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
- info->cpu_type);
+ bc->cpu_type);
}
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
@@ -84,7 +58,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
- const BCM283XInfo *info = bc->info;
Object *obj;
int n;
@@ -102,14 +75,14 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
"sd-bus");
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
- info->peri_base, 1);
+ bc->peri_base, 1);
/* bcm2836 interrupt controller (and mailboxes, etc.) */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
@@ -118,11 +91,11 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
for (n = 0; n < BCM283X_NCPUS; n++) {
/* TODO: this should be converted to a property of ARM_CPU */
- s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
+ s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
/* set periphbase/CBAR value for CPU-local registers */
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
- info->peri_base, errp)) {
+ bc->peri_base, errp)) {
return;
}
@@ -165,38 +138,59 @@ static Property bcm2836_props[] = {
static void bcm283x_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- BCM283XClass *bc = BCM283X_CLASS(oc);
- bc->info = data;
- dc->realize = bcm2836_realize;
- device_class_set_props(dc, bcm2836_props);
/* Reason: Must be wired up in code (see raspi_init() function) */
dc->user_creatable = false;
}
-static const TypeInfo bcm283x_type_info = {
- .name = TYPE_BCM283X,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(BCM283XState),
- .instance_init = bcm2836_init,
- .class_size = sizeof(BCM283XClass),
- .abstract = true,
+static void bcm2836_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ bc->peri_base = 0x3f000000;
+ bc->ctrl_base = 0x40000000;
+ bc->clusterid = 0xf;
+ dc->realize = bcm2836_realize;
+ device_class_set_props(dc, bcm2836_props);
};
-static void bcm2836_register_types(void)
+#ifdef TARGET_AARCH64
+static void bcm2837_class_init(ObjectClass *oc, void *data)
{
- int i;
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
- type_register_static(&bcm283x_type_info);
- for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
- TypeInfo ti = {
- .name = bcm283x_socs[i].name,
- .parent = TYPE_BCM283X,
- .class_init = bcm283x_class_init,
- .class_data = (void *) &bcm283x_socs[i],
- };
- type_register(&ti);
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+ bc->peri_base = 0x3f000000;
+ bc->ctrl_base = 0x40000000;
+ bc->clusterid = 0x0;
+ dc->realize = bcm2836_realize;
+ device_class_set_props(dc, bcm2836_props);
+};
+#endif
+
+static const TypeInfo bcm283x_types[] = {
+ {
+ .name = TYPE_BCM2836,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2836_class_init,
+#ifdef TARGET_AARCH64
+ }, {
+ .name = TYPE_BCM2837,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2837_class_init,
+#endif
+ }, {
+ .name = TYPE_BCM283X,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(BCM283XState),
+ .instance_init = bcm2836_init,
+ .class_size = sizeof(BCM283XClass),
+ .class_init = bcm283x_class_init,
+ .abstract = true,
}
-}
+};
-type_init(bcm2836_register_types)
+DEFINE_TYPES(bcm283x_types)
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/9] hw/arm/bcm2836: Introduce BCM283XClass::core_count
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 1/9] hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 2/9] hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 4/9] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs Philippe Mathieu-Daudé
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
The BCM2835 has only one core. Introduce the core_count field to
be able to use values different than BCM283X_NCPUS (4).
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2836.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 8f921d8e904..c5d46a8e805 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -23,6 +23,7 @@ typedef struct BCM283XClass {
/*< public >*/
const char *name;
const char *cpu_type;
+ unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
@@ -39,7 +40,7 @@ static void bcm2836_init(Object *obj)
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
int n;
- for (n = 0; n < BCM283X_NCPUS; n++) {
+ for (n = 0; n < bc->core_count; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
bc->cpu_type);
}
@@ -149,6 +150,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0xf;
@@ -163,6 +165,7 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
BCM283XClass *bc = BCM283X_CLASS(oc);
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+ bc->core_count = BCM283X_NCPUS;
bc->peri_base = 0x3f000000;
bc->ctrl_base = 0x40000000;
bc->clusterid = 0x0;
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/9] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 3/9] hw/arm/bcm2836: Introduce BCM283XClass::core_count Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 5/9] hw/arm/bcm2836: Split out common realize() code Philippe Mathieu-Daudé
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
It makes no sense to set enabled-cpus=0 on single core SoCs.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2836.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index c5d46a8e805..fcb2c9c3e73 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -34,6 +34,9 @@ typedef struct BCM283XClass {
#define BCM283X_GET_CLASS(obj) \
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+static Property bcm2836_enabled_cores_property =
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
+
static void bcm2836_init(Object *obj)
{
BCM283XState *s = BCM283X(obj);
@@ -44,6 +47,10 @@ static void bcm2836_init(Object *obj)
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
bc->cpu_type);
}
+ if (bc->core_count > 1) {
+ qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
+ qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
+ }
object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
@@ -130,12 +137,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
}
}
-static Property bcm2836_props[] = {
- DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
- BCM283X_NCPUS),
- DEFINE_PROP_END_OF_LIST()
-};
-
static void bcm283x_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -155,7 +156,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
bc->ctrl_base = 0x40000000;
bc->clusterid = 0xf;
dc->realize = bcm2836_realize;
- device_class_set_props(dc, bcm2836_props);
};
#ifdef TARGET_AARCH64
@@ -170,7 +170,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
bc->ctrl_base = 0x40000000;
bc->clusterid = 0x0;
dc->realize = bcm2836_realize;
- device_class_set_props(dc, bcm2836_props);
};
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/9] hw/arm/bcm2836: Split out common realize() code
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 4/9] hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 6/9] hw/arm/bcm2836: Introduce the BCM2835 SoC Philippe Mathieu-Daudé
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
The realize() function is clearly composed of two parts,
each described by a comment:
void realize()
{
/* common peripherals from bcm2835 */
...
/* bcm2836 interrupt controller (and mailboxes, etc.) */
...
}
Split the two part, so we can reuse the common part with other
SoCs from this family.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/bcm2836.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index fcb2c9c3e73..7d975cf2f53 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -52,7 +52,10 @@ static void bcm2836_init(Object *obj)
qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
}
- object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
+ if (bc->ctrl_base) {
+ object_initialize_child(obj, "control", &s->control,
+ TYPE_BCM2836_CONTROL);
+ }
object_initialize_child(obj, "peripherals", &s->peripherals,
TYPE_BCM2835_PERIPHERALS);
@@ -62,12 +65,11 @@ static void bcm2836_init(Object *obj)
"vcram-size");
}
-static void bcm2836_realize(DeviceState *dev, Error **errp)
+static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
Object *obj;
- int n;
/* common peripherals from bcm2835 */
@@ -76,7 +78,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
- return;
+ return false;
}
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
@@ -84,6 +86,18 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
bc->peri_base, 1);
+ return true;
+}
+
+static void bcm2836_realize(DeviceState *dev, Error **errp)
+{
+ BCM283XState *s = BCM283X(dev);
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+ int n;
+
+ if (!bcm283x_common_realize(dev, errp)) {
+ return;
+ }
/* bcm2836 interrupt controller (and mailboxes, etc.) */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/9] hw/arm/bcm2836: Introduce the BCM2835 SoC
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 5/9] hw/arm/bcm2836: Split out common realize() code Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 7/9] hw/arm/raspi: Add the Raspberry Pi A+ machine Philippe Mathieu-Daudé
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/arm/bcm2836.h | 1 +
hw/arm/bcm2836.c | 34 ++++++++++++++++++++++++++++++++++
hw/arm/raspi.c | 2 ++
3 files changed, 37 insertions(+)
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index 43e9f8cd0ef..6f90cabfa3a 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
* them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros.
*/
+#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 7d975cf2f53..de7ade2878e 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -89,6 +89,25 @@ static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
return true;
}
+static void bcm2835_realize(DeviceState *dev, Error **errp)
+{
+ BCM283XState *s = BCM283X(dev);
+
+ if (!bcm283x_common_realize(dev, errp)) {
+ return;
+ }
+
+ if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
+ return;
+ }
+
+ /* Connect irq/fiq outputs from the interrupt controller. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
+}
+
static void bcm2836_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
@@ -159,6 +178,17 @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
+static void bcm2835_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ bc->core_count = 1;
+ bc->peri_base = 0x20000000;
+ dc->realize = bcm2835_realize;
+};
+
static void bcm2836_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -189,6 +219,10 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
static const TypeInfo bcm283x_types[] = {
{
+ .name = TYPE_BCM2835,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2835_class_init,
+ }, {
.name = TYPE_BCM2836,
.parent = TYPE_BCM283X,
.class_init = bcm2836_class_init,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index b5b30f0f38f..30fafa59ecb 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId {
+ PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId;
@@ -78,6 +79,7 @@ static const struct {
const char *type;
int cores_count;
} soc_property[] = {
+ [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
};
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 7/9] hw/arm/raspi: Add the Raspberry Pi A+ machine
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 6/9] hw/arm/bcm2836: Introduce the BCM2835 SoC Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-23 15:55 ` Igor Mammedov
2020-10-18 20:33 ` [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine Philippe Mathieu-Daudé
2020-10-18 20:33 ` [PATCH v3 9/9] hw/arm/raspi: Add the Raspberry Pi 3 model A+ Philippe Mathieu-Daudé
8 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann
The Pi A is almost the first machine released.
It uses a BCM2835 SoC which includes a ARMv6Z core.
Example booting the machine using content from [*]
(we use the device tree from the B model):
$ qemu-system-arm -M raspi1ap -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
-dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \
-append 'earlycon=pl011,0x20201000 console=ttyAMA0'
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+
...
[*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/raspi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 30fafa59ecb..91a59d1d489 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
mc->default_ram_id = "ram";
};
+static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x900021;
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -343,6 +352,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo raspi_machine_types[] = {
{
+ .name = MACHINE_TYPE_NAME("raspi1ap"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi1ap_machine_class_init,
+ }, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 7/9] hw/arm/raspi: Add the Raspberry Pi A+ machine
2020-10-18 20:33 ` [PATCH v3 7/9] hw/arm/raspi: Add the Raspberry Pi A+ machine Philippe Mathieu-Daudé
@ 2020-10-23 15:55 ` Igor Mammedov
0 siblings, 0 replies; 15+ messages in thread
From: Igor Mammedov @ 2020-10-23 15:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, qemu-arm, Luc Michel, qemu-devel, Andrew Baumann
On Sun, 18 Oct 2020 22:33:56 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> The Pi A is almost the first machine released.
> It uses a BCM2835 SoC which includes a ARMv6Z core.
>
> Example booting the machine using content from [*]
> (we use the device tree from the B model):
>
> $ qemu-system-arm -M raspi1ap -serial stdio \
> -kernel raspberrypi/firmware/boot/kernel.img \
> -dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \
> -append 'earlycon=pl011,0x20201000 console=ttyAMA0'
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
> [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
> [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
> [ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+
> ...
>
> [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/arm/raspi.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index 30fafa59ecb..91a59d1d489 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
> mc->default_ram_id = "ram";
> };
>
> +static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
> +
> + rmc->board_rev = 0x900021;
> + raspi_machine_class_common_init(mc, rmc->board_rev);
> +};
> +
> static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -343,6 +352,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo raspi_machine_types[] = {
> {
> + .name = MACHINE_TYPE_NAME("raspi1ap"),
> + .parent = TYPE_RASPI_MACHINE,
> + .class_init = raspi1ap_machine_class_init,
> + }, {
> .name = MACHINE_TYPE_NAME("raspi2b"),
> .parent = TYPE_RASPI_MACHINE,
> .class_init = raspi2b_machine_class_init,
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 7/9] hw/arm/raspi: Add the Raspberry Pi A+ machine Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-23 15:51 ` Igor Mammedov
2020-10-18 20:33 ` [PATCH v3 9/9] hw/arm/raspi: Add the Raspberry Pi 3 model A+ Philippe Mathieu-Daudé
8 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann, qemu-arm, Luc Michel
Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
Example booting the machine using content from [*]:
$ qemu-system-arm -M raspi0 -serial stdio \
-kernel raspberrypi/firmware/boot/kernel.img \
-dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
-append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
[ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
...
[*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/raspi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 91a59d1d489..1510ca01afe 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
mc->default_ram_id = "ram";
};
+static void raspi0_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x900092;
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -352,6 +361,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo raspi_machine_types[] = {
{
+ .name = MACHINE_TYPE_NAME("raspi0"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi0_machine_class_init,
+ }, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine
2020-10-18 20:33 ` [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine Philippe Mathieu-Daudé
@ 2020-10-23 15:51 ` Igor Mammedov
2020-10-23 17:35 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 15+ messages in thread
From: Igor Mammedov @ 2020-10-23 15:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Luc Michel, qemu-devel, Andrew Baumann, qemu-arm,
Luc Michel
On Sun, 18 Oct 2020 22:33:57 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
>
> Example booting the machine using content from [*]:
>
> $ qemu-system-arm -M raspi0 -serial stdio \
> -kernel raspberrypi/firmware/boot/kernel.img \
> -dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
> -append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
> [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
> [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
> [ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
> ...
>
> [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
>
> Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/arm/raspi.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index 91a59d1d489..1510ca01afe 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
> mc->default_ram_id = "ram";
> };
>
> +static void raspi0_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
> +
> + rmc->board_rev = 0x900092;
shouldn't it be
920092 Zero 1.2 512MB Embest
or
920093 Zero 1.3 512MB Embest
> + raspi_machine_class_common_init(mc, rmc->board_rev);
> +};
> +
> static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -352,6 +361,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo raspi_machine_types[] = {
> {
> + .name = MACHINE_TYPE_NAME("raspi0"),
> + .parent = TYPE_RASPI_MACHINE,
> + .class_init = raspi0_machine_class_init,
> + }, {
> .name = MACHINE_TYPE_NAME("raspi1ap"),
> .parent = TYPE_RASPI_MACHINE,
> .class_init = raspi1ap_machine_class_init,
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine
2020-10-23 15:51 ` Igor Mammedov
@ 2020-10-23 17:35 ` Philippe Mathieu-Daudé
2020-10-23 17:39 ` Igor Mammedov
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-23 17:35 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Luc Michel, qemu-devel, Andrew Baumann, qemu-arm,
Luc Michel
Hi Igor,
On 10/23/20 5:51 PM, Igor Mammedov wrote:
> On Sun, 18 Oct 2020 22:33:57 +0200
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
>> Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
>>
>> Example booting the machine using content from [*]:
>>
>> $ qemu-system-arm -M raspi0 -serial stdio \
>> -kernel raspberrypi/firmware/boot/kernel.img \
>> -dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
>> -append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
>> [ 0.000000] Booting Linux on physical CPU 0x0
>> [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
>> [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
>> [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
>> [ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
>> ...
>>
>> [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
>>
>> Reviewed-by: Luc Michel <luc.michel@greensocs.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> hw/arm/raspi.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
>> index 91a59d1d489..1510ca01afe 100644
>> --- a/hw/arm/raspi.c
>> +++ b/hw/arm/raspi.c
>> @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
>> mc->default_ram_id = "ram";
>> };
>>
>> +static void raspi0_machine_class_init(ObjectClass *oc, void *data)
>> +{
>> + MachineClass *mc = MACHINE_CLASS(oc);
>> + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
>> +
>> + rmc->board_rev = 0x900092;
>
> shouldn't it be
> 920092 Zero 1.2 512MB Embest
> or
> 920093 Zero 1.3 512MB Embest
I took the value from the "New-style revision codes"
table listed in hw/arm/raspi.c before the REV_CODE
register definitions:
https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
90009x's manufacturer is "Sony UK", 92009x is "Embest".
I guess we don't care much the manufacturer :)
The Revision 1.3 exposed the MIPI camera interface.
As we don't model it, I prefer to use the 1.2 revision
which matches better.
I'll add this information in the commit description.
Thanks for reviewing!
>
>> + raspi_machine_class_common_init(mc, rmc->board_rev);
>> +};
>> +
>> static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
>> {
>> MachineClass *mc = MACHINE_CLASS(oc);
>> @@ -352,6 +361,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
>>
>> static const TypeInfo raspi_machine_types[] = {
>> {
>> + .name = MACHINE_TYPE_NAME("raspi0"),
>> + .parent = TYPE_RASPI_MACHINE,
>> + .class_init = raspi0_machine_class_init,
>> + }, {
>> .name = MACHINE_TYPE_NAME("raspi1ap"),
>> .parent = TYPE_RASPI_MACHINE,
>> .class_init = raspi1ap_machine_class_init,
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine
2020-10-23 17:35 ` Philippe Mathieu-Daudé
@ 2020-10-23 17:39 ` Igor Mammedov
0 siblings, 0 replies; 15+ messages in thread
From: Igor Mammedov @ 2020-10-23 17:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Luc Michel, qemu-devel, Andrew Baumann, qemu-arm,
Luc Michel
On Fri, 23 Oct 2020 19:35:19 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi Igor,
>
> On 10/23/20 5:51 PM, Igor Mammedov wrote:
> > On Sun, 18 Oct 2020 22:33:57 +0200
> > Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >
> >> Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core).
> >>
> >> Example booting the machine using content from [*]:
> >>
> >> $ qemu-system-arm -M raspi0 -serial stdio \
> >> -kernel raspberrypi/firmware/boot/kernel.img \
> >> -dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \
> >> -append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0'
> >> [ 0.000000] Booting Linux on physical CPU 0x0
> >> [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020
> >> [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
> >> [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache
> >> [ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero
> >> ...
> >>
> >> [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb
> >>
> >> Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> >> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >> ---
> >> hw/arm/raspi.c | 13 +++++++++++++
> >> 1 file changed, 13 insertions(+)
> >>
> >> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> >> index 91a59d1d489..1510ca01afe 100644
> >> --- a/hw/arm/raspi.c
> >> +++ b/hw/arm/raspi.c
> >> @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc,
> >> mc->default_ram_id = "ram";
> >> };
> >>
> >> +static void raspi0_machine_class_init(ObjectClass *oc, void *data)
> >> +{
> >> + MachineClass *mc = MACHINE_CLASS(oc);
> >> + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
> >> +
> >> + rmc->board_rev = 0x900092;
> >
> > shouldn't it be
> > 920092 Zero 1.2 512MB Embest
> > or
> > 920093 Zero 1.3 512MB Embest
>
> I took the value from the "New-style revision codes"
> table listed in hw/arm/raspi.c before the REV_CODE
> register definitions:
>
> https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
>
> 90009x's manufacturer is "Sony UK", 92009x is "Embest".
> I guess we don't care much the manufacturer :)
>
> The Revision 1.3 exposed the MIPI camera interface.
> As we don't model it, I prefer to use the 1.2 revision
> which matches better.
>
> I'll add this information in the commit description.
With that
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
>
> Thanks for reviewing!
>
> >
> >> + raspi_machine_class_common_init(mc, rmc->board_rev);
> >> +};
> >> +
> >> static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
> >> {
> >> MachineClass *mc = MACHINE_CLASS(oc);
> >> @@ -352,6 +361,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
> >>
> >> static const TypeInfo raspi_machine_types[] = {
> >> {
> >> + .name = MACHINE_TYPE_NAME("raspi0"),
> >> + .parent = TYPE_RASPI_MACHINE,
> >> + .class_init = raspi0_machine_class_init,
> >> + }, {
> >> .name = MACHINE_TYPE_NAME("raspi1ap"),
> >> .parent = TYPE_RASPI_MACHINE,
> >> .class_init = raspi1ap_machine_class_init,
> >
> >
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 9/9] hw/arm/raspi: Add the Raspberry Pi 3 model A+
2020-10-18 20:33 [PATCH v3 0/9] hw/arm: Add raspi Zero, 1A+ and 3A+ machines Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2020-10-18 20:33 ` [PATCH v3 8/9] hw/arm/raspi: Add the Raspberry Pi Zero machine Philippe Mathieu-Daudé
@ 2020-10-18 20:33 ` Philippe Mathieu-Daudé
2020-10-23 15:57 ` Igor Mammedov
8 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-18 20:33 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, qemu-arm, Luc Michel, Philippe Mathieu-Daudé,
Andrew Baumann
The Pi 3A+ is a stripped down version of the 3B:
- 512 MiB of RAM instead of 1 GiB
- no on-board ethernet chipset
Add it as it is a closer match to what we model.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/arm/raspi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 1510ca01afe..4ea200572ea 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -348,6 +348,15 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
};
#ifdef TARGET_AARCH64
+static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x9020e0;
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -373,6 +382,10 @@ static const TypeInfo raspi_machine_types[] = {
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
#ifdef TARGET_AARCH64
+ }, {
+ .name = MACHINE_TYPE_NAME("raspi3ap"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi3ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
--
2.26.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 9/9] hw/arm/raspi: Add the Raspberry Pi 3 model A+
2020-10-18 20:33 ` [PATCH v3 9/9] hw/arm/raspi: Add the Raspberry Pi 3 model A+ Philippe Mathieu-Daudé
@ 2020-10-23 15:57 ` Igor Mammedov
0 siblings, 0 replies; 15+ messages in thread
From: Igor Mammedov @ 2020-10-23 15:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, qemu-arm, Luc Michel, qemu-devel, Andrew Baumann
On Sun, 18 Oct 2020 22:33:58 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> The Pi 3A+ is a stripped down version of the 3B:
> - 512 MiB of RAM instead of 1 GiB
> - no on-board ethernet chipset
>
> Add it as it is a closer match to what we model.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/arm/raspi.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
> index 1510ca01afe..4ea200572ea 100644
> --- a/hw/arm/raspi.c
> +++ b/hw/arm/raspi.c
> @@ -348,6 +348,15 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
> };
>
> #ifdef TARGET_AARCH64
> +static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
> +
> + rmc->board_rev = 0x9020e0;
> + raspi_machine_class_common_init(mc, rmc->board_rev);
> +};
> +
> static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -373,6 +382,10 @@ static const TypeInfo raspi_machine_types[] = {
> .parent = TYPE_RASPI_MACHINE,
> .class_init = raspi2b_machine_class_init,
> #ifdef TARGET_AARCH64
> + }, {
> + .name = MACHINE_TYPE_NAME("raspi3ap"),
> + .parent = TYPE_RASPI_MACHINE,
> + .class_init = raspi3ap_machine_class_init,
> }, {
> .name = MACHINE_TYPE_NAME("raspi3b"),
> .parent = TYPE_RASPI_MACHINE,
^ permalink raw reply [flat|nested] 15+ messages in thread