* [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM
@ 2020-11-03 12:01 Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Jiahui Cen
` (8 more replies)
0 siblings, 9 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
Changes with v8
v8->v9:
Rebase to master
Changes with v7
v7->v8:
Fix the error:no member named 'fw_cfg' in 'struct PCMachineState'
Changes with v6
v6->v7:
Refactor fw_cfg_write_extra_pci_roots
Add API PCI_GET_PCIE_HOST_STATE
Fix typos
Changes with v5
v5->v6: stat crs_range_insert in aml_build.h
Changes with v4
v4->v5: Not using specific resources for PXB.
Instead, the resources for pxb are composed of the bar space of the
pci-bridge/pcie-root-port behined it and the config space of devices
behind it.
Only if the bios(uefi for arm) support multiple roots,
configure space of devices behind pxbs could be obtained.
The uefi work is updated for discussion by the following link:
https://edk2.groups.io/g/devel/message/56901?p=,,,20,0,0,0::Created,,add+extra+roots+for+Arm,20,2,0,72723351
[PATCH] ArmVirtPkg/FdtPciHostBridgeLib: add extra roots for Arm.
This patch will be updated to v2 later.
Currently pxb-pcie is not supported by arm,
the reason for it is pxb-pcie is not described in DSDT table
and only one main host bridge is described in acpi tables,
which means it is not impossible to present different io numas
for different devices.
This series of patches make arm to support PXB-PCIE.
Users can configure pxb-pcie with certain numa, Example command
is:
-device pxb-pcie,id=pci.7,bus_nr=128,numa_node=0,bus=pcie.0,addr=0x9
Yubo Miao (8):
acpi: Extract two APIs from acpi_dsdt_add_pci
fw_cfg: Write the extra roots into the fw_cfg
acpi: Extract crs build form acpi_build.c
acpi: Refactor the source of host bridge and build tables for pxb
acpi: Align the size to 128k
unit-test: The files changed.
unit-test: Add testcase for pxb
unit-test: Add the binary file and clear diff.h
hw/acpi/aml-build.c | 273 ++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 30 +++-
hw/arm/virt.c | 8 +
hw/i386/acpi-build.c | 293 ---------------------------------
hw/i386/pc.c | 18 +-
hw/nvram/fw_cfg.c | 20 +++
hw/pci-host/gpex-acpi.c | 205 +++++++++++++++++------
include/hw/acpi/aml-build.h | 25 +++
include/hw/nvram/fw_cfg.h | 2 +
include/hw/pci/pcie_host.h | 4 +
tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 7802 bytes
tests/qtest/bios-tables-test.c | 58 ++++++-
12 files changed, 568 insertions(+), 368 deletions(-)
create mode 100644 tests/data/acpi/virt/DSDT.pxb
--
2.19.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg Jiahui Cen
` (7 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
Extract two APIs acpi_dsdt_add_pci_route_table and
acpi_dsdt_add_pci_osc from acpi_dsdt_add_pci. The first
API is used to specify the pci route table and the second
API is used to declare the operation system capabilities.
These two APIs would be used to specify the pxb-pcie in DSDT.
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/pci-host/gpex-acpi.c | 118 +++++++++++++++++++++++-----------------
1 file changed, 67 insertions(+), 51 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index dbb350a837..86ddb52cbd 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -2,20 +2,10 @@
#include "hw/acpi/aml-build.h"
#include "hw/pci-host/gpex.h"
-void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
+static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope, uint32_t irq)
{
- int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
- Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
int i, slot_no;
-
- Aml *dev = aml_device("%s", "PCI0");
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
- aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
- aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
- aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
- aml_append(dev, aml_name_decl("_UID", aml_int(0)));
- aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+ Aml *method, *crs;
/* Declare the PCI Routing Table. */
Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
@@ -34,7 +24,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
/* Create GSI link device */
for (i = 0; i < PCI_NUM_PINS; i++) {
- uint32_t irqs = cfg->irq + i;
+ uint32_t irqs = irq + i;
Aml *dev_gsi = aml_device("GSI%d", i);
aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
@@ -52,43 +42,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev_gsi, method);
aml_append(dev, dev_gsi);
}
+}
- method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
- aml_append(method, aml_return(aml_int(cfg->ecam.base)));
- aml_append(dev, method);
-
- Aml *rbuf = aml_resource_template();
- aml_append(rbuf,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
- nr_pcie_buses));
- if (cfg->mmio32.size) {
- aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio32.base,
- cfg->mmio32.base + cfg->mmio32.size - 1,
- 0x0000,
- cfg->mmio32.size));
- }
- if (cfg->pio.size) {
- aml_append(rbuf,
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000,
- cfg->pio.size - 1,
- cfg->pio.base,
- cfg->pio.size));
- }
- if (cfg->mmio64.size) {
- aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio64.base,
- cfg->mmio64.base + cfg->mmio64.size - 1,
- 0x0000,
- cfg->mmio64.size));
- }
- aml_append(dev, aml_name_decl("_CRS", rbuf));
+static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
+{
+ Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
/* Declare an _OSC (OS Control Handoff) method */
aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
@@ -97,7 +55,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(method,
aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
- /* PCI Firmware Specification 3.0
+ /*
+ * PCI Firmware Specification 3.0
* 4.5.1. _OSC Interface for PCI Host Bridge Devices
* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
* identified by the Universal Unique IDentifier (UUID)
@@ -142,7 +101,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
- /* PCI Firmware Specification 3.0
+ /*
+ * PCI Firmware Specification 3.0
* 4.6.1. _DSM for PCI Express Slot Information
* The UUID in _DSM in this context is
* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
@@ -160,6 +120,62 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
buf = aml_buffer(1, byte_list);
aml_append(method, aml_return(buf));
aml_append(dev, method);
+}
+
+void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
+{
+ int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
+ Aml *method, *crs;
+
+ Aml *dev = aml_device("%s", "PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+ aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+ acpi_dsdt_add_pci_route_table(dev, scope, cfg->irq);
+
+ method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(cfg->ecam.base)));
+ aml_append(dev, method);
+
+ Aml *rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
+ nr_pcie_buses));
+ if (cfg->mmio32.size) {
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ cfg->mmio32.base,
+ cfg->mmio32.base + cfg->mmio32.size - 1,
+ 0x0000,
+ cfg->mmio32.size));
+ }
+ if (cfg->pio.size) {
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ AML_ENTIRE_RANGE, 0x0000, 0x0000,
+ cfg->pio.size - 1,
+ cfg->pio.base,
+ cfg->pio.size));
+ }
+ if (cfg->mmio64.size) {
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ cfg->mmio64.base,
+ cfg->mmio64.base + cfg->mmio64.size - 1,
+ 0x0000,
+ cfg->mmio64.size));
+ }
+ aml_append(dev, aml_name_decl("_CRS", rbuf));
+
+ acpi_dsdt_add_pci_osc(dev, scope);
Aml *dev_res0 = aml_device("%s", "RES0");
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-04 19:54 ` Laszlo Ersek
2020-11-03 12:01 ` [PATCH v9 3/8] acpi: Extract crs build form acpi_build.c Jiahui Cen
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
Write the extra roots into the fw_cfg, therefore the uefi could
get the extra roots. Only if the uefi knows there are extra roots,
the config space of devices behind the root could be obtained.
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/arm/virt.c | 8 ++++++++
hw/i386/pc.c | 18 ++----------------
hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
include/hw/nvram/fw_cfg.h | 2 ++
include/hw/pci/pcie_host.h | 4 ++++
5 files changed, 36 insertions(+), 16 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 27dbeb549e..58c3695290 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -78,6 +78,8 @@
#include "hw/virtio/virtio-iommu.h"
#include "hw/char/pl011.h"
#include "qemu/guest-random.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pcie_host.h"
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
@@ -1463,6 +1465,10 @@ void virt_machine_done(Notifier *notifier, void *data)
ARMCPU *cpu = ARM_CPU(first_cpu);
struct arm_boot_info *info = &vms->bootinfo;
AddressSpace *as = arm_boot_address_space(cpu, info);
+ PCIHostState *s = PCI_GET_PCIE_HOST_STATE;
+
+ PCIBus *bus = s->bus;
+ FWCfgState *fw_cfg = vms->fw_cfg;
/*
* If the user provided a dtb, we assume the dynamic sysbus nodes
@@ -1481,6 +1487,8 @@ void virt_machine_done(Notifier *notifier, void *data)
exit(1);
}
+ fw_cfg_write_extra_pci_roots(bus, fw_cfg);
+
virt_acpi_setup(vms);
virt_build_smbios(vms);
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5e6c0023e0..bdd2301d19 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -778,26 +778,12 @@ void pc_machine_done(Notifier *notifier, void *data)
PCMachineState, machine_done);
X86MachineState *x86ms = X86_MACHINE(pcms);
PCIBus *bus = pcms->bus;
+ FWCfgState *fw_cfg = x86ms->fw_cfg;
/* set the number of CPUs */
x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
- if (bus) {
- int extra_hosts = 0;
-
- QLIST_FOREACH(bus, &bus->child, sibling) {
- /* look for expander root buses */
- if (pci_bus_is_root(bus)) {
- extra_hosts++;
- }
- }
- if (extra_hosts && x86ms->fw_cfg) {
- uint64_t *val = g_malloc(sizeof(*val));
- *val = cpu_to_le64(extra_hosts);
- fw_cfg_add_file(x86ms->fw_cfg,
- "etc/extra-pci-roots", val, sizeof(*val));
- }
- }
+ fw_cfg_write_extra_pci_roots(bus, fw_cfg);
acpi_setup();
if (x86ms->fw_cfg) {
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 08539a1aab..33dcbdd31d 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -40,6 +40,7 @@
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "hw/acpi/aml-build.h"
+#include "hw/pci/pci_bus.h"
#define FW_CFG_FILE_SLOTS_DFLT 0x20
@@ -742,6 +743,25 @@ static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
return ptr;
}
+void fw_cfg_write_extra_pci_roots(PCIBus *bus, FWCfgState *s)
+{
+ if (bus) {
+ int extra_hosts = 0;
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ /* look for expander root buses */
+ if (pci_bus_is_root(bus)) {
+ extra_hosts++;
+ }
+ }
+ if (extra_hosts && s) {
+ uint64_t *val = g_malloc(sizeof(*val));
+ *val = cpu_to_le64(extra_hosts);
+ fw_cfg_add_file(s,
+ "etc/extra-pci-roots", val, sizeof(*val));
+ }
+ }
+}
+
void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
{
trace_fw_cfg_add_bytes(key, trace_key_name(key), len);
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 8a9f5738bf..0dc75ba6ca 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -104,6 +104,8 @@ struct FWCfgMemState {
MemoryRegionOps wide_data_ops;
};
+void fw_cfg_write_extra_pci_roots(PCIBus *bus, FWCfgState *s);
+
/**
* fw_cfg_add_bytes:
* @s: fw_cfg device being modified
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 076457b270..12f48ddd59 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -27,6 +27,10 @@
#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
OBJECT_DECLARE_SIMPLE_TYPE(PCIExpressHost, PCIE_HOST_BRIDGE)
+#define PCI_GET_PCIE_HOST_STATE \
+ OBJECT_CHECK(PCIHostState, \
+ object_resolve_path_type("", "pcie-host-bridge", NULL), \
+ TYPE_PCIE_HOST_BRIDGE)
#define PCIE_HOST_MCFG_BASE "MCFG"
#define PCIE_HOST_MCFG_SIZE "mcfg_size"
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 3/8] acpi: Extract crs build form acpi_build.c
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 4/8] acpi: Refactor the source of host bridge and build tables for pxb Jiahui Cen
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
Extract crs build form acpi_build.c, the function could also be used
to build the crs for pxbs for arm. The resources are composed by two parts:
1. The bar space of pci-bridge/pcie-root-ports
2. The resources needed by devices behind PXBs.
The base and limit of memory/io are obtained from the config via two APIs:
pci_bridge_get_base and pci_bridge_get_limit
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/acpi/aml-build.c | 273 +++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 293 ------------------------------------
include/hw/acpi/aml-build.h | 25 +++
3 files changed, 298 insertions(+), 293 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 3792ba96ce..8b06d1315f 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -27,6 +27,9 @@
#include "sysemu/numa.h"
#include "hw/boards.h"
#include "hw/acpi/tpm.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_bridge.h"
static GArray *build_alloc_array(void)
{
@@ -55,6 +58,125 @@ static void build_append_array(GArray *array, GArray *val)
#define ACPI_NAMESEG_LEN 4
+void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
+{
+ CrsRangeEntry *entry;
+
+ entry = g_malloc(sizeof(*entry));
+ entry->base = base;
+ entry->limit = limit;
+
+ g_ptr_array_add(ranges, entry);
+}
+
+static void crs_range_free(gpointer data)
+{
+ CrsRangeEntry *entry = (CrsRangeEntry *)data;
+ g_free(entry);
+}
+
+void crs_range_set_init(CrsRangeSet *range_set)
+{
+ range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_64bit_ranges =
+ g_ptr_array_new_with_free_func(crs_range_free);
+}
+
+void crs_range_set_free(CrsRangeSet *range_set)
+{
+ g_ptr_array_free(range_set->io_ranges, true);
+ g_ptr_array_free(range_set->mem_ranges, true);
+ g_ptr_array_free(range_set->mem_64bit_ranges, true);
+}
+
+static gint crs_range_compare(gconstpointer a, gconstpointer b)
+{
+ CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
+ CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
+
+ if (entry_a->base < entry_b->base) {
+ return -1;
+ } else if (entry_a->base > entry_b->base) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/*
+ * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
+ * interval, computes the 'free' ranges from the same interval.
+ * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
+ * will return { [base - a1], [a2 - b1], [b2 - limit] }.
+ */
+void crs_replace_with_free_ranges(GPtrArray *ranges,
+ uint64_t start, uint64_t end)
+{
+ GPtrArray *free_ranges = g_ptr_array_new();
+ uint64_t free_base = start;
+ int i;
+
+ g_ptr_array_sort(ranges, crs_range_compare);
+ for (i = 0; i < ranges->len; i++) {
+ CrsRangeEntry *used = g_ptr_array_index(ranges, i);
+
+ if (free_base < used->base) {
+ crs_range_insert(free_ranges, free_base, used->base - 1);
+ }
+
+ free_base = used->limit + 1;
+ }
+
+ if (free_base < end) {
+ crs_range_insert(free_ranges, free_base, end);
+ }
+
+ g_ptr_array_set_size(ranges, 0);
+ for (i = 0; i < free_ranges->len; i++) {
+ g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
+ }
+
+ g_ptr_array_free(free_ranges, true);
+}
+
+static void crs_range_merge(GPtrArray *range)
+{
+ GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
+ CrsRangeEntry *entry;
+ uint64_t range_base, range_limit;
+ int i;
+
+ if (!range->len) {
+ return;
+ }
+
+ g_ptr_array_sort(range, crs_range_compare);
+
+ entry = g_ptr_array_index(range, 0);
+ range_base = entry->base;
+ range_limit = entry->limit;
+ for (i = 1; i < range->len; i++) {
+ entry = g_ptr_array_index(range, i);
+ if (entry->base - 1 == range_limit) {
+ range_limit = entry->limit;
+ } else {
+ crs_range_insert(tmp, range_base, range_limit);
+ range_base = entry->base;
+ range_limit = entry->limit;
+ }
+ }
+ crs_range_insert(tmp, range_base, range_limit);
+
+ g_ptr_array_set_size(range, 0);
+ for (i = 0; i < tmp->len; i++) {
+ entry = g_ptr_array_index(tmp, i);
+ crs_range_insert(range, entry->base, entry->limit);
+ }
+ g_ptr_array_free(tmp, true);
+}
+
+
static void
build_append_nameseg(GArray *array, const char *seg)
{
@@ -1951,6 +2073,157 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL);
}
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
+{
+ Aml *crs = aml_resource_template();
+ CrsRangeSet temp_range_set;
+ CrsRangeEntry *entry;
+ uint8_t max_bus = pci_bus_num(host->bus);
+ uint8_t type;
+ int devfn;
+ int i;
+
+ crs_range_set_init(&temp_range_set);
+ for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
+ uint64_t range_base, range_limit;
+ PCIDevice *dev = host->bus->devices[devfn];
+
+ if (!dev) {
+ continue;
+ }
+
+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
+ PCIIORegion *r = &dev->io_regions[i];
+
+ range_base = r->addr;
+ range_limit = r->addr + r->size - 1;
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (!range_base || range_base > range_limit) {
+ continue;
+ }
+
+ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
+ } else { /* "memory" */
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ }
+ }
+
+ type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
+ if (type == PCI_HEADER_TYPE_BRIDGE) {
+ uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
+ if (subordinate > max_bus) {
+ max_bus = subordinate;
+ }
+
+ range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
+ range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
+ }
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
+ }
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
+ }
+ }
+ }
+
+ crs_range_merge(temp_range_set.io_ranges);
+ for (i = 0; i < temp_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.io_ranges, i);
+ aml_append(crs,
+ aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
+ }
+
+ crs_range_merge(temp_range_set.mem_ranges);
+ for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
+ aml_append(crs,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
+ }
+
+ crs_range_merge(temp_range_set.mem_64bit_ranges);
+ for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
+ aml_append(crs,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->mem_64bit_ranges,
+ entry->base, entry->limit);
+ }
+
+ crs_range_set_free(&temp_range_set);
+
+ aml_append(crs,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0,
+ pci_bus_num(host->bus),
+ max_bus,
+ 0,
+ max_bus - pci_bus_num(host->bus) + 1));
+
+ return crs;
+}
+
/* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */
static Aml *aml_serial_bus_device(uint8_t serial_bus_type, uint8_t flags,
uint16_t type_flags,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4f66642d88..170e1f23d9 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -616,299 +616,6 @@ static Aml *build_prt(bool is_pci0_prt)
return method;
}
-typedef struct CrsRangeEntry {
- uint64_t base;
- uint64_t limit;
-} CrsRangeEntry;
-
-static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
-{
- CrsRangeEntry *entry;
-
- entry = g_malloc(sizeof(*entry));
- entry->base = base;
- entry->limit = limit;
-
- g_ptr_array_add(ranges, entry);
-}
-
-static void crs_range_free(gpointer data)
-{
- CrsRangeEntry *entry = (CrsRangeEntry *)data;
- g_free(entry);
-}
-
-typedef struct CrsRangeSet {
- GPtrArray *io_ranges;
- GPtrArray *mem_ranges;
- GPtrArray *mem_64bit_ranges;
- } CrsRangeSet;
-
-static void crs_range_set_init(CrsRangeSet *range_set)
-{
- range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_64bit_ranges =
- g_ptr_array_new_with_free_func(crs_range_free);
-}
-
-static void crs_range_set_free(CrsRangeSet *range_set)
-{
- g_ptr_array_free(range_set->io_ranges, true);
- g_ptr_array_free(range_set->mem_ranges, true);
- g_ptr_array_free(range_set->mem_64bit_ranges, true);
-}
-
-static gint crs_range_compare(gconstpointer a, gconstpointer b)
-{
- CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
- CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
-
- if (entry_a->base < entry_b->base) {
- return -1;
- } else if (entry_a->base > entry_b->base) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/*
- * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
- * interval, computes the 'free' ranges from the same interval.
- * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
- * will return { [base - a1], [a2 - b1], [b2 - limit] }.
- */
-static void crs_replace_with_free_ranges(GPtrArray *ranges,
- uint64_t start, uint64_t end)
-{
- GPtrArray *free_ranges = g_ptr_array_new();
- uint64_t free_base = start;
- int i;
-
- g_ptr_array_sort(ranges, crs_range_compare);
- for (i = 0; i < ranges->len; i++) {
- CrsRangeEntry *used = g_ptr_array_index(ranges, i);
-
- if (free_base < used->base) {
- crs_range_insert(free_ranges, free_base, used->base - 1);
- }
-
- free_base = used->limit + 1;
- }
-
- if (free_base < end) {
- crs_range_insert(free_ranges, free_base, end);
- }
-
- g_ptr_array_set_size(ranges, 0);
- for (i = 0; i < free_ranges->len; i++) {
- g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
- }
-
- g_ptr_array_free(free_ranges, true);
-}
-
-/*
- * crs_range_merge - merges adjacent ranges in the given array.
- * Array elements are deleted and replaced with the merged ranges.
- */
-static void crs_range_merge(GPtrArray *range)
-{
- GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
- CrsRangeEntry *entry;
- uint64_t range_base, range_limit;
- int i;
-
- if (!range->len) {
- return;
- }
-
- g_ptr_array_sort(range, crs_range_compare);
-
- entry = g_ptr_array_index(range, 0);
- range_base = entry->base;
- range_limit = entry->limit;
- for (i = 1; i < range->len; i++) {
- entry = g_ptr_array_index(range, i);
- if (entry->base - 1 == range_limit) {
- range_limit = entry->limit;
- } else {
- crs_range_insert(tmp, range_base, range_limit);
- range_base = entry->base;
- range_limit = entry->limit;
- }
- }
- crs_range_insert(tmp, range_base, range_limit);
-
- g_ptr_array_set_size(range, 0);
- for (i = 0; i < tmp->len; i++) {
- entry = g_ptr_array_index(tmp, i);
- crs_range_insert(range, entry->base, entry->limit);
- }
- g_ptr_array_free(tmp, true);
-}
-
-static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
-{
- Aml *crs = aml_resource_template();
- CrsRangeSet temp_range_set;
- CrsRangeEntry *entry;
- uint8_t max_bus = pci_bus_num(host->bus);
- uint8_t type;
- int devfn;
- int i;
-
- crs_range_set_init(&temp_range_set);
- for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
- uint64_t range_base, range_limit;
- PCIDevice *dev = host->bus->devices[devfn];
-
- if (!dev) {
- continue;
- }
-
- for (i = 0; i < PCI_NUM_REGIONS; i++) {
- PCIIORegion *r = &dev->io_regions[i];
-
- range_base = r->addr;
- range_limit = r->addr + r->size - 1;
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (!range_base || range_base > range_limit) {
- continue;
- }
-
- if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- } else { /* "memory" */
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges, range_base,
- range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
- }
-
- type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
- if (type == PCI_HEADER_TYPE_BRIDGE) {
- uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
- if (subordinate > max_bus) {
- max_bus = subordinate;
- }
-
- range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
- range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
- }
- }
-
- crs_range_merge(temp_range_set.io_ranges);
- for (i = 0; i < temp_range_set.io_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.io_ranges, i);
- aml_append(crs,
- aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
- AML_POS_DECODE, AML_ENTIRE_RANGE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_ranges);
- for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
- assert(entry->limit <= UINT32_MAX &&
- (entry->limit - entry->base + 1) <= UINT32_MAX);
- aml_append(crs,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_64bit_ranges);
- for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
- aml_append(crs,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_64bit_ranges,
- entry->base, entry->limit);
- }
-
- crs_range_set_free(&temp_range_set);
-
- aml_append(crs,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0,
- pci_bus_num(host->bus),
- max_bus,
- 0,
- max_bus - pci_bus_num(host->bus) + 1));
-
- return crs;
-}
-
static void build_hpet_aml(Aml *table)
{
Aml *crs;
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index fe0055fffb..2d3b2f2c6f 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -224,6 +224,20 @@ struct AcpiBuildTables {
BIOSLinker *linker;
} AcpiBuildTables;
+typedef
+struct CrsRangeEntry {
+ uint64_t base;
+ uint64_t limit;
+} CrsRangeEntry;
+
+typedef
+struct CrsRangeSet {
+ GPtrArray *io_ranges;
+ GPtrArray *mem_ranges;
+ GPtrArray *mem_64bit_ranges;
+} CrsRangeSet;
+
+
/*
* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors
* Serial Bus Type
@@ -432,6 +446,17 @@ build_append_gas_from_struct(GArray *table, const struct AcpiGenericAddress *s)
s->access_width, s->address);
}
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
+
+void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit);
+
+void crs_replace_with_free_ranges(GPtrArray *ranges,
+ uint64_t start, uint64_t end);
+
+void crs_range_set_init(CrsRangeSet *range_set);
+
+void crs_range_set_free(CrsRangeSet *range_set);
+
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 4/8] acpi: Refactor the source of host bridge and build tables for pxb
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (2 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 3/8] acpi: Extract crs build form acpi_build.c Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 5/8] acpi: Align the size to 128k Jiahui Cen
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
The resources of pxbs are obtained by crs_build and the resources
used by pxbs would be moved from the resources defined for host-bridge.
The resources for pxb are composed of following two parts:
1. The bar space of the pci-bridge/pcie-root-port behined it
2. The config space of devices behind it.
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/arm/virt-acpi-build.c | 5 +-
hw/pci-host/gpex-acpi.c | 129 ++++++++++++++++++++++++++++++++-------
2 files changed, 111 insertions(+), 23 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9747a6458f..fd9c2007c0 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -153,7 +153,8 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
- uint32_t irq, bool use_highmem, bool highmem_ecam)
+ uint32_t irq, bool use_highmem, bool highmem_ecam,
+ VirtMachineState *vms)
{
int ecam_id = VIRT_ECAM_ID(highmem_ecam);
struct GPEXConfig cfg = {
@@ -609,7 +610,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
- vms->highmem, vms->highmem_ecam);
+ vms->highmem, vms->highmem_ecam, vms);
if (vms->acpi_dev) {
build_ged_aml(scope, "\\_SB."GED_DEVICE,
HOTPLUG_HANDLER(vms->acpi_dev),
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 86ddb52cbd..b5436c7128 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -1,6 +1,10 @@
#include "qemu/osdep.h"
#include "hw/acpi/aml-build.h"
#include "hw/pci-host/gpex.h"
+#include "hw/arm/virt.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pcie_host.h"
static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope, uint32_t irq)
{
@@ -125,9 +129,69 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope)
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
{
int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
- Aml *method, *crs;
+ Aml *method, *crs, *dev_pxb;
+ int i;
+ CrsRangeEntry *entry;
+ CrsRangeSet crs_range_set;
+
+ crs_range_set_init(&crs_range_set);
Aml *dev = aml_device("%s", "PCI0");
+ PCIHostState *s = PCI_GET_PCIE_HOST_STATE;
+
+ PCIBus *bus = s->bus;
+ /* start to construct the tables for pxb */
+ if (bus) {
+ QLIST_FOREACH(bus, &bus->child, sibling) {
+ uint8_t bus_num = pci_bus_num(bus);
+ uint8_t numa_node = pci_bus_numa_node(bus);
+
+ if (!pci_bus_is_root(bus)) {
+ continue;
+ }
+ /*
+ * 0 - (nr_pcie_buses - 1) is the bus range for the main
+ * host-bridge and it equals the MIN of the
+ * busNr defined for pxb-pcie.
+ */
+ if (bus_num < nr_pcie_buses) {
+ nr_pcie_buses = bus_num;
+ }
+
+ dev_pxb = aml_device("PC%.02X", bus_num);
+ aml_append(dev_pxb, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev_pxb, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev_pxb, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev_pxb, aml_name_decl("_CCA", aml_int(1)));
+ aml_append(dev_pxb, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev_pxb, aml_name_decl("_BBN", aml_int(bus_num)));
+ aml_append(dev_pxb, aml_name_decl("_UID", aml_int(bus_num)));
+ aml_append(dev_pxb,
+ aml_name_decl("_STR", aml_unicode("pxb Device")));
+ if (numa_node != NUMA_NODE_UNASSIGNED) {
+ method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(numa_node)));
+ aml_append(dev_pxb, method);
+ }
+
+ acpi_dsdt_add_pci_route_table(dev_pxb, scope, cfg->irq);
+
+ /*
+ * Resources defined for PXBs are composed by the folling parts:
+ * 1. The resources the pci-brige/pcie-root-port need.
+ * 2. The resources the devices behind pxb need.
+ */
+ crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
+ aml_append(dev_pxb, aml_name_decl("_CRS", crs));
+
+ acpi_dsdt_add_pci_osc(dev_pxb, scope);
+
+ aml_append(scope, dev_pxb);
+
+ }
+ }
+
+ /* tables for the main */
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
@@ -147,32 +211,53 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
nr_pcie_buses));
+
+ /*
+ * Remove the resources used by PXBs.
+ */
if (cfg->mmio32.size) {
- aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio32.base,
- cfg->mmio32.base + cfg->mmio32.size - 1,
- 0x0000,
- cfg->mmio32.size));
+ crs_replace_with_free_ranges(crs_range_set.mem_ranges,
+ cfg->mmio32.base,
+ cfg->mmio32.base + cfg->mmio32.size - 1);
+ for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ entry->base, entry->limit,
+ 0x0000, entry->limit - entry->base + 1));
+ }
}
+
if (cfg->pio.size) {
- aml_append(rbuf,
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000,
- cfg->pio.size - 1,
- cfg->pio.base,
- cfg->pio.size));
+ crs_replace_with_free_ranges(crs_range_set.io_ranges,
+ 0x0000,
+ cfg->pio.size - 1);
+ for (i = 0; i < crs_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.io_ranges, i);
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ AML_ENTIRE_RANGE, 0x0000, entry->base,
+ entry->limit, cfg->pio.base,
+ entry->limit - entry->base + 1));
+ }
}
+
if (cfg->mmio64.size) {
- aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio64.base,
- cfg->mmio64.base + cfg->mmio64.size - 1,
- 0x0000,
- cfg->mmio64.size));
+ crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
+ cfg->mmio64.base,
+ cfg->mmio64.base + cfg->mmio64.size - 1);
+ for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ entry->base,
+ entry->limit, 0x0000,
+ entry->limit - entry->base + 1));
+ }
}
+
aml_append(dev, aml_name_decl("_CRS", rbuf));
acpi_dsdt_add_pci_osc(dev, scope);
@@ -190,4 +275,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev_res0, aml_name_decl("_CRS", crs));
aml_append(dev, dev_res0);
aml_append(scope, dev);
+
+ crs_range_set_free(&crs_range_set);
}
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 5/8] acpi: Align the size to 128k
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (3 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 4/8] acpi: Refactor the source of host bridge and build tables for pxb Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 6/8] unit-test: The files changed Jiahui Cen
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
If table size is changed between virt_acpi_build and
virt_acpi_build_update, the table size would not be updated to
UEFI, therefore, just align the size to 128kb, which is enough
and same with x86. It would warn if 64k is not enough and the
align size should be updated.
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/arm/virt-acpi-build.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index fd9c2007c0..7f57ab6938 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -57,6 +57,8 @@
#define ARM_SPI_BASE 32
+#define ACPI_BUILD_TABLE_SIZE 0x20000
+
static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
{
uint16_t i;
@@ -655,6 +657,15 @@ struct AcpiBuildState {
bool patched;
} AcpiBuildState;
+static void acpi_align_size(GArray *blob, unsigned align)
+{
+ /*
+ * Align size to multiple of given size. This reduces the chance
+ * we need to change size in the future (breaking cross version migration).
+ */
+ g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
+}
+
static
void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
{
@@ -742,6 +753,20 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
}
+ /*
+ * The align size is 128, warn if 64k is not enough therefore
+ * the align size could be resized.
+ */
+ if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
+ warn_report("ACPI table size %u exceeds %d bytes,"
+ " migration may not work",
+ tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
+ error_printf("Try removing CPUs, NUMA nodes, memory slots"
+ " or PCI bridges.");
+ }
+ acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
+
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 6/8] unit-test: The files changed.
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (4 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 5/8] acpi: Align the size to 128k Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 7/8] unit-test: Add testcase for pxb Jiahui Cen
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
The unit-test is seperated into three patches:
1. The files changed and list in bios-tables-test-allowed-diff.h
2. The unit-test
3. The binary file and clear bios-tables-test-allowed-diff.h
The ASL diff would also be listed.
Sice there are 1000+lines diff, some changes would be omitted.
* Original Table Header:
* Signature "DSDT"
- * Length 0x000014BB (5307)
+ * Length 0x00001E7A (7802)
* Revision 0x02
- * Checksum 0xD1
+ * Checksum 0x57
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
+ Device (PC80)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, 0x80) // _BBN: BIOS Bus Number
+ Name (_UID, 0x80) // _UID: Unique ID
+ Name (_STR, Unicode ("pxb Device")) // _STR: Description String
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
Packages are omitted.
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ }
+ })
+ Device (GSI0)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
GSI1,2,3 are omitted.
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PC80._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PC80._OSC.CDW3 */
+ CTRL &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PC80.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
DSM is are omitted
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
- 0x00FF, // Range Maximum
+ 0x007F, // Range Maximum
0x0000, // Translation Offset
- 0x0100, // Length
+ 0x0080, // Length
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..90c53925fc 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/DSDT.pxb",
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 7/8] unit-test: Add testcase for pxb
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (5 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 6/8] unit-test: The files changed Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 8/8] unit-test: Add the binary file and clear diff.h Jiahui Cen
2020-11-05 7:35 ` [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Gerd Hoffmann
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
Add testcase for pxb to make sure the ACPI table is correct for guest.
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/qtest/bios-tables-test.c | 58 ++++++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index f23a5335a8..64a9a772ee 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -671,12 +671,21 @@ static void test_acpi_one(const char *params, test_data *data)
* TODO: convert '-drive if=pflash' to new syntax (see e33763be7cd3)
* when arm/virt boad starts to support it.
*/
- args = g_strdup_printf("-machine %s %s -accel tcg -nodefaults -nographic "
- "-drive if=pflash,format=raw,file=%s,readonly "
- "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s",
- data->machine, data->tcg_only ? "" : "-accel kvm",
- data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : "");
-
+ if (data->cd) {
+ args = g_strdup_printf("-machine %s %s -accel tcg "
+ "-nodefaults -nographic "
+ "-drive if=pflash,format=raw,file=%s,readonly "
+ "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : "");
+ } else {
+ args = g_strdup_printf("-machine %s %s -accel tcg "
+ "-nodefaults -nographic "
+ "-drive if=pflash,format=raw,file=%s,readonly "
+ "-drive if=pflash,format=raw,file=%s,snapshot=on %s",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ data->uefi_fl1, data->uefi_fl2, params ? params : "");
+ }
} else {
args = g_strdup_printf("-machine %s %s -accel tcg "
"-net none -display none %s "
@@ -1176,6 +1185,40 @@ static void test_acpi_virt_tcg_numamem(void)
}
+#ifdef CONFIG_PXB
+static void test_acpi_virt_tcg_pxb(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+ /*
+ * While using -cdrom, the cdrom would auto plugged into pxb-pcie,
+ * the reason is the bus of pxb-pcie is also root bus, it would lead
+ * to the error only PCI/PCIE bridge could plug onto pxb.
+ * Therefore,thr cdrom is defined and plugged onto the scsi controller
+ * to solve the conflicts.
+ */
+ data.variant = ".pxb";
+ test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
+ " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
+ " -drive file="
+ "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
+ "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
+ " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
+ "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
+ " -cpu cortex-a57"
+ " -device pxb-pcie,bus_nr=128",
+ &data);
+
+ free_test_data(&data);
+}
+#endif
+
static void test_acpi_tcg_acpi_hmat(const char *machine)
{
test_data data;
@@ -1287,6 +1330,9 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
+#ifdef CONFIG_PXB
+ qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
+#endif
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 8/8] unit-test: Add the binary file and clear diff.h
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (6 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 7/8] unit-test: Add testcase for pxb Jiahui Cen
@ 2020-11-03 12:01 ` Jiahui Cen
2020-11-05 7:35 ` [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Gerd Hoffmann
8 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-03 12:01 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, peter.maydell, Jiahui Cen, berrange, mst,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
From: Yubo Miao <miaoyubo@huawei.com>
Add the binary file DSDT.pxb and clear bios-tables-test-allowed-diff.h
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 7802 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
create mode 100644 tests/data/acpi/virt/DSDT.pxb
diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb
new file mode 100644
index 0000000000000000000000000000000000000000..d5f0533a02d62bc2ae2db9b9de9484e5c06652fe
GIT binary patch
literal 7802
zcmeI1%WoT16o;=LiS6+tw&OgUms2Pe&&rRcNlRN|kDbINPK+mQkW$GN2t>&y5*4DY
z5GE1@x}%ZUunAHY{255B*s){5x*Prhb`0mvok@O&o()@MN3!S4-1E)-#wYff>!#D(
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HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 90c53925fc..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/DSDT.pxb",
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-03 12:01 ` [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg Jiahui Cen
@ 2020-11-04 19:54 ` Laszlo Ersek
2020-11-04 20:05 ` Laszlo Ersek
0 siblings, 1 reply; 15+ messages in thread
From: Laszlo Ersek @ 2020-11-04 19:54 UTC (permalink / raw)
To: Jiahui Cen, qemu-devel
Cc: xieyingtai, peter.maydell, berrange, mst, xiexiangyou,
shannon.zhaosl, miaoyubo, imammedo
+Marcel
On 11/03/20 13:01, Jiahui Cen wrote:
> From: Yubo Miao <miaoyubo@huawei.com>
>
> Write the extra roots into the fw_cfg, therefore the uefi could
> get the extra roots. Only if the uefi knows there are extra roots,
> the config space of devices behind the root could be obtained.
>
> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
> ---
> hw/arm/virt.c | 8 ++++++++
> hw/i386/pc.c | 18 ++----------------
> hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
> include/hw/nvram/fw_cfg.h | 2 ++
> include/hw/pci/pcie_host.h | 4 ++++
> 5 files changed, 36 insertions(+), 16 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 27dbeb549e..58c3695290 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -78,6 +78,8 @@
> #include "hw/virtio/virtio-iommu.h"
> #include "hw/char/pl011.h"
> #include "qemu/guest-random.h"
> +#include "hw/pci/pci_bus.h"
> +#include "hw/pci/pcie_host.h"
>
> #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
> static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
> @@ -1463,6 +1465,10 @@ void virt_machine_done(Notifier *notifier, void *data)
> ARMCPU *cpu = ARM_CPU(first_cpu);
> struct arm_boot_info *info = &vms->bootinfo;
> AddressSpace *as = arm_boot_address_space(cpu, info);
> + PCIHostState *s = PCI_GET_PCIE_HOST_STATE;
(1) Not too happy about this new macro.
For pc/q35, see commit 81ed6482a347 ("hw/i386: extend pxb query for all
PC machines", 2015-12-22).
Any reason the same approach cannot work for "virt"? (I.e., saving root
bus 0 in "vms", like we do now in pc_init1().)
> +
> + PCIBus *bus = s->bus;
> + FWCfgState *fw_cfg = vms->fw_cfg;
(2) the helper variables "bus" and "fw_cfg" are almost entirely useless
(they don't save any work whatsoever); please just pass "vms->bus" and
"vms->fw_cfg" to the new helper function below.
>
> /*
> * If the user provided a dtb, we assume the dynamic sysbus nodes
> @@ -1481,6 +1487,8 @@ void virt_machine_done(Notifier *notifier, void *data)
> exit(1);
> }
>
> + fw_cfg_write_extra_pci_roots(bus, fw_cfg);
> +
> virt_acpi_setup(vms);
> virt_build_smbios(vms);
> }
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 5e6c0023e0..bdd2301d19 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -778,26 +778,12 @@ void pc_machine_done(Notifier *notifier, void *data)
> PCMachineState, machine_done);
> X86MachineState *x86ms = X86_MACHINE(pcms);
> PCIBus *bus = pcms->bus;
> + FWCfgState *fw_cfg = x86ms->fw_cfg;
(3) Same as (2): "fw_cfg" is useless (especially because you leave other
prior uses of "x86ms->fw_cfg" in this function untouched); furthermore,
the existent "bus" shorthand *becomes* useless with the extraction of
fw_cfg_write_extra_pci_roots(), so "bus" should be deleted when the bus
walking is factored out.
>
> /* set the number of CPUs */
> x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
>
> - if (bus) {
> - int extra_hosts = 0;
> -
> - QLIST_FOREACH(bus, &bus->child, sibling) {
> - /* look for expander root buses */
> - if (pci_bus_is_root(bus)) {
> - extra_hosts++;
> - }
> - }
> - if (extra_hosts && x86ms->fw_cfg) {
> - uint64_t *val = g_malloc(sizeof(*val));
> - *val = cpu_to_le64(extra_hosts);
> - fw_cfg_add_file(x86ms->fw_cfg,
> - "etc/extra-pci-roots", val, sizeof(*val));
> - }
> - }
> + fw_cfg_write_extra_pci_roots(bus, fw_cfg);
>
> acpi_setup();
> if (x86ms->fw_cfg) {
> diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
> index 08539a1aab..33dcbdd31d 100644
> --- a/hw/nvram/fw_cfg.c
> +++ b/hw/nvram/fw_cfg.c
> @@ -40,6 +40,7 @@
> #include "qemu/cutils.h"
> #include "qapi/error.h"
> #include "hw/acpi/aml-build.h"
> +#include "hw/pci/pci_bus.h"
>
> #define FW_CFG_FILE_SLOTS_DFLT 0x20
>
> @@ -742,6 +743,25 @@ static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
> return ptr;
> }
>
> +void fw_cfg_write_extra_pci_roots(PCIBus *bus, FWCfgState *s)
> +{
> + if (bus) {
> + int extra_hosts = 0;
(4) I don't understand why we need to remove the empty line after this
declaration. It helps understanding if we have an empty line between
declarations and code.
(5) Simpler to return at once if bus is NULL; the extra nesting is
unjustified in this helper function, which has its own top-level scope.
> + QLIST_FOREACH(bus, &bus->child, sibling) {
> + /* look for expander root buses */
> + if (pci_bus_is_root(bus)) {
> + extra_hosts++;
> + }
> + }
> + if (extra_hosts && s) {
> + uint64_t *val = g_malloc(sizeof(*val));
> + *val = cpu_to_le64(extra_hosts);
> + fw_cfg_add_file(s,
> + "etc/extra-pci-roots", val, sizeof(*val));
> + }
> + }
> +}
> +
> void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
> {
> trace_fw_cfg_add_bytes(key, trace_key_name(key), len);
> diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
> index 8a9f5738bf..0dc75ba6ca 100644
> --- a/include/hw/nvram/fw_cfg.h
> +++ b/include/hw/nvram/fw_cfg.h
> @@ -104,6 +104,8 @@ struct FWCfgMemState {
> MemoryRegionOps wide_data_ops;
> };
>
> +void fw_cfg_write_extra_pci_roots(PCIBus *bus, FWCfgState *s);
> +
> /**
> * fw_cfg_add_bytes:
> * @s: fw_cfg device being modified
(6) Missing documentation (interface contract).
(7) I suggest calling the function fw_cfg_add_extra_pci_roots(), to
conform to the fw_cfg_add_* pattern.
(8) Also, likely not the best place to introduce this function in the
header file. The function contracts tend to grow in complexity towards
the end of the file. (Note that this applies to the "hw/nvram/fw_cfg.c"
file as well.)
> diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
> index 076457b270..12f48ddd59 100644
> --- a/include/hw/pci/pcie_host.h
> +++ b/include/hw/pci/pcie_host.h
> @@ -27,6 +27,10 @@
>
> #define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
> OBJECT_DECLARE_SIMPLE_TYPE(PCIExpressHost, PCIE_HOST_BRIDGE)
> +#define PCI_GET_PCIE_HOST_STATE \
> + OBJECT_CHECK(PCIHostState, \
> + object_resolve_path_type("", "pcie-host-bridge", NULL), \
> + TYPE_PCIE_HOST_BRIDGE)
>
> #define PCIE_HOST_MCFG_BASE "MCFG"
> #define PCIE_HOST_MCFG_SIZE "mcfg_size"
>
(9) According to (1), I suggest dropping this hunk.
(10) Please split this patch into two patches; the first patch should
factor fw_cfg_add_extra_pci_roots() out of pc_machine_done(), while the
second patch should hook it into the "virt" machine.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-04 19:54 ` Laszlo Ersek
@ 2020-11-04 20:05 ` Laszlo Ersek
2020-11-04 21:11 ` Philippe Mathieu-Daudé
2020-11-05 3:07 ` Jiahui Cen
0 siblings, 2 replies; 15+ messages in thread
From: Laszlo Ersek @ 2020-11-04 20:05 UTC (permalink / raw)
To: Jiahui Cen, qemu-devel
Cc: xieyingtai, peter.maydell, berrange, mst, xiexiangyou,
shannon.zhaosl, miaoyubo, Gerd Hoffmann, imammedo,
Philippe Mathieu-Daudé
+Phil, +Gerd
On 11/04/20 20:54, Laszlo Ersek wrote:
> +Marcel
>
> On 11/03/20 13:01, Jiahui Cen wrote:
>> From: Yubo Miao <miaoyubo@huawei.com>
>>
>> Write the extra roots into the fw_cfg, therefore the uefi could
>> get the extra roots. Only if the uefi knows there are extra roots,
>> the config space of devices behind the root could be obtained.
>>
>> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
>> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
>> ---
>> hw/arm/virt.c | 8 ++++++++
>> hw/i386/pc.c | 18 ++----------------
>> hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
>> include/hw/nvram/fw_cfg.h | 2 ++
>> include/hw/pci/pcie_host.h | 4 ++++
>> 5 files changed, 36 insertions(+), 16 deletions(-)
I realize I never reacted to this patch before (and we're at v9), so you
might not welcome my feedback at this point.
The explanation why I've only reacted now is the following: there's an
agreement between Phil and myself that Phil handles fw_cfg reviews
primarily, and I review only (or almost only) Phil's patches for fw_cfg.
Furthermore, all versions of this particular patch, as far as I can see,
CC'd me but not Phil. So Phil never knew to look, and I never checked
(this being an fw_cfg patch, per subject line) beyond the author being
Phil or not.
The solution is of course to use the get_maintainer.pl script for
determining reviewers, and adding them with "Cc:" tags to the commit
message. (You also missed Marcel at the least; see my previous
response.) git-send-email is supposed to adhere to those "Cc:" tags.
The reason I've looked now is... I guess I was too tired to remember our
agreement with Phil.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-04 20:05 ` Laszlo Ersek
@ 2020-11-04 21:11 ` Philippe Mathieu-Daudé
2020-11-05 3:07 ` Jiahui Cen
2020-11-05 3:07 ` Jiahui Cen
1 sibling, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-11-04 21:11 UTC (permalink / raw)
To: Laszlo Ersek, Jiahui Cen, qemu-devel
Cc: xieyingtai, peter.maydell, berrange, mst, xiexiangyou,
shannon.zhaosl, miaoyubo, Gerd Hoffmann, imammedo
Hi Laszlo,
On 11/4/20 9:05 PM, Laszlo Ersek wrote:
> +Phil, +Gerd
>
> On 11/04/20 20:54, Laszlo Ersek wrote:
>> +Marcel
>>
>> On 11/03/20 13:01, Jiahui Cen wrote:
>>> From: Yubo Miao <miaoyubo@huawei.com>
>>>
>>> Write the extra roots into the fw_cfg, therefore the uefi could
>>> get the extra roots. Only if the uefi knows there are extra roots,
>>> the config space of devices behind the root could be obtained.
>>>
>>> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
>>> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
>>> ---
>>> hw/arm/virt.c | 8 ++++++++
>>> hw/i386/pc.c | 18 ++----------------
>>> hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
>>> include/hw/nvram/fw_cfg.h | 2 ++
>>> include/hw/pci/pcie_host.h | 4 ++++
>>> 5 files changed, 36 insertions(+), 16 deletions(-)
>
> I realize I never reacted to this patch before (and we're at v9), so you
> might not welcome my feedback at this point.
>
> The explanation why I've only reacted now is the following: there's an
> agreement between Phil and myself that Phil handles fw_cfg reviews
> primarily, and I review only (or almost only) Phil's patches for fw_cfg.
> Furthermore, all versions of this particular patch, as far as I can see,
> CC'd me but not Phil. So Phil never knew to look, and I never checked
> (this being an fw_cfg patch, per subject line) beyond the author being
> Phil or not.
I noticed this patch yesterday too (by luck looking at the cover).
Since we are in freeze, I tagged it for review but postponed it for
in 2 or 3 weeks. Sorry for not mentioning that I would review this
later on the list.
> The solution is of course to use the get_maintainer.pl script for
> determining reviewers, and adding them with "Cc:" tags to the commit
> message. (You also missed Marcel at the least; see my previous
> response.) git-send-email is supposed to adhere to those "Cc:" tags.
>
> The reason I've looked now is... I guess I was too tired to remember our
> agreement with Phil.
>
> Thanks
> Laszlo
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-04 20:05 ` Laszlo Ersek
2020-11-04 21:11 ` Philippe Mathieu-Daudé
@ 2020-11-05 3:07 ` Jiahui Cen
1 sibling, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-05 3:07 UTC (permalink / raw)
To: Laszlo Ersek, qemu-devel
Cc: xieyingtai, peter.maydell, berrange, mst, xiexiangyou,
shannon.zhaosl, miaoyubo, Gerd Hoffmann, imammedo,
Philippe Mathieu-Daudé
On 2020/11/5 4:05, Laszlo Ersek wrote:
> +Phil, +Gerd
>
> On 11/04/20 20:54, Laszlo Ersek wrote:
>> +Marcel
>>
>> On 11/03/20 13:01, Jiahui Cen wrote:
>>> From: Yubo Miao <miaoyubo@huawei.com>
>>>
>>> Write the extra roots into the fw_cfg, therefore the uefi could
>>> get the extra roots. Only if the uefi knows there are extra roots,
>>> the config space of devices behind the root could be obtained.
>>>
>>> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
>>> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
>>> ---
>>> hw/arm/virt.c | 8 ++++++++
>>> hw/i386/pc.c | 18 ++----------------
>>> hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
>>> include/hw/nvram/fw_cfg.h | 2 ++
>>> include/hw/pci/pcie_host.h | 4 ++++
>>> 5 files changed, 36 insertions(+), 16 deletions(-)
>
> I realize I never reacted to this patch before (and we're at v9), so you
> might not welcome my feedback at this point.
Hi Laszlo,
Thanks for your comments. Any feedback is welcomed at any time :)
> The explanation why I've only reacted now is the following: there's an
> agreement between Phil and myself that Phil handles fw_cfg reviews
> primarily, and I review only (or almost only) Phil's patches for fw_cfg.
> Furthermore, all versions of this particular patch, as far as I can see,
> CC'd me but not Phil. So Phil never knew to look, and I never checked
> (this being an fw_cfg patch, per subject line) beyond the author being
> Phil or not.
I did not know the agreement between you and Phil before, and it's
my mistake forgetting to CC Phil. I'll check the CC list in the
future patches.
Thanks
Jiahui
> The solution is of course to use the get_maintainer.pl script for
> determining reviewers, and adding them with "Cc:" tags to the commit
> message. (You also missed Marcel at the least; see my previous
> response.) git-send-email is supposed to adhere to those "Cc:" tags.
>
> The reason I've looked now is... I guess I was too tired to remember our
> agreement with Phil.
>> Thanks
> Laszlo
>
> .
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg
2020-11-04 21:11 ` Philippe Mathieu-Daudé
@ 2020-11-05 3:07 ` Jiahui Cen
0 siblings, 0 replies; 15+ messages in thread
From: Jiahui Cen @ 2020-11-05 3:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: xieyingtai, peter.maydell, berrange, mst, xiexiangyou,
shannon.zhaosl, miaoyubo, Gerd Hoffmann, imammedo, Laszlo Ersek
Hi Phil,
On 2020/11/5 5:11, Philippe Mathieu-Daudé wrote:
> Hi Laszlo,
>
> On 11/4/20 9:05 PM, Laszlo Ersek wrote:
>> +Phil, +Gerd
>>
>> On 11/04/20 20:54, Laszlo Ersek wrote:
>>> +Marcel
>>>
>>> On 11/03/20 13:01, Jiahui Cen wrote:
>>>> From: Yubo Miao <miaoyubo@huawei.com>
>>>>
>>>> Write the extra roots into the fw_cfg, therefore the uefi could
>>>> get the extra roots. Only if the uefi knows there are extra roots,
>>>> the config space of devices behind the root could be obtained.
>>>>
>>>> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
>>>> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
>>>> ---
>>>> hw/arm/virt.c | 8 ++++++++
>>>> hw/i386/pc.c | 18 ++----------------
>>>> hw/nvram/fw_cfg.c | 20 ++++++++++++++++++++
>>>> include/hw/nvram/fw_cfg.h | 2 ++
>>>> include/hw/pci/pcie_host.h | 4 ++++
>>>> 5 files changed, 36 insertions(+), 16 deletions(-)
>>
>> I realize I never reacted to this patch before (and we're at v9), so you
>> might not welcome my feedback at this point.
>>
>> The explanation why I've only reacted now is the following: there's an
>> agreement between Phil and myself that Phil handles fw_cfg reviews
>> primarily, and I review only (or almost only) Phil's patches for fw_cfg.
>> Furthermore, all versions of this particular patch, as far as I can see,
>> CC'd me but not Phil. So Phil never knew to look, and I never checked
>> (this being an fw_cfg patch, per subject line) beyond the author being
>> Phil or not.
>
> I noticed this patch yesterday too (by luck looking at the cover).
> Since we are in freeze, I tagged it for review but postponed it for
> in 2 or 3 weeks. Sorry for not mentioning that I would review this
> later on the list.
Sorry for forgetting to CC you. I'm glad to wait for your review :)
Thanks
Jiahui
>
>> The solution is of course to use the get_maintainer.pl script for
>> determining reviewers, and adding them with "Cc:" tags to the commit
>> message. (You also missed Marcel at the least; see my previous
>> response.) git-send-email is supposed to adhere to those "Cc:" tags.
>>
>> The reason I've looked now is... I guess I was too tired to remember our
>> agreement with Phil.
>>
>> Thanks
>> Laszlo
>>
>
> .
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
` (7 preceding siblings ...)
2020-11-03 12:01 ` [PATCH v9 8/8] unit-test: Add the binary file and clear diff.h Jiahui Cen
@ 2020-11-05 7:35 ` Gerd Hoffmann
8 siblings, 0 replies; 15+ messages in thread
From: Gerd Hoffmann @ 2020-11-05 7:35 UTC (permalink / raw)
To: Jiahui Cen
Cc: xieyingtai, peter.maydell, berrange, mst, qemu-devel,
xiexiangyou, shannon.zhaosl, miaoyubo, imammedo, lersek
Hi,
Looking at the whole series for the first time after being Cc'ed on one
of the patches.
> Currently pxb-pcie is not supported by arm,
> the reason for it is pxb-pcie is not described in DSDT table
> and only one main host bridge is described in acpi tables,
> which means it is not impossible to present different io numas
> for different devices.
I'm wondering whenever it would be easier to just have multiple
gpex devices (one per numa node)?
Also I think you don't have to use the x86-style crs handling.
Just pick address ranges for the new pci root. Linux should
cope just fine. When adding the pci root to the device tree
edk2 can handle this too (might require some firmware tweaks
though).
take care,
Gerd
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2020-11-05 7:36 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-03 12:01 [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 2/8] fw_cfg: Write the extra roots into the fw_cfg Jiahui Cen
2020-11-04 19:54 ` Laszlo Ersek
2020-11-04 20:05 ` Laszlo Ersek
2020-11-04 21:11 ` Philippe Mathieu-Daudé
2020-11-05 3:07 ` Jiahui Cen
2020-11-05 3:07 ` Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 3/8] acpi: Extract crs build form acpi_build.c Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 4/8] acpi: Refactor the source of host bridge and build tables for pxb Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 5/8] acpi: Align the size to 128k Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 6/8] unit-test: The files changed Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 7/8] unit-test: Add testcase for pxb Jiahui Cen
2020-11-03 12:01 ` [PATCH v9 8/8] unit-test: Add the binary file and clear diff.h Jiahui Cen
2020-11-05 7:35 ` [PATCH v9 0/8] pci_expander_brdige:acpi: Support pxb-pcie for ARM Gerd Hoffmann
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