[PATCH 0/2] target/mips: Let cpu_supports_isa() take CPUMIPSState argument

[PATCH 0/2] target/mips: Let cpu_supports_isa() take CPUMIPSState argument

[Philippe Mathieu-Daudé]

Hi Jiaxun,

Here goes the cpu_supports_isa() helper for your bootloader API:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg764582.html

Regards,

Phil.

Philippe Mathieu-Daudé (2):
  target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
  target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument

 target/mips/cpu.h       | 5 +++--
 hw/mips/boston.c        | 4 ++--
 hw/mips/malta.c         | 4 ++--
 target/mips/cpu.c       | 5 +++++
 target/mips/translate.c | 4 ++--
 5 files changed, 14 insertions(+), 8 deletions(-)

-- 
2.26.2

[PATCH 1/2] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()

[Philippe Mathieu-Daudé]

As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type'
name argument, rename them cpu_type_supports_FEAT().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h       | 4 ++--
 hw/mips/boston.c        | 4 ++--
 hw/mips/malta.c         | 4 ++--
 target/mips/translate.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..9c65c87bf99 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1286,8 +1286,8 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
-bool cpu_supports_cps_smp(const char *cpu_type);
-bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
+bool cpu_type_supports_cps_smp(const char *cpu_type);
+bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
 /* mips_int.c */
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 3d40867dc4c..16467ea4752 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -459,12 +459,12 @@ static void boston_mach_init(MachineState *machine)
     s = BOSTON(dev);
     s->mach = machine;
 
-    if (!cpu_supports_cps_smp(machine->cpu_type)) {
+    if (!cpu_type_supports_cps_smp(machine->cpu_type)) {
         error_report("Boston requires CPUs which support CPS");
         exit(1);
     }
 
-    is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
+    is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64);
 
     object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
     object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9d1a3b50b7a..965a952d934 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1204,7 +1204,7 @@ static void create_cps(MachineState *ms, MaltaState *s,
 static void mips_create_cpu(MachineState *ms, MaltaState *s,
                             qemu_irq *cbus_irq, qemu_irq *i8259_irq)
 {
-    if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
+    if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
         create_cps(ms, s, cbus_irq, i8259_irq);
     } else {
         create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
@@ -1308,7 +1308,7 @@ void mips_malta_init(MachineState *machine)
         loaderparams.initrd_filename = initrd_filename;
         kernel_entry = load_kernel();
 
-        if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
+        if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
             write_bootloader(memory_region_get_ram_ptr(bios),
                              bootloader_run_addr, kernel_entry);
         } else {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c64a1bc42e1..b8ed16bb779 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31770,13 +31770,13 @@ void cpu_mips_realize_env(CPUMIPSState *env)
     mvp_init(env, env->cpu_model);
 }
 
-bool cpu_supports_cps_smp(const char *cpu_type)
+bool cpu_type_supports_cps_smp(const char *cpu_type)
 {
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
 
-bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
+bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
 {
     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
     return (mcc->cpu_def->insn_flags & isa) != 0;
-- 
2.26.2

[PATCH 2/2] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument

[Philippe Mathieu-Daudé]

Introduce cpu_supports_isa() which takes a CPUMIPSState
argument, more useful at runtime when the CPU is created
(no need to call the extensive object_class_by_name()).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h | 1 +
 target/mips/cpu.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c65c87bf99..e8bca75f237 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
 bool cpu_type_supports_cps_smp(const char *cpu_type);
+bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b42..687e2680dd1 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 
     return MIPS_CPU(cpu);
 }
+
+bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
+{
+    return (env->cpu_model->insn_flags & isa_mask) != 0;
+}
-- 
2.26.2

Re: [PATCH 0/2] target/mips: Let cpu_supports_isa() take CPUMIPSState argument

[Richard Henderson]

On 12/7/20 3:52 PM, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (2):
>   target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
>   target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 0/2] target/mips: Let cpu_supports_isa() take CPUMIPSState argument

[Philippe Mathieu-Daudé]

On 12/7/20 10:52 PM, Philippe Mathieu-Daudé wrote:
> Hi Jiaxun,
> 
> Here goes the cpu_supports_isa() helper for your bootloader API:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg764582.html
> 
> Regards,
> 
> Phil.
> 
> Philippe Mathieu-Daudé (2):
>   target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
>   target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
> 
>  target/mips/cpu.h       | 5 +++--
>  hw/mips/boston.c        | 4 ++--
>  hw/mips/malta.c         | 4 ++--
>  target/mips/cpu.c       | 5 +++++
>  target/mips/translate.c | 4 ++--
>  5 files changed, 14 insertions(+), 8 deletions(-)

Thanks, series applied to mips-next tree.