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From: Leif Lindholm <leif@nuviainc.com>
To: qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: [PATCH v2 4/5] target/arm: add aarch64 ID register fields to cpu.h
Date: Tue, 15 Dec 2020 11:48:27 +0000	[thread overview]
Message-ID: <20201215114828.18076-5-leif@nuviainc.com> (raw)
In-Reply-To: <20201215114828.18076-1-leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 90ba707b64..efa977eaca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1895,6 +1895,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -1905,11 +1908,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -1923,6 +1933,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -1932,6 +1944,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -1958,6 +1972,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1



  parent reply	other threads:[~2020-12-15 11:54 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-15 11:48 [PATCH v2 0/5] target/arm: various changes to cpu.h Leif Lindholm
2020-12-15 11:48 ` [PATCH v2 1/5] target/arm: fix typo in cpu.h ID_AA64PFR1 field name Leif Lindholm
2020-12-15 12:25   ` Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit Leif Lindholm
2020-12-15 12:29   ` Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h Leif Lindholm
2020-12-15 12:23   ` Laurent Desnogues
2020-12-15 16:49     ` Leif Lindholm
2020-12-17 10:02       ` Laurent Desnogues
2020-12-17 12:10         ` Leif Lindholm
2020-12-17 12:18           ` Laurent Desnogues
2020-12-17 12:24             ` Leif Lindholm
2021-01-07 17:43               ` Peter Maydell
2020-12-15 11:48 ` Leif Lindholm [this message]
2020-12-15 12:28   ` [PATCH v2 4/5] target/arm: add aarch64 ID register fields " Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 5/5] target/arm: add aarch32 " Leif Lindholm
2020-12-15 12:32   ` Laurent Desnogues
2020-12-15 12:11 ` [PATCH v2 0/5] target/arm: various changes " Peter Maydell
2020-12-15 16:14   ` Leif Lindholm

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