From: Leif Lindholm <leif@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 0/5] target/arm: various changes to cpu.h
Date: Tue, 15 Dec 2020 16:14:08 +0000 [thread overview]
Message-ID: <20201215161408.GX1664@vanye> (raw)
In-Reply-To: <CAFEAcA8i6vAaOFPFRPPYjQgj6gnvS_GutH1HBq=trvrz-Ud-2g@mail.gmail.com>
On Tue, Dec 15, 2020 at 12:11:43 +0000, Peter Maydell wrote:
> On Tue, 15 Dec 2020 at 11:48, Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS).
> >
> > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined
> > by the ARM ARM.
> >
> > Third, add field definitions for CLIDR (excepting the Ttype<n> fields, since
> > I was unsure of prefererred naming - Ttype7-Ttype1?).
> >
> > Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c,
> >
> > Lastly, add all ID_ (aarch32) registers/fields.
> >
> > Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be
> > submitting shortly, and some of those features also exist for aarch32.
> >
> > v1->v2:
> > - Correct CCSIDR_EL1 field sizes in 3/5.
> > - Rebase to current master.
>
> What happened to the various Reviewed-by:s that people gave you for
> patches in the v1 series ?
Melted away in excessive multitasking, sigh.
Sorry, v3 coming up.
/
Leif
prev parent reply other threads:[~2020-12-15 16:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 11:48 [PATCH v2 0/5] target/arm: various changes to cpu.h Leif Lindholm
2020-12-15 11:48 ` [PATCH v2 1/5] target/arm: fix typo in cpu.h ID_AA64PFR1 field name Leif Lindholm
2020-12-15 12:25 ` Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit Leif Lindholm
2020-12-15 12:29 ` Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h Leif Lindholm
2020-12-15 12:23 ` Laurent Desnogues
2020-12-15 16:49 ` Leif Lindholm
2020-12-17 10:02 ` Laurent Desnogues
2020-12-17 12:10 ` Leif Lindholm
2020-12-17 12:18 ` Laurent Desnogues
2020-12-17 12:24 ` Leif Lindholm
2021-01-07 17:43 ` Peter Maydell
2020-12-15 11:48 ` [PATCH v2 4/5] target/arm: add aarch64 ID register fields " Leif Lindholm
2020-12-15 12:28 ` Laurent Desnogues
2020-12-15 11:48 ` [PATCH v2 5/5] target/arm: add aarch32 " Leif Lindholm
2020-12-15 12:32 ` Laurent Desnogues
2020-12-15 12:11 ` [PATCH v2 0/5] target/arm: various changes " Peter Maydell
2020-12-15 16:14 ` Leif Lindholm [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201215161408.GX1664@vanye \
--to=leif@nuviainc.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).