From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks
Date: Thu, 17 Dec 2020 22:01:09 -0800 [thread overview]
Message-ID: <20201218060114.3591217-19-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201218060114.3591217-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
---
target/riscv/cpu.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6f032122..47b738c314 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -240,10 +240,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-#ifdef TARGET_RISCV32
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
- (target_ulong)(env->mstatus >> 32));
-#endif
+ if (riscv_cpu_is_32bit(env)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+ (target_ulong)(env->mstatus >> 32));
+ }
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
@@ -356,11 +356,12 @@ static void riscv_cpu_reset(DeviceState *dev)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
-#if defined(TARGET_RISCV32)
- info->print_insn = print_insn_riscv32;
-#elif defined(TARGET_RISCV64)
- info->print_insn = print_insn_riscv64;
-#endif
+ RISCVCPU *cpu = RISCV_CPU(s);
+ if (riscv_cpu_is_32bit(&cpu->env)) {
+ info->print_insn = print_insn_riscv32;
+ } else {
+ info->print_insn = print_insn_riscv64;
+ }
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
--
2.29.2
next prev parent reply other threads:[~2020-12-18 6:07 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 6:00 [PULL 00/23] riscv-to-apply queue Alistair Francis
2020-12-18 6:00 ` [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Alistair Francis
2020-12-18 6:00 ` [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash Alistair Francis
2020-12-18 6:00 ` [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format Alistair Francis
2020-12-18 6:00 ` [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV Alistair Francis
2020-12-18 6:00 ` [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alistair Francis
2020-12-18 6:00 ` [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process Alistair Francis
2020-12-18 6:00 ` [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-18 6:00 ` [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-18 6:01 ` [PULL 09/23] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-18 6:01 ` [PULL 10/23] riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 12/23] hw/riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 13/23] hw/riscv: spike: " Alistair Francis
2020-12-18 6:01 ` [PULL 14/23] hw/riscv: sifive_u: " Alistair Francis
2020-12-18 6:01 ` [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-18 6:01 ` [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-18 6:01 ` [PULL 17/23] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-18 6:01 ` Alistair Francis [this message]
2020-12-18 6:01 ` [PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 20/23] target/riscv: csr: " Alistair Francis
2020-12-18 6:01 ` [PULL 21/23] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-18 6:01 ` [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis
2021-01-10 19:55 ` Peter Maydell
2021-01-15 1:20 ` Alistair Francis
2020-12-18 6:01 ` [PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout Alistair Francis
2020-12-18 13:36 ` [PULL 00/23] riscv-to-apply queue Peter Maydell
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