From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Palmer Dabbelt <palmerdabbelt@google.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs
Date: Thu, 17 Dec 2020 22:00:58 -0800 [thread overview]
Message-ID: <20201218060114.3591217-8-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201218060114.3591217-1-alistair.francis@wdc.com>
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
---
hw/riscv/boot.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d62f3dc758..3c70ac75d7 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -41,7 +41,17 @@
bool riscv_is_32_bit(MachineState *machine)
{
- if (!strncmp(machine->cpu_type, "rv32", 4)) {
+ /*
+ * To determine if the CPU is 32-bit we need to check a few different CPUs.
+ *
+ * If the CPU starts with rv32
+ * If the CPU is a sifive 3 seriries CPU (E31, U34)
+ * If it's the Ibex CPU
+ */
+ if (!strncmp(machine->cpu_type, "rv32", 4) ||
+ (!strncmp(machine->cpu_type, "sifive", 6) &&
+ machine->cpu_type[8] == '3') ||
+ !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
return true;
} else {
return false;
--
2.29.2
next prev parent reply other threads:[~2020-12-18 6:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 6:00 [PULL 00/23] riscv-to-apply queue Alistair Francis
2020-12-18 6:00 ` [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Alistair Francis
2020-12-18 6:00 ` [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash Alistair Francis
2020-12-18 6:00 ` [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format Alistair Francis
2020-12-18 6:00 ` [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV Alistair Francis
2020-12-18 6:00 ` [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alistair Francis
2020-12-18 6:00 ` [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process Alistair Francis
2020-12-18 6:00 ` Alistair Francis [this message]
2020-12-18 6:00 ` [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-18 6:01 ` [PULL 09/23] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-18 6:01 ` [PULL 10/23] riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 12/23] hw/riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 13/23] hw/riscv: spike: " Alistair Francis
2020-12-18 6:01 ` [PULL 14/23] hw/riscv: sifive_u: " Alistair Francis
2020-12-18 6:01 ` [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-18 6:01 ` [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-18 6:01 ` [PULL 17/23] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-18 6:01 ` [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 19/23] target/riscv: cpu_helper: " Alistair Francis
2020-12-18 6:01 ` [PULL 20/23] target/riscv: csr: " Alistair Francis
2020-12-18 6:01 ` [PULL 21/23] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-18 6:01 ` [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis
2021-01-10 19:55 ` Peter Maydell
2021-01-15 1:20 ` Alistair Francis
2020-12-18 6:01 ` [PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout Alistair Francis
2020-12-18 13:36 ` [PULL 00/23] riscv-to-apply queue Peter Maydell
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