* [PATCH v3 0/1] target-riscv: support QMP dump-guest-memory
@ 2021-01-15 1:28 Yifei Jiang
2021-01-15 1:28 ` [PATCH v3 1/1] " Yifei Jiang
0 siblings, 1 reply; 4+ messages in thread
From: Yifei Jiang @ 2021-01-15 1:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: drjones, zhang.zhanghailiang, sagark, kbastian, limingwang,
Yifei Jiang, Alistair.Francis, palmer, fanliang, wu.wubin,
dengkai1
Hi,
This patch supports QMP dump-guest-memory in RISC-V. We tested this
feature by using following command: dump-guest-memory guest.memory.
Then we used the gdb tool to debug guest.memory: gdb vmlinux guest.memory.
The test result is as follow:
1. info registers
ra 0xffffffe0008cb83c 0xffffffe0008cb83c <_raw_spin_lock_irqsave+28>
sp 0xffffffe0012c3f70 0xffffffe0012c3f70
gp 0xffffffe0010d6048 0xffffffe0010d6048 <__compound_literal.109>
tp 0xffffffe00127f200 0xffffffe00127f200
t0 0x1f8 504
t1 0x0 0
t2 0x3fd9bf5c3c 274236136508
fp 0xffffffe0012c3f80 0xffffffe0012c3f80
s1 0xffffffe0010d7228 -137421295064
a0 0x1 1
a1 0xffffffe00127f200 -137419558400
a2 0xffffffe00110a0b8 -137421086536
a3 0x3af32000 989011968
a4 0x35b2 13746
a5 0xffffffe03af6b880 -136449705856
a6 0x1c5d09af00 121820000000
a7 0x54494d45 1414090053
s2 0x1 1
s3 0xffffffe0010d73f0 -137421294608
s4 0x0 0
s5 0x0 0
s6 0x0 0
s7 0xc 12
s8 0x2000 8192
s9 0x80015708 2147571464
s10 0x0 0
s11 0x0 0
t3 0x2257d71 36011377
t4 0x0 0
t5 0x3ab0030 61538352
t6 0x3fffefb3a0 274876838816
pc 0xffffffe000201478 0xffffffe000201478 <arch_cpu_idle+10>
2. x/1024ux 0x80000000
0x80000000: 0x00050433 0x000584b3 0x00060933 0x62c000ef
0x80000010: 0x00050833 0x00040533 0x000485b3 0x00090633
0x80000020: 0x046358fd 0x1d630118 0x08171305 0x08130000
0x80000030: 0x48854868 0x0118282f 0x12081463 0x00000297
0x80000040: 0x48428293 0x00000317 0xfbc30313 0x0062b023
...
Changes since v2
1. Add build-bugs.
Changes since v1
1. Fix the build failure for RISC-V linux user.
Yifei Jiang (1):
target-riscv: support QMP dump-guest-memory
target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 4 +
target/riscv/cpu_bits.h | 1 +
target/riscv/meson.build | 1 +
5 files changed, 210 insertions(+)
create mode 100644 target/riscv/arch_dump.c
--
2.19.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
2021-01-15 1:28 [PATCH v3 0/1] target-riscv: support QMP dump-guest-memory Yifei Jiang
@ 2021-01-15 1:28 ` Yifei Jiang
2021-01-15 2:12 ` Palmer Dabbelt
2021-01-15 14:45 ` Andrew Jones
0 siblings, 2 replies; 4+ messages in thread
From: Yifei Jiang @ 2021-01-15 1:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: drjones, zhang.zhanghailiang, sagark, kbastian, limingwang,
Yifei Jiang, Alistair.Francis, palmer, fanliang, wu.wubin,
dengkai1
Add the support needed for creating prstatus elf notes. Now elf notes
only contains user_regs. This allows us to use QMP dump-guest-memory.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
---
target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 4 +
target/riscv/cpu_bits.h | 1 +
target/riscv/meson.build | 1 +
5 files changed, 210 insertions(+)
create mode 100644 target/riscv/arch_dump.c
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
new file mode 100644
index 0000000000..6ad8f25920
--- /dev/null
+++ b/target/riscv/arch_dump.c
@@ -0,0 +1,202 @@
+/* Support for writing ELF notes for RISC-V architectures
+ *
+ * Copyright (C) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "elf.h"
+#include "sysemu/dump.h"
+
+/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */
+struct riscv64_user_regs {
+ uint64_t pc;
+ uint64_t regs[31];
+} QEMU_PACKED;
+
+QEMU_BUILD_BUG_ON(sizeof(struct riscv64_user_regs) != 256);
+
+/* struct elf_prstatus from include/uapi/linux/elfcore.h */
+struct riscv64_elf_prstatus {
+ char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */
+ uint32_t pr_pid;
+ char pad2[76]; /* 76 == offsetof(struct elf_prstatus, pr_reg) -
+ offsetof(struct elf_prstatus, pr_ppid) */
+ struct riscv64_user_regs pr_reg;
+ char pad3[8];
+} QEMU_PACKED;
+
+QEMU_BUILD_BUG_ON(sizeof(struct riscv64_elf_prstatus) != 376);
+
+struct riscv64_note {
+ Elf64_Nhdr hdr;
+ char name[8]; /* align_up(sizeof("CORE"), 4) */
+ struct riscv64_elf_prstatus prstatus;
+} QEMU_PACKED;
+
+#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus)
+#define RISCV64_PRSTATUS_NOTE_SIZE \
+ (RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus))
+
+static void riscv64_note_init(struct riscv64_note *note, DumpState *s,
+ const char *name, Elf64_Word namesz,
+ Elf64_Word type, Elf64_Word descsz)
+{
+ memset(note, 0, sizeof(*note));
+
+ note->hdr.n_namesz = cpu_to_dump32(s, namesz);
+ note->hdr.n_descsz = cpu_to_dump32(s, descsz);
+ note->hdr.n_type = cpu_to_dump32(s, type);
+
+ memcpy(note->name, name, namesz);
+}
+
+int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
+ int cpuid, void *opaque)
+{
+ struct riscv64_note note;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ DumpState *s = opaque;
+ int ret, i = 0;
+ const char name[] = "CORE";
+
+ riscv64_note_init(¬e, s, name, sizeof(name),
+ NT_PRSTATUS, sizeof(note.prstatus));
+
+ note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
+
+ note.prstatus.pr_reg.pc = cpu_to_dump64(s, env->pc);
+
+ for (i = 0; i < 31; i++) {
+ note.prstatus.pr_reg.regs[i] = cpu_to_dump64(s, env->gpr[i + 1]);
+ }
+
+ ret = f(¬e, RISCV64_PRSTATUS_NOTE_SIZE, s);
+ if (ret < 0) {
+ return -1;
+ }
+
+ return ret;
+}
+
+struct riscv32_user_regs {
+ uint32_t pc;
+ uint32_t regs[31];
+} QEMU_PACKED;
+
+QEMU_BUILD_BUG_ON(sizeof(struct riscv32_user_regs) != 128);
+
+struct riscv32_elf_prstatus {
+ char pad1[24]; /* 24 == offsetof(struct elf_prstatus, pr_pid) */
+ uint32_t pr_pid;
+ char pad2[44]; /* 44 == offsetof(struct elf_prstatus, pr_reg) -
+ offsetof(struct elf_prstatus, pr_ppid) */
+ struct riscv32_user_regs pr_reg;
+ char pad3[4];
+} QEMU_PACKED;
+
+QEMU_BUILD_BUG_ON(sizeof(struct riscv32_elf_prstatus) != 204);
+
+struct riscv32_note {
+ Elf32_Nhdr hdr;
+ char name[8]; /* align_up(sizeof("CORE"), 4) */
+ struct riscv32_elf_prstatus prstatus;
+} QEMU_PACKED;
+
+#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus)
+#define RISCV32_PRSTATUS_NOTE_SIZE \
+ (RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus))
+
+static void riscv32_note_init(struct riscv32_note *note, DumpState *s,
+ const char *name, Elf32_Word namesz,
+ Elf32_Word type, Elf32_Word descsz)
+{
+ memset(note, 0, sizeof(*note));
+
+ note->hdr.n_namesz = cpu_to_dump32(s, namesz);
+ note->hdr.n_descsz = cpu_to_dump32(s, descsz);
+ note->hdr.n_type = cpu_to_dump32(s, type);
+
+ memcpy(note->name, name, namesz);
+}
+
+int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
+ int cpuid, void *opaque)
+{
+ struct riscv32_note note;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ DumpState *s = opaque;
+ int ret, i;
+ const char name[] = "CORE";
+
+ riscv32_note_init(¬e, s, name, sizeof(name),
+ NT_PRSTATUS, sizeof(note.prstatus));
+
+ note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
+
+ note.prstatus.pr_reg.pc = cpu_to_dump32(s, env->pc);
+
+ for (i = 0; i < 31; i++) {
+ note.prstatus.pr_reg.regs[i] = cpu_to_dump32(s, env->gpr[i + 1]);
+ }
+
+ ret = f(¬e, RISCV32_PRSTATUS_NOTE_SIZE, s);
+ if (ret < 0) {
+ return -1;
+ }
+
+ return ret;
+}
+
+int cpu_get_dump_info(ArchDumpInfo *info,
+ const GuestPhysBlockList *guest_phys_blocks)
+{
+ RISCVCPU *cpu;
+ CPURISCVState *env;
+
+ if (first_cpu == NULL) {
+ return -1;
+ }
+ cpu = RISCV_CPU(first_cpu);
+ env = &cpu->env;
+
+ info->d_machine = EM_RISCV;
+
+#if defined(TARGET_RISCV64)
+ info->d_class = ELFCLASS64;
+#else
+ info->d_class = ELFCLASS32;
+#endif
+
+ info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
+ ? ELFDATA2MSB : ELFDATA2LSB;
+
+ return 0;
+}
+
+ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
+{
+ size_t note_size;
+
+ if (class == ELFCLASS64) {
+ note_size = RISCV64_PRSTATUS_NOTE_SIZE;
+ } else {
+ note_size = RISCV32_PRSTATUS_NOTE_SIZE;
+ }
+
+ return note_size * nr_cpus;
+}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8227d7aea9..eebc35b53e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -591,6 +591,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ cc->write_elf64_note = riscv_cpu_write_elf64_note;
+ cc->write_elf32_note = riscv_cpu_write_elf32_note;
#endif
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6339e84819..2649949924 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -321,6 +321,10 @@ extern const char * const riscv_intr_names[];
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
void riscv_cpu_do_interrupt(CPUState *cpu);
+int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
+ int cpuid, void *opaque);
+int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
+ int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index b41e8836c3..24b2fa9b72 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -368,6 +368,7 @@
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_UBE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_MPP 0x00001800
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 14a5c62dac..88ab850682 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -26,6 +26,7 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
+ 'arch_dump.c',
'pmp.c',
'monitor.c',
'machine.c'
--
2.19.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
2021-01-15 1:28 ` [PATCH v3 1/1] " Yifei Jiang
@ 2021-01-15 2:12 ` Palmer Dabbelt
2021-01-15 14:45 ` Andrew Jones
1 sibling, 0 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2021-01-15 2:12 UTC (permalink / raw)
To: jiangyifei
Cc: drjones, qemu-riscv, zhang.zhanghailiang, sagark,
Bastian Koppelmann, qemu-devel, limingwang, Alistair Francis,
jiangyifei, fanliang, wu.wubin, dengkai1
On Thu, 14 Jan 2021 17:28:19 PST (-0800), jiangyifei@huawei.com wrote:
> Add the support needed for creating prstatus elf notes. Now elf notes
> only contains user_regs. This allows us to use QMP dump-guest-memory.
"Now elf notes only contains user_regs" sounds a bit odd. Also, I usually see
this as ELF.
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
> ---
> target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 4 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/meson.build | 1 +
> 5 files changed, 210 insertions(+)
> create mode 100644 target/riscv/arch_dump.c
>
> diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
> new file mode 100644
> index 0000000000..6ad8f25920
> --- /dev/null
> +++ b/target/riscv/arch_dump.c
> @@ -0,0 +1,202 @@
> +/* Support for writing ELF notes for RISC-V architectures
> + *
> + * Copyright (C) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "elf.h"
> +#include "sysemu/dump.h"
> +
> +/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */
> +struct riscv64_user_regs {
> + uint64_t pc;
> + uint64_t regs[31];
> +} QEMU_PACKED;
> +
> +QEMU_BUILD_BUG_ON(sizeof(struct riscv64_user_regs) != 256);
> +
> +/* struct elf_prstatus from include/uapi/linux/elfcore.h */
It's just include/linux/elfcore.h.
We don't have any ABI document that defines core dumps in RISC-V. That
shouldn't block this, as there's tons of stuff we don't have written down, but
this would be a good thing to put in the ELF psABI specification.
> +struct riscv64_elf_prstatus {
> + char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */
> + uint32_t pr_pid;
> + char pad2[76]; /* 76 == offsetof(struct elf_prstatus, pr_reg) -
> + offsetof(struct elf_prstatus, pr_ppid) */
> + struct riscv64_user_regs pr_reg;
> + char pad3[8];
> +} QEMU_PACKED;
> +
> +QEMU_BUILD_BUG_ON(sizeof(struct riscv64_elf_prstatus) != 376);
> +
> +struct riscv64_note {
> + Elf64_Nhdr hdr;
> + char name[8]; /* align_up(sizeof("CORE"), 4) */
> + struct riscv64_elf_prstatus prstatus;
> +} QEMU_PACKED;
> +
> +#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus)
> +#define RISCV64_PRSTATUS_NOTE_SIZE \
> + (RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus))
> +
> +static void riscv64_note_init(struct riscv64_note *note, DumpState *s,
> + const char *name, Elf64_Word namesz,
> + Elf64_Word type, Elf64_Word descsz)
> +{
> + memset(note, 0, sizeof(*note));
> +
> + note->hdr.n_namesz = cpu_to_dump32(s, namesz);
> + note->hdr.n_descsz = cpu_to_dump32(s, descsz);
> + note->hdr.n_type = cpu_to_dump32(s, type);
> +
> + memcpy(note->name, name, namesz);
> +}
> +
> +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
> + int cpuid, void *opaque)
> +{
> + struct riscv64_note note;
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + DumpState *s = opaque;
> + int ret, i = 0;
> + const char name[] = "CORE";
> +
> + riscv64_note_init(¬e, s, name, sizeof(name),
> + NT_PRSTATUS, sizeof(note.prstatus));
> +
> + note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
> +
> + note.prstatus.pr_reg.pc = cpu_to_dump64(s, env->pc);
> +
> + for (i = 0; i < 31; i++) {
> + note.prstatus.pr_reg.regs[i] = cpu_to_dump64(s, env->gpr[i + 1]);
> + }
> +
> + ret = f(¬e, RISCV64_PRSTATUS_NOTE_SIZE, s);
> + if (ret < 0) {
> + return -1;
> + }
> +
> + return ret;
> +}
> +
> +struct riscv32_user_regs {
> + uint32_t pc;
> + uint32_t regs[31];
> +} QEMU_PACKED;
> +
> +QEMU_BUILD_BUG_ON(sizeof(struct riscv32_user_regs) != 128);
> +
> +struct riscv32_elf_prstatus {
> + char pad1[24]; /* 24 == offsetof(struct elf_prstatus, pr_pid) */
> + uint32_t pr_pid;
> + char pad2[44]; /* 44 == offsetof(struct elf_prstatus, pr_reg) -
> + offsetof(struct elf_prstatus, pr_ppid) */
> + struct riscv32_user_regs pr_reg;
> + char pad3[4];
> +} QEMU_PACKED;
> +
> +QEMU_BUILD_BUG_ON(sizeof(struct riscv32_elf_prstatus) != 204);
> +
> +struct riscv32_note {
> + Elf32_Nhdr hdr;
> + char name[8]; /* align_up(sizeof("CORE"), 4) */
> + struct riscv32_elf_prstatus prstatus;
> +} QEMU_PACKED;
> +
> +#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus)
> +#define RISCV32_PRSTATUS_NOTE_SIZE \
> + (RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus))
> +
> +static void riscv32_note_init(struct riscv32_note *note, DumpState *s,
> + const char *name, Elf32_Word namesz,
> + Elf32_Word type, Elf32_Word descsz)
> +{
> + memset(note, 0, sizeof(*note));
> +
> + note->hdr.n_namesz = cpu_to_dump32(s, namesz);
> + note->hdr.n_descsz = cpu_to_dump32(s, descsz);
> + note->hdr.n_type = cpu_to_dump32(s, type);
> +
> + memcpy(note->name, name, namesz);
> +}
> +
> +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> + int cpuid, void *opaque)
> +{
> + struct riscv32_note note;
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> + DumpState *s = opaque;
> + int ret, i;
> + const char name[] = "CORE";
> +
> + riscv32_note_init(¬e, s, name, sizeof(name),
> + NT_PRSTATUS, sizeof(note.prstatus));
> +
> + note.prstatus.pr_pid = cpu_to_dump32(s, cpuid);
> +
> + note.prstatus.pr_reg.pc = cpu_to_dump32(s, env->pc);
> +
> + for (i = 0; i < 31; i++) {
> + note.prstatus.pr_reg.regs[i] = cpu_to_dump32(s, env->gpr[i + 1]);
> + }
> +
> + ret = f(¬e, RISCV32_PRSTATUS_NOTE_SIZE, s);
> + if (ret < 0) {
> + return -1;
> + }
> +
> + return ret;
> +}
> +
> +int cpu_get_dump_info(ArchDumpInfo *info,
> + const GuestPhysBlockList *guest_phys_blocks)
> +{
> + RISCVCPU *cpu;
> + CPURISCVState *env;
> +
> + if (first_cpu == NULL) {
> + return -1;
> + }
> + cpu = RISCV_CPU(first_cpu);
> + env = &cpu->env;
> +
> + info->d_machine = EM_RISCV;
> +
> +#if defined(TARGET_RISCV64)
> + info->d_class = ELFCLASS64;
> +#else
> + info->d_class = ELFCLASS32;
> +#endif
> +
> + info->d_endian = (env->mstatus & MSTATUS_UBE) != 0
> + ? ELFDATA2MSB : ELFDATA2LSB;
> +
> + return 0;
> +}
> +
> +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
> +{
> + size_t note_size;
> +
> + if (class == ELFCLASS64) {
> + note_size = RISCV64_PRSTATUS_NOTE_SIZE;
> + } else {
> + note_size = RISCV32_PRSTATUS_NOTE_SIZE;
> + }
> +
> + return note_size * nr_cpus;
> +}
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8227d7aea9..eebc35b53e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -591,6 +591,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> + cc->write_elf64_note = riscv_cpu_write_elf64_note;
> + cc->write_elf32_note = riscv_cpu_write_elf32_note;
> #endif
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6339e84819..2649949924 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -321,6 +321,10 @@ extern const char * const riscv_intr_names[];
>
> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
> void riscv_cpu_do_interrupt(CPUState *cpu);
> +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
> + int cpuid, void *opaque);
> +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> + int cpuid, void *opaque);
> int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
> int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index b41e8836c3..24b2fa9b72 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -368,6 +368,7 @@
> #define MSTATUS_MIE 0x00000008
> #define MSTATUS_UPIE 0x00000010
> #define MSTATUS_SPIE 0x00000020
> +#define MSTATUS_UBE 0x00000040
> #define MSTATUS_MPIE 0x00000080
> #define MSTATUS_SPP 0x00000100
> #define MSTATUS_MPP 0x00001800
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 14a5c62dac..88ab850682 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -26,6 +26,7 @@ riscv_ss.add(files(
>
> riscv_softmmu_ss = ss.source_set()
> riscv_softmmu_ss.add(files(
> + 'arch_dump.c',
> 'pmp.c',
> 'monitor.c',
> 'machine.c'
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Has anyone tested this with GDB?
Thanks!
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/1] target-riscv: support QMP dump-guest-memory
2021-01-15 1:28 ` [PATCH v3 1/1] " Yifei Jiang
2021-01-15 2:12 ` Palmer Dabbelt
@ 2021-01-15 14:45 ` Andrew Jones
1 sibling, 0 replies; 4+ messages in thread
From: Andrew Jones @ 2021-01-15 14:45 UTC (permalink / raw)
To: Yifei Jiang
Cc: qemu-riscv, sagark, limingwang, kbastian, qemu-devel,
Alistair.Francis, palmer, fanliang, dengkai1, wu.wubin,
zhang.zhanghailiang
On Fri, Jan 15, 2021 at 09:28:19AM +0800, Yifei Jiang wrote:
> Add the support needed for creating prstatus elf notes. Now elf notes
> only contains user_regs. This allows us to use QMP dump-guest-memory.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
> ---
> target/riscv/arch_dump.c | 202 +++++++++++++++++++++++++++++++++++++++
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 4 +
> target/riscv/cpu_bits.h | 1 +
> target/riscv/meson.build | 1 +
> 5 files changed, 210 insertions(+)
> create mode 100644 target/riscv/arch_dump.c
>
I gave my r-b on the last review and the only change in this version
is the suggestion I made. Anyway, here's my r-b again
Reviewed-by: Andrew Jones <drjones@redhat.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-01-15 14:47 UTC | newest]
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2021-01-15 1:28 [PATCH v3 0/1] target-riscv: support QMP dump-guest-memory Yifei Jiang
2021-01-15 1:28 ` [PATCH v3 1/1] " Yifei Jiang
2021-01-15 2:12 ` Palmer Dabbelt
2021-01-15 14:45 ` Andrew Jones
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