* [PATCH] target/arm: Implement ID_PFR2
@ 2021-01-20 3:52 Richard Henderson
2021-01-20 19:04 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Richard Henderson @ 2021-01-20 3:52 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, alex.bennee
This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
I've pulled this out of a largely defunct 2019 branch. This will
be required for the cortex-a76. Aside from simplistic isar changes,
this is unchanged from its April 2019 review, so I did keep the r-b.
r~
---
target/arm/cpu.h | 1 +
target/arm/helper.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df0d677833..d080239863 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -922,6 +922,7 @@ struct ARMCPU {
uint32_t id_mmfr4;
uint32_t id_pfr0;
uint32_t id_pfr1;
+ uint32_t id_pfr2;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 10102aab3c..677a4aa79e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7671,11 +7671,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
.resetvalue = 0 },
- { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+ { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = 0 },
+ .resetvalue = cpu->isar.id_pfr2 },
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/arm: Implement ID_PFR2
2021-01-20 3:52 [PATCH] target/arm: Implement ID_PFR2 Richard Henderson
@ 2021-01-20 19:04 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2021-01-20 19:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, alex.bennee
On 1/19/21 5:52 PM, Richard Henderson wrote:
> This was defined at some point before ARMv8.4, and will
> shortly be used by new processor descriptions.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>
> I've pulled this out of a largely defunct 2019 branch. This will
> be required for the cortex-a76. Aside from simplistic isar changes,
> this is unchanged from its April 2019 review, so I did keep the r-b.
>
Ho hum, the patch is missing the change to kvm64 to pull the value out of the
test vm.
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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