* [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
2021-01-22 12:29 [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Bin Meng
@ 2021-01-22 12:29 ` Bin Meng
2021-01-22 21:22 ` Alistair Francis
2021-01-25 17:41 ` Philippe Mathieu-Daudé
2021-01-22 12:29 ` [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Bin Meng
` (3 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Bin Meng @ 2021-01-22 12:29 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
There is already a MemMapEntry type defined in hwaddr.h. Let's drop
the RISC-V defined `struct MemmapEntry` and use the existing one.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/microchip_pfsoc.c | 9 +++------
hw/riscv/opentitan.c | 9 +++------
hw/riscv/sifive_e.c | 9 +++------
hw/riscv/sifive_u.c | 11 ++++-------
hw/riscv/spike.c | 9 +++------
hw/riscv/virt.c | 9 +++------
6 files changed, 19 insertions(+), 37 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e952b49e8c..266f1c3342 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -86,10 +86,7 @@
* - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
* describes the complete IOSCB modules memory maps
*/
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} microchip_pfsoc_memmap[] = {
+static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
[MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
@@ -182,7 +179,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
- const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+ const MemMapEntry *memmap = microchip_pfsoc_memmap;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
@@ -451,7 +448,7 @@ type_init(microchip_pfsoc_soc_register_types)
static void microchip_icicle_kit_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
- const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+ const MemMapEntry *memmap = microchip_pfsoc_memmap;
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mem_low = g_new(MemoryRegion, 1);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index af3456932f..e168bffe69 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -28,10 +28,7 @@
#include "qemu/units.h"
#include "sysemu/sysemu.h"
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} ibex_memmap[] = {
+static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
[IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
@@ -66,7 +63,7 @@ static const struct MemmapEntry {
static void opentitan_board_init(MachineState *machine)
{
- const struct MemmapEntry *memmap = ibex_memmap;
+ const MemMapEntry *memmap = ibex_memmap;
OpenTitanState *s = g_new0(OpenTitanState, 1);
MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
@@ -114,7 +111,7 @@ static void lowrisc_ibex_soc_init(Object *obj)
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
- const struct MemmapEntry *memmap = ibex_memmap;
+ const MemMapEntry *memmap = ibex_memmap;
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 59bac4cc9a..f939bcf9ea 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -50,10 +50,7 @@
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} sifive_e_memmap[] = {
+static MemMapEntry sifive_e_memmap[] = {
[SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
[SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
@@ -77,7 +74,7 @@ static const struct MemmapEntry {
static void sifive_e_machine_init(MachineState *machine)
{
- const struct MemmapEntry *memmap = sifive_e_memmap;
+ const MemMapEntry *memmap = sifive_e_memmap;
SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory();
@@ -187,7 +184,7 @@ static void sifive_e_soc_init(Object *obj)
static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
- const struct MemmapEntry *memmap = sifive_e_memmap;
+ const MemMapEntry *memmap = sifive_e_memmap;
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 59b61cea01..51e4132fc4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -60,10 +60,7 @@
#include <libfdt.h>
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} sifive_u_memmap[] = {
+static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
[SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
@@ -86,7 +83,7 @@ static const struct MemmapEntry {
#define OTP_SERIAL 1
#define GEM_REVISION 0x10070109
-static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
+static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -428,7 +425,7 @@ static void sifive_u_machine_reset(void *opaque, int n, int level)
static void sifive_u_machine_init(MachineState *machine)
{
- const struct MemmapEntry *memmap = sifive_u_memmap;
+ const MemMapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
@@ -686,7 +683,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(dev);
- const struct MemmapEntry *memmap = sifive_u_memmap;
+ const MemMapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 56986ecfe0..ed4ca9808e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -43,16 +43,13 @@
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} spike_memmap[] = {
+static const MemMapEntry spike_memmap[] = {
[SPIKE_MROM] = { 0x1000, 0xf000 },
[SPIKE_CLINT] = { 0x2000000, 0x10000 },
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
-static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
+static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
{
void *fdt;
@@ -179,7 +176,7 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
static void spike_board_init(MachineState *machine)
{
- const struct MemmapEntry *memmap = spike_memmap;
+ const MemMapEntry *memmap = spike_memmap;
SpikeState *s = SPIKE_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2299b3a6be..cfd52bc59b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -43,10 +43,7 @@
#include "hw/pci/pci.h"
#include "hw/pci-host/gpex.h"
-static const struct MemmapEntry {
- hwaddr base;
- hwaddr size;
-} virt_memmap[] = {
+static const MemMapEntry virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
[VIRT_MROM] = { 0x1000, 0xf000 },
[VIRT_TEST] = { 0x100000, 0x1000 },
@@ -170,7 +167,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
0x1800, 0, 0, 0x7);
}
-static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
+static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
uint64_t mem_size, const char *cmdline, bool is_32_bit)
{
void *fdt;
@@ -490,7 +487,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
static void virt_machine_init(MachineState *machine)
{
- const struct MemmapEntry *memmap = virt_memmap;
+ const MemMapEntry *memmap = virt_memmap;
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
2021-01-22 12:29 ` [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry' Bin Meng
@ 2021-01-22 21:22 ` Alistair Francis
2021-01-25 17:41 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-22 21:22 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Jan 22, 2021 at 4:31 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is already a MemMapEntry type defined in hwaddr.h. Let's drop
> the RISC-V defined `struct MemmapEntry` and use the existing one.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/microchip_pfsoc.c | 9 +++------
> hw/riscv/opentitan.c | 9 +++------
> hw/riscv/sifive_e.c | 9 +++------
> hw/riscv/sifive_u.c | 11 ++++-------
> hw/riscv/spike.c | 9 +++------
> hw/riscv/virt.c | 9 +++------
> 6 files changed, 19 insertions(+), 37 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e952b49e8c..266f1c3342 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -86,10 +86,7 @@
> * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
> * describes the complete IOSCB modules memory maps
> */
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} microchip_pfsoc_memmap[] = {
> +static const MemMapEntry microchip_pfsoc_memmap[] = {
> [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
> [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
> [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
> @@ -182,7 +179,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
> - const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> + const MemMapEntry *memmap = microchip_pfsoc_memmap;
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> @@ -451,7 +448,7 @@ type_init(microchip_pfsoc_soc_register_types)
> static void microchip_icicle_kit_machine_init(MachineState *machine)
> {
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> - const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> + const MemMapEntry *memmap = microchip_pfsoc_memmap;
> MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mem_low = g_new(MemoryRegion, 1);
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index af3456932f..e168bffe69 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -28,10 +28,7 @@
> #include "qemu/units.h"
> #include "sysemu/sysemu.h"
>
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} ibex_memmap[] = {
> +static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB },
> [IBEX_DEV_RAM] = { 0x10000000, 0x10000 },
> [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
> @@ -66,7 +63,7 @@ static const struct MemmapEntry {
>
> static void opentitan_board_init(MachineState *machine)
> {
> - const struct MemmapEntry *memmap = ibex_memmap;
> + const MemMapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> MemoryRegion *sys_mem = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> @@ -114,7 +111,7 @@ static void lowrisc_ibex_soc_init(Object *obj)
>
> static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> - const struct MemmapEntry *memmap = ibex_memmap;
> + const MemMapEntry *memmap = ibex_memmap;
> MachineState *ms = MACHINE(qdev_get_machine());
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
> MemoryRegion *sys_mem = get_system_memory();
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 59bac4cc9a..f939bcf9ea 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -50,10 +50,7 @@
> #include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
>
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} sifive_e_memmap[] = {
> +static MemMapEntry sifive_e_memmap[] = {
> [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
> [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
> [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
> @@ -77,7 +74,7 @@ static const struct MemmapEntry {
>
> static void sifive_e_machine_init(MachineState *machine)
> {
> - const struct MemmapEntry *memmap = sifive_e_memmap;
> + const MemMapEntry *memmap = sifive_e_memmap;
>
> SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -187,7 +184,7 @@ static void sifive_e_soc_init(Object *obj)
> static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> - const struct MemmapEntry *memmap = sifive_e_memmap;
> + const MemMapEntry *memmap = sifive_e_memmap;
> SiFiveESoCState *s = RISCV_E_SOC(dev);
> MemoryRegion *sys_mem = get_system_memory();
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 59b61cea01..51e4132fc4 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -60,10 +60,7 @@
>
> #include <libfdt.h>
>
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} sifive_u_memmap[] = {
> +static const MemMapEntry sifive_u_memmap[] = {
> [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
> [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
> [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
> @@ -86,7 +83,7 @@ static const struct MemmapEntry {
> #define OTP_SERIAL 1
> #define GEM_REVISION 0x10070109
>
> -static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> +static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
> uint64_t mem_size, const char *cmdline, bool is_32_bit)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -428,7 +425,7 @@ static void sifive_u_machine_reset(void *opaque, int n, int level)
>
> static void sifive_u_machine_init(MachineState *machine)
> {
> - const struct MemmapEntry *memmap = sifive_u_memmap;
> + const MemMapEntry *memmap = sifive_u_memmap;
> SiFiveUState *s = RISCV_U_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> @@ -686,7 +683,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> SiFiveUSoCState *s = RISCV_U_SOC(dev);
> - const struct MemmapEntry *memmap = sifive_u_memmap;
> + const MemMapEntry *memmap = sifive_u_memmap;
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 56986ecfe0..ed4ca9808e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -43,16 +43,13 @@
> #include "sysemu/qtest.h"
> #include "sysemu/sysemu.h"
>
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} spike_memmap[] = {
> +static const MemMapEntry spike_memmap[] = {
> [SPIKE_MROM] = { 0x1000, 0xf000 },
> [SPIKE_CLINT] = { 0x2000000, 0x10000 },
> [SPIKE_DRAM] = { 0x80000000, 0x0 },
> };
>
> -static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
> +static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
> uint64_t mem_size, const char *cmdline, bool is_32_bit)
> {
> void *fdt;
> @@ -179,7 +176,7 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
>
> static void spike_board_init(MachineState *machine)
> {
> - const struct MemmapEntry *memmap = spike_memmap;
> + const MemMapEntry *memmap = spike_memmap;
> SpikeState *s = SPIKE_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2299b3a6be..cfd52bc59b 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -43,10 +43,7 @@
> #include "hw/pci/pci.h"
> #include "hw/pci-host/gpex.h"
>
> -static const struct MemmapEntry {
> - hwaddr base;
> - hwaddr size;
> -} virt_memmap[] = {
> +static const MemMapEntry virt_memmap[] = {
> [VIRT_DEBUG] = { 0x0, 0x100 },
> [VIRT_MROM] = { 0x1000, 0xf000 },
> [VIRT_TEST] = { 0x100000, 0x1000 },
> @@ -170,7 +167,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
> 0x1800, 0, 0, 0x7);
> }
>
> -static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
> +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
> uint64_t mem_size, const char *cmdline, bool is_32_bit)
> {
> void *fdt;
> @@ -490,7 +487,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
>
> static void virt_machine_init(MachineState *machine)
> {
> - const struct MemmapEntry *memmap = virt_memmap;
> + const MemMapEntry *memmap = virt_memmap;
> RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry'
2021-01-22 12:29 ` [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry' Bin Meng
2021-01-22 21:22 ` Alistair Francis
@ 2021-01-25 17:41 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-25 17:41 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
On 1/22/21 1:29 PM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> There is already a MemMapEntry type defined in hwaddr.h. Let's drop
> the RISC-V defined `struct MemmapEntry` and use the existing one.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/microchip_pfsoc.c | 9 +++------
> hw/riscv/opentitan.c | 9 +++------
> hw/riscv/sifive_e.c | 9 +++------
> hw/riscv/sifive_u.c | 11 ++++-------
> hw/riscv/spike.c | 9 +++------
> hw/riscv/virt.c | 9 +++------
> 6 files changed, 19 insertions(+), 37 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
2021-01-22 12:29 [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Bin Meng
2021-01-22 12:29 ` [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry' Bin Meng
@ 2021-01-22 12:29 ` Bin Meng
2021-01-22 21:22 ` Alistair Francis
2021-01-22 12:29 ` [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system Bin Meng
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Bin Meng @ 2021-01-22 12:29 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
`link_up` is never used in gpex_pcie_init(). Drop it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/virt.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cfd52bc59b..1d05bb3ef9 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -449,7 +449,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
hwaddr ecam_base, hwaddr ecam_size,
hwaddr mmio_base, hwaddr mmio_size,
hwaddr pio_base,
- DeviceState *plic, bool link_up)
+ DeviceState *plic)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
@@ -669,12 +669,12 @@ static void virt_machine_init(MachineState *machine)
}
gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- memmap[VIRT_PCIE_PIO].base,
- DEVICE(pcie_plic), true);
+ memmap[VIRT_PCIE_ECAM].base,
+ memmap[VIRT_PCIE_ECAM].size,
+ memmap[VIRT_PCIE_MMIO].base,
+ memmap[VIRT_PCIE_MMIO].size,
+ memmap[VIRT_PCIE_PIO].base,
+ DEVICE(pcie_plic));
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
2021-01-22 12:29 ` [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Bin Meng
@ 2021-01-22 21:22 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-22 21:22 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Jan 22, 2021 at 4:32 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> `link_up` is never used in gpex_pcie_init(). Drop it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/virt.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index cfd52bc59b..1d05bb3ef9 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -449,7 +449,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> hwaddr ecam_base, hwaddr ecam_size,
> hwaddr mmio_base, hwaddr mmio_size,
> hwaddr pio_base,
> - DeviceState *plic, bool link_up)
> + DeviceState *plic)
> {
> DeviceState *dev;
> MemoryRegion *ecam_alias, *ecam_reg;
> @@ -669,12 +669,12 @@ static void virt_machine_init(MachineState *machine)
> }
>
> gpex_pcie_init(system_memory,
> - memmap[VIRT_PCIE_ECAM].base,
> - memmap[VIRT_PCIE_ECAM].size,
> - memmap[VIRT_PCIE_MMIO].base,
> - memmap[VIRT_PCIE_MMIO].size,
> - memmap[VIRT_PCIE_PIO].base,
> - DEVICE(pcie_plic), true);
> + memmap[VIRT_PCIE_ECAM].base,
> + memmap[VIRT_PCIE_ECAM].size,
> + memmap[VIRT_PCIE_MMIO].base,
> + memmap[VIRT_PCIE_MMIO].size,
> + memmap[VIRT_PCIE_PIO].base,
> + DEVICE(pcie_plic));
>
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
2021-01-22 12:29 [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Bin Meng
2021-01-22 12:29 ` [PATCH 1/4] hw/riscv: Drop 'struct MemmapEntry' Bin Meng
2021-01-22 12:29 ` [PATCH 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Bin Meng
@ 2021-01-22 12:29 ` Bin Meng
2021-01-22 21:26 ` Alistair Francis
2021-01-22 12:29 ` [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe Bin Meng
2021-02-12 22:05 ` [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Alistair Francis
4 siblings, 1 reply; 11+ messages in thread
From: Bin Meng @ 2021-01-22 12:29 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
RV32 supports 34-bit physical address hence the maximum RAM size
should be limitted. Limit the RAM size to 10 GiB, which leaves
some room for PCIe high mmio space.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/virt.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1d05bb3ef9..4f44509360 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -590,6 +590,19 @@ static void virt_machine_init(MachineState *machine)
}
}
+ /* limit RAM size in a 32-bit system */
+ if (riscv_is_32bit(&s->soc[0])) {
+ /*
+ * Cast machine->ram_size to 64-bit for 32-bit host,
+ * to make the build on 32-bit host happy.
+ */
+ if ((uint64_t)(machine->ram_size) > 10 * GiB) {
+ /* 32-bit host won't have a chance to execute here */
+ machine->ram_size = 10 * GiB;
+ error_report("Limitting RAM size to 10 GiB");
+ }
+ }
+
/* register system main memory (actual RAM) */
memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
machine->ram_size, &error_fatal);
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system
2021-01-22 12:29 ` [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system Bin Meng
@ 2021-01-22 21:26 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-22 21:26 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Jan 22, 2021 at 4:34 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> RV32 supports 34-bit physical address hence the maximum RAM size
> should be limitted. Limit the RAM size to 10 GiB, which leaves
> some room for PCIe high mmio space.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/virt.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 1d05bb3ef9..4f44509360 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -590,6 +590,19 @@ static void virt_machine_init(MachineState *machine)
> }
> }
>
> + /* limit RAM size in a 32-bit system */
> + if (riscv_is_32bit(&s->soc[0])) {
> + /*
> + * Cast machine->ram_size to 64-bit for 32-bit host,
> + * to make the build on 32-bit host happy.
> + */
> + if ((uint64_t)(machine->ram_size) > 10 * GiB) {
> + /* 32-bit host won't have a chance to execute here */
> + machine->ram_size = 10 * GiB;
> + error_report("Limitting RAM size to 10 GiB");
> + }
> + }
> +
> /* register system main memory (actual RAM) */
> memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
> machine->ram_size, &error_fatal);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe
2021-01-22 12:29 [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Bin Meng
` (2 preceding siblings ...)
2021-01-22 12:29 ` [PATCH 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system Bin Meng
@ 2021-01-22 12:29 ` Bin Meng
2021-02-12 21:47 ` Alistair Francis
2021-02-12 22:05 ` [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Alistair Francis
4 siblings, 1 reply; 11+ messages in thread
From: Bin Meng @ 2021-01-22 12:29 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Some peripherals require 64-bit PCI address, so let's map the high
mmio space for PCIe.
For RV32, the address is hardcoded to below 4 GiB from the highest
accessible physical address. For RV64, the base address depends on
top of RAM and is aligned to its size which is using 16 GiB for now.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/virt.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4f44509360..4ab3b35cc7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_DRAM] = { 0x80000000, 0x0 },
};
+/* PCIe high mmio is fixed for RV32 */
+#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
+#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
+
+/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
+#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
+
+static MemMapEntry virt_high_pcie_memmap;
+
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
@@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
1, FDT_PCI_RANGE_MMIO,
2, memmap[VIRT_PCIE_MMIO].base,
- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
+ 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
+ 1, FDT_PCI_RANGE_MMIO_64BIT,
+ 2, virt_high_pcie_memmap.base,
+ 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
+
create_pcie_irq_map(fdt, name, plic_pcie_phandle);
g_free(name);
@@ -448,12 +461,14 @@ update_bootargs:
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
hwaddr ecam_base, hwaddr ecam_size,
hwaddr mmio_base, hwaddr mmio_size,
+ hwaddr high_mmio_base,
+ hwaddr high_mmio_size,
hwaddr pio_base,
DeviceState *plic)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
- MemoryRegion *mmio_alias, *mmio_reg;
+ MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
qemu_irq irq;
int i;
@@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
mmio_reg, mmio_base, mmio_size);
memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
+ /* Map high MMIO space */
+ high_mmio_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
+ mmio_reg, high_mmio_base, high_mmio_size);
+ memory_region_add_subregion(get_system_memory(), high_mmio_base,
+ high_mmio_alias);
+
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
@@ -601,6 +623,14 @@ static void virt_machine_init(MachineState *machine)
machine->ram_size = 10 * GiB;
error_report("Limitting RAM size to 10 GiB");
}
+
+ virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
+ virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
+ } else {
+ virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
+ virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
+ virt_high_pcie_memmap.base =
+ ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
}
/* register system main memory (actual RAM) */
@@ -686,6 +716,8 @@ static void virt_machine_init(MachineState *machine)
memmap[VIRT_PCIE_ECAM].size,
memmap[VIRT_PCIE_MMIO].base,
memmap[VIRT_PCIE_MMIO].size,
+ virt_high_pcie_memmap.base,
+ virt_high_pcie_memmap.size,
memmap[VIRT_PCIE_PIO].base,
DEVICE(pcie_plic));
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe
2021-01-22 12:29 ` [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe Bin Meng
@ 2021-02-12 21:47 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-02-12 21:47 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Jan 22, 2021 at 4:35 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Some peripherals require 64-bit PCI address, so let's map the high
> mmio space for PCIe.
>
> For RV32, the address is hardcoded to below 4 GiB from the highest
> accessible physical address. For RV64, the base address depends on
> top of RAM and is aligned to its size which is using 16 GiB for now.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> hw/riscv/virt.c | 36 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 4f44509360..4ab3b35cc7 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] = {
> [VIRT_DRAM] = { 0x80000000, 0x0 },
> };
>
> +/* PCIe high mmio is fixed for RV32 */
> +#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
> +#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
> +
> +/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
> +#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
> +
> +static MemMapEntry virt_high_pcie_memmap;
> +
> #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
>
> static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
> @@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
> 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
> 1, FDT_PCI_RANGE_MMIO,
> 2, memmap[VIRT_PCIE_MMIO].base,
> - 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
> + 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
> + 1, FDT_PCI_RANGE_MMIO_64BIT,
> + 2, virt_high_pcie_memmap.base,
> + 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
> +
> create_pcie_irq_map(fdt, name, plic_pcie_phandle);
> g_free(name);
>
> @@ -448,12 +461,14 @@ update_bootargs:
> static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> hwaddr ecam_base, hwaddr ecam_size,
> hwaddr mmio_base, hwaddr mmio_size,
> + hwaddr high_mmio_base,
> + hwaddr high_mmio_size,
> hwaddr pio_base,
> DeviceState *plic)
> {
> DeviceState *dev;
> MemoryRegion *ecam_alias, *ecam_reg;
> - MemoryRegion *mmio_alias, *mmio_reg;
> + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
> qemu_irq irq;
> int i;
>
> @@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> mmio_reg, mmio_base, mmio_size);
> memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
>
> + /* Map high MMIO space */
> + high_mmio_alias = g_new0(MemoryRegion, 1);
> + memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
> + mmio_reg, high_mmio_base, high_mmio_size);
> + memory_region_add_subregion(get_system_memory(), high_mmio_base,
> + high_mmio_alias);
> +
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
>
> for (i = 0; i < GPEX_NUM_IRQS; i++) {
> @@ -601,6 +623,14 @@ static void virt_machine_init(MachineState *machine)
> machine->ram_size = 10 * GiB;
> error_report("Limitting RAM size to 10 GiB");
> }
> +
> + virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
> + virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
> + } else {
> + virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
> + virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
> + virt_high_pcie_memmap.base =
> + ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
> }
>
> /* register system main memory (actual RAM) */
> @@ -686,6 +716,8 @@ static void virt_machine_init(MachineState *machine)
> memmap[VIRT_PCIE_ECAM].size,
> memmap[VIRT_PCIE_MMIO].base,
> memmap[VIRT_PCIE_MMIO].size,
> + virt_high_pcie_memmap.base,
> + virt_high_pcie_memmap.size,
> memmap[VIRT_PCIE_PIO].base,
> DEVICE(pcie_plic));
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine
2021-01-22 12:29 [PATCH 0/4] hw/riscv: Clean-ups and map high mmio for PCIe of 'virt' machine Bin Meng
` (3 preceding siblings ...)
2021-01-22 12:29 ` [PATCH 4/4] hw/riscv: virt: Map high mmio for PCIe Bin Meng
@ 2021-02-12 22:05 ` Alistair Francis
4 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-02-12 22:05 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Bin Meng, Alistair Francis,
qemu-devel@nongnu.org Developers
On Fri, Jan 22, 2021 at 4:32 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This series does the following clean-ups:
> - Drop 'struct MemmapEntry'
> - virt: Drop the 'link_up' parameter of gpex_pcie_init()
>
> It also adds the following small enhancement to 'virt' machine:
> - Limit RAM size in a 32-bit system
> - Map high mmio for PCIe
>
>
> Bin Meng (4):
> hw/riscv: Drop 'struct MemmapEntry'
> hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
> hw/riscv: virt: Limit RAM size in a 32-bit system
> hw/riscv: virt: Map high mmio for PCIe
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/riscv/microchip_pfsoc.c | 9 ++---
> hw/riscv/opentitan.c | 9 ++---
> hw/riscv/sifive_e.c | 9 ++---
> hw/riscv/sifive_u.c | 11 +++---
> hw/riscv/spike.c | 9 ++---
> hw/riscv/virt.c | 72 ++++++++++++++++++++++++++++++--------
> 6 files changed, 73 insertions(+), 46 deletions(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread