From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <qemu-devel@nongnu.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Thomas Huth <thuth@redhat.com>,
Ben Widawsky <ben.widawsky@intel.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>,
f.fangjian@huawei.com, Chris Browy <cbrowy@avery-design.com>,
f4bug@amsat.org, linuxarm@openeuler.org, jcm@redhat.com,
Prashant V Agarwal <agpr123@gmail.com>,
Igor Mammedov <imammedo@redhat.com>,
Dan Williams <dan.j.williams@intel.com>,
Richard Henderson <richard.henderson@linaro.org>,
alex.bennee@linaro.org
Subject: [RFC PATCH 1/3] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl
Date: Mon, 1 Feb 2021 23:26:53 +0800 [thread overview]
Message-ID: <20210201152655.31027-2-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20210201152655.31027-1-Jonathan.Cameron@huawei.com>
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/pci-host/gpex-acpi.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 446912d771..58f67ee4b0 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -5,6 +5,7 @@
#include "hw/pci/pci_bus.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie_host.h"
+#include "hw/acpi/cxl.h"
static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
{
@@ -155,6 +156,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
QLIST_FOREACH(bus, &bus->child, sibling) {
uint8_t bus_num = pci_bus_num(bus);
uint8_t numa_node = pci_bus_numa_node(bus);
+ bool is_cxl;
if (!pci_bus_is_root(bus)) {
continue;
@@ -169,9 +171,19 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
nr_pcie_buses = bus_num;
}
+ is_cxl = pci_bus_is_cxl(bus);
+
dev = aml_device("PC%.02X", bus_num);
- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
- aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ if (is_cxl) {
+ struct Aml *pkg = aml_package(2);
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
+ aml_append(pkg, aml_eisaid("PNP0A08"));
+ aml_append(pkg, aml_eisaid("PNP0A03"));
+ aml_append(dev, aml_name_decl("_CID", pkg));
+ } else {
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ }
aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
@@ -190,7 +202,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
cfg->pio.base, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
- acpi_dsdt_add_pci_osc(dev);
+ if (is_cxl) {
+ build_cxl_osc_method(dev);
+ } else {
+ acpi_dsdt_add_pci_osc(dev);
+ }
aml_append(scope, dev);
}
--
2.19.1
next prev parent reply other threads:[~2021-02-01 15:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 15:26 [RFC PATCH 0/3] hw/arm/virt: CXL enablement including gpex-acpi Jonathan Cameron
2021-02-01 15:26 ` Jonathan Cameron [this message]
2021-02-01 15:26 ` [RFC PATCH 2/3] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2021-02-01 15:26 ` [RFC PATCH 3/3] hw/cxl/cxl-device-utils: Allow incorrect read lengths Jonathan Cameron
2021-02-03 16:10 ` Ben Widawsky
2021-02-03 17:26 ` Jonathan Cameron
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