From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
"Xuzhou Cheng" <xuzhou.cheng@windriver.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-devel@nongnu.org,
"Francisco Iglesias" <francisco.iglesias@xilinx.com>,
qemu-arm@nongnu.org
Subject: [RESEND PATCH v4 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues
Date: Mon, 22 Feb 2021 21:15:01 +0800 [thread overview]
Message-ID: <20210222131502.3098-5-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210222131502.3098-1-bmeng.cn@gmail.com>
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
There are some coding convention warnings in xilinx_spips.c,
as reported by:
$ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
(no changes since v1)
hw/ssi/xilinx_spips.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index a897034601..8a0cc22d42 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -176,7 +176,8 @@
FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1)
#define R_GQSPI_GFIFO_THRESH (0x150 / 4)
#define R_GQSPI_DATA_STS (0x15c / 4)
-/* We use the snapshot register to hold the core state for the currently
+/*
+ * We use the snapshot register to hold the core state for the currently
* or most recently executed command. So the generic fifo format is defined
* for the snapshot register
*/
@@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
xlnx_zynqmp_qspips_update_ixr(s);
}
-/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
+/*
+ * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
* column wise (from element 0 to N-1). num is the length of x, and dir
* reverses the direction of the transform. Best illustrated by example:
* Each digit in the below array is a single bit (num == 3):
@@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
tx_rx[i] = tx;
}
} else {
- /* Extract a dummy byte and generate dummy cycles according to the
- * link state */
+ /*
+ * Extract a dummy byte and generate dummy cycles according to the
+ * link state
+ */
tx = fifo8_pop(&s->tx_fifo);
dummy_cycles = 8 / s->link_state;
}
@@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
}
break;
case (SNOOP_ADDR):
- /* Address has been transmitted, transmit dummy cycles now if
- * needed */
+ /*
+ * Address has been transmitted, transmit dummy cycles now if needed
+ */
if (s->cmd_dummies < 0) {
s->snoop_state = SNOOP_NONE;
} else {
@@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque)
}
static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
- unsigned size)
+ unsigned size)
{
XilinxSPIPS *s = opaque;
uint32_t mask = ~0;
@@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque,
}
static void xilinx_spips_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
+ uint64_t value, unsigned size)
{
int mask = ~0;
XilinxSPIPS *s = opaque;
@@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr,
}
static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size)
+ uint64_t value, unsigned size)
{
XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
uint32_t reg = addr / 4;
--
2.25.1
next prev parent reply other threads:[~2021-02-22 13:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 13:14 [RESEND PATCH v4 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Bin Meng
2021-02-22 13:14 ` [RESEND PATCH v4 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model Bin Meng
2021-02-22 13:14 ` [RESEND PATCH v4 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Bin Meng
2021-02-22 13:15 ` [RESEND PATCH v4 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI Bin Meng
2021-02-23 9:24 ` Edgar E. Iglesias
2021-02-22 13:15 ` Bin Meng [this message]
2021-02-22 13:15 ` [RESEND PATCH v4 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Bin Meng
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