From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Xuzhou Cheng <xuzhou.cheng@windriver.com>,
Bin Meng <bin.meng@windriver.com>,
qemu-devel@nongnu.org,
Francisco Iglesias <francisco.iglesias@xilinx.com>,
qemu-arm@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [RESEND PATCH v4 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
Date: Tue, 23 Feb 2021 10:24:17 +0100 [thread overview]
Message-ID: <20210223092417.GW477672@toto> (raw)
In-Reply-To: <20210222131502.3098-4-bmeng.cn@gmail.com>
On Mon, Feb 22, 2021 at 09:15:00PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
>
> Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
> link of GQSPI to CSU DMA.
>
> Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> ---
> RESEND this patch to remove 2 blank lines that were accidently added
>
> Changes in v4:
> - Rename "csu_dma" to "qspi_dma"
>
> Changes in v3:
> - new patch: xlnx-zynqmp: Add XLNX CSU DMA module
>
> include/hw/arm/xlnx-zynqmp.h | 2 ++
> hw/arm/xlnx-zynqmp.c | 12 ++++++++++++
> hw/arm/Kconfig | 1 +
> 3 files changed, 15 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index be15cc8814..2edeed911c 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -35,6 +35,7 @@
> #include "target/arm/cpu.h"
> #include "qom/object.h"
> #include "net/can_emu.h"
> +#include "hw/dma/xlnx_csu_dma.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -108,6 +109,7 @@ struct XlnxZynqMPState {
> XlnxZynqMPRTC rtc;
> XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
> XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
> + XlnxCSUDMA qspi_dma;
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 49465a2794..76cc3b5e78 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -50,6 +50,7 @@
> #define QSPI_ADDR 0xff0f0000
> #define LQSPI_ADDR 0xc0000000
> #define QSPI_IRQ 15
> +#define QSPI_DMA_ADDR 0xff0f0800
>
> #define DP_ADDR 0xfd4a0000
> #define DP_IRQ 113
> @@ -284,6 +285,8 @@ static void xlnx_zynqmp_init(Object *obj)
> for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
> object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
> }
> +
> + object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
> }
>
> static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> @@ -643,6 +646,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
> gic_spi[adma_ch_intr[i]]);
> }
> +
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
> + object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
> + OBJECT(&s->qspi_dma), errp);
> }
>
> static Property xlnx_zynqmp_props[] = {
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 4e6f4ffe90..27ec10f89b 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -353,6 +353,7 @@ config XLNX_ZYNQMP_ARM
> select SSI_M25P80
> select XILINX_AXI
> select XILINX_SPIPS
> + select XLNX_CSU_DMA
> select XLNX_ZYNQMP
> select XLNX_ZDMA
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-02-23 9:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 13:14 [RESEND PATCH v4 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Bin Meng
2021-02-22 13:14 ` [RESEND PATCH v4 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model Bin Meng
2021-02-22 13:14 ` [RESEND PATCH v4 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Bin Meng
2021-02-22 13:15 ` [RESEND PATCH v4 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI Bin Meng
2021-02-23 9:24 ` Edgar E. Iglesias [this message]
2021-02-22 13:15 ` [RESEND PATCH v4 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Bin Meng
2021-02-22 13:15 ` [RESEND PATCH v4 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Bin Meng
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