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From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Frank Chang <frank.chang@sifive.com>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Date: Fri, 26 Feb 2021 11:18:40 +0800	[thread overview]
Message-ID: <20210226031902.23656-57-frank.chang@sifive.com> (raw)
In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com>

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/helper.h                   | 6 ------
 target/riscv/insn32.decode              | 2 --
 target/riscv/insn_trans/trans_rvv.c.inc | 2 --
 target/riscv/vector_helper.c            | 7 -------
 4 files changed, 17 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 24fdc4396bd..cdaa21b7008 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -943,12 +943,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
 DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
 
 DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
 DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0ac3329b3c0..2d96c53d066 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -557,8 +557,6 @@ vmfle_vv        011001 . ..... ..... 001 ..... 1010111 @r_vm
 vmfle_vf        011001 . ..... ..... 101 ..... 1010111 @r_vm
 vmfgt_vf        011101 . ..... ..... 101 ..... 1010111 @r_vm
 vmfge_vf        011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv       011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf       011010 . ..... ..... 101 ..... 1010111 @r_vm
 vfclass_v       010011 . ..... 10000 001 ..... 1010111 @r2_vm
 vfmerge_vfm     010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
 vfmv_v_f        010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4abafcd2edc..c3ec88e238c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2655,7 +2655,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
 GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
 GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
 GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
 
 static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
 {
@@ -2671,7 +2670,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
 GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
 GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
 GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
 
 /* Vector Floating-Point Classify Instruction */
 GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 549a476490e..c5e65720120 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3839,13 +3839,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
 GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
 GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
 
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
 /* Vector Floating-Point Classify Instruction */
 #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP)         \
 static void do_##NAME(void *vd, void *vs2, int i)      \
-- 
2.17.1



  parent reply	other threads:[~2021-02-26  3:57 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-26  3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
2021-02-26  3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-02-26  3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-02-26  3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-02-26  3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-02-26  3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-02-26  3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-02-26  3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-02-26  3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-02-26  3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-02-26  3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-02-26  3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-02-26  3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-02-26  3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-02-26  3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang
2021-02-26  3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-02-26  3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-02-26  3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang
2021-02-26  3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-02-26  3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-02-26  3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang
2021-02-26  3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-02-26  3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-02-26  3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-02-26  3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang
2021-02-26  3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-02-26  3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang
2021-02-26  3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-02-26  3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-02-26  3:18 ` frank.chang [this message]
2021-02-26  3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-02-26  3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-02-26  3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-02-26  3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-02-26  3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-02-26  3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-02-26  3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-02-26  3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-02-26  3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-02-26  3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-02-26  3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-02-26  3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-02-26  3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-02-26  3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-02-26  3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-02-26  3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang

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