From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum
Date: Fri, 26 Feb 2021 11:18:43 +0800 [thread overview]
Message-ID: <20210226031902.23656-60-frank.chang@sifive.com> (raw)
In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 7c4ab92ecbe..ad84aeebc1c 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == RISCV_FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case RISCV_FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case RISCV_FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case RISCV_FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case RISCV_FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case RISCV_FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index de7152dc323..3f453ed457a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2321,7 +2321,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2400,7 +2400,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2432,7 +2432,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2468,7 +2468,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2534,7 +2534,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2611,7 +2611,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2757,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2804,7 +2804,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 959b81b3016..469cc418c4e 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1);
extern const VMStateDescription vmstate_riscv_cpu;
#endif
+enum {
+ RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ RISCV_FRM_RTZ = 1, /* Round towards Zero */
+ RISCV_FRM_RDN = 2, /* Round Down */
+ RISCV_FRM_RUP = 3, /* Round Up */
+ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
next prev parent reply other threads:[~2021-02-26 3:57 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang
2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang
2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang
2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang
2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang
2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-02-26 3:18 ` frank.chang [this message]
2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
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